Claims
- 1. A ferroelectric memory cell comprising:
a ferroelectric capacitor including a bottom electrode, a ferroelectric layer formed on the bottom electrode and a top electrode formed on the ferroelectric layer; a high permittivity dielectric layer formed over the ferroelectric capacitor, wherein the high permittivity dielectric layer comprises an encapsulation layer and completely covers the top electrode; and a local interconnect electrode formed on the encapsulation layer.
- 2. The ferroelectric memory cell according to claim 1, wherein a dielectric permittivity of the encapsulation layer is 5 to 10 times larger than a dielectric permittivity of the ferroelectric layer.
- 3. The ferroelectric memory cell according to claim 1, wherein the ferroelectric layer includes a first PZT.
- 4. The ferroelectric memory cell according to claim 3, wherein the encapsulation layer includes a second PZT, and a Pb (lead) of the second PZT is lower than that of the first PZT.
- 5. The ferroelectric memory cell according to claim 3, wherein the encapsulation layer includes a second PZT, and the second PZT has a different concentration of Pb (lead), Zr (zirconate) or Ti (titanate) than that of the first PZT.
- 6. The ferroelectric memory cell according to claim 1, wherein the top electrode, the encapsulation layer and the local interconnect electrode comprise a second capacitor.
- 7. The ferroelectric memory cell according to claim 6, wherein a capacitance of the second capacitor is 5 to 10 times larger than a capacitance of the ferroelectric capacitor.
- 8. The ferroelectric memory cell according to claim 6, wherein the second capacitor has high charge storage capability.
- 9. The ferroelectric memory cell according to claim 1, further comprising a transistor, wherein the transistor is connected to the local interconnect electrode.
- 10. An integrated circuit comprising:
a ferroelectric capacitor including a bottom electrode, a ferroelectric layer formed on the bottom electrode and a top electrode formed on the ferroelectric layer; a high permittivity dielectric layer formed over the ferroelectric capacitor, wherein the high permittivity dielectric layer comprises an encapsulation layer and completely covers the top electrode; and a local interconnect electrode formed on the encapsulation layer.
- 11. The integrated circuit according to claim 10, wherein a dielectric permittivity of the encapsulation layer is 5 to 10 times larger than a dielectric permittivity of the ferroelectric layer.
- 12. The integrated circuit according to claim 10, wherein the top electrode, the encapsulation layer and the local interconnect electrode comprise a second capacitor.
- 13. The integrated circuit according to claim 12, wherein a capacitance of the second capacitor is 5 to 10 times larger than a capacitance of the ferroelectric capacitor.
- 14. A method for forming an integrated circuit comprising:
forming a bottom electrode; forming a ferroelectric layer on the bottom electrode; forming a top electrode on the ferroelectric layer, wherein the bottom electrode, the ferroelectric layer, and the top electrode form a ferroelectric capacitor; forming a high permittivity dielectric layer over the ferroelectric capacitor, wherein the high permittivity dielectric layer comprises an encapsulation layer and completely covers the top electrode; and forming a local interconnect electrode on the encapsulation layer so that the top electrode, the encapsulation layer and the local interconnect electrode form a second capacitor.
- 15. The method for forming an integrated circuit according to claim 14, wherein a dielectric permittivity of the encapsulation layer is 5 to 10 times larger than a dielectric permittivity of the ferroelectric layer.
- 16. The method for forming an integrated circuit according to claim 14, wherein the ferroelectric layer includes a first PZT.
- 17. The method for forming an integrated circuit according to claim 16, wherein the encapsulation layer includes a second PZT, and a Pb (lead) concentration of the second PZT is lower than that of the first PZT.
- 18. The method for forming an integrated circuit according to claim 16, wherein the encapsulation layer includes a second PZT, and the second PZT has a different concentration of Pb (lead), Zr (zirconate) or Ti (titanate) than that of the first PZT.
- 19. The method for forming an integrated circuit according to claim 14, wherein the encapsulation layer is formed by plasma damaging a PZT layer.
- 20. The method for forming an integrated circuit according to claim 14, wherein the encapsulation layer is formed at a temperature as high as 700° C.
- 21. The method for forming an integrated circuit according to claim 14, wherein a capacitance of the second capacitor is 5 to 10 times larger than a capacitance of the ferroelectric capacitor.
- 22. The method for forming an integrated circuit according to claim 14, wherein the ferroelectric capacitor is driven by a capacitive coupling.
- 23. A ferroelectric memory cell comprising:
a conductive barrier; a ferroelectric capacitor formed on the conductive barrier, wherein the ferroelectric capacitor includes a bottom electrode, a ferroelectric layer formed on the bottom electrode and a top electrode formed on the ferroelectric layer; and a high permittivity dielectric layer formed between the conductive barrier and the ferroelectric capacitor, wherein the conductive barrier connects the ferroelectric capacitor to an underlying device through a connecting electrode formed directly below the ferroelectric capacitor.
- 24. The ferroelectric memory cell according to claim 23, wherein a dielectric permittivity of the high permittivity dielectric layer is 5 to 10 times larger than a dielectric permittivity of the ferroelectric layer.
- 25. The ferroelectric memory cell according to claim 23, wherein the ferroelectric layer includes a first PZT.
- 26. The ferroelectric memory cell according to claim 25, wherein the high permittivity dielectric layer includes a second PZT, and a Pb (lead) concentration of the second PZT is lower than that of the first PZT.
- 27. The ferroelectric memory cell according to claim 25, wherein the high permittivity dielectric layer includes a second PZT, and the second PZT has a different concentration of Pb (lead), Zr (zirconate) or Ti (titanate) than that of the first PZT.
- 28. The ferroelectric memory cell according to claim 23, wherein the bottom electrode, the high permittivity dielectric layer and the conductive layer comprise a second capacitor.
- 29. The ferroelectric memory cell according to claim 28, wherein a capacitance of the second capacitor is 5 to 10 times larger than a capacitance of the ferroelectric capacitor.
- 30. The ferroelectric memory cell according to claim 23, wherein the ferroelectric capacitor is driven by a capacitive coupling.
- 31. The ferroelectric memory cell according to claim 23, further comprising a metalization layer formed on the ferroelectric capacitor.
- 32. An integrated circuit comprising:
a conductive barrier; a ferroelectric capacitor formed on the conductive barrier, wherein the ferroelectric capacitor includes a bottom electrode, a ferroelectric layer formed on the bottom electrode and a top electrode formed on the ferroelectric layer; and a high permittivity dielectric layer formed between the conductive barrier and the ferroelectric capacitor, wherein the conductive barrier connects the ferroelectric capacitor to an underlying device through a connecting electrode formed directly below the ferroelectric capacitor.
- 33. The integrated circuit according to claim 32, wherein a dielectric permittivity of the high permittivity dielectric layer is 5 to 10 times larger than a dielectric permittivity of the ferroelectric layer.
- 34. The integrated circuit according to claim 32, wherein the bottom electrode, the high permittivity dielectric layer and the conductive layer comprise a second capacitor.
- 35. The integrated circuit according to claim 34, wherein a capacitance of the second capacitor is 5 to 10 times larger than a capacitance of the ferroelectric capacitor.
- 36. A method for forming an integrated circuit comprising:
forming a conductor; forming a conductive barrier on the conductor; forming a high permittivity dielectric layer on the conductive barrier; and forming a ferroelectric capacitor on the high permittivity dielectric layer, wherein the ferroelectric capacitor includes a bottom electrode, a ferroelectric layer formed on the bottom electrode and a top electrode formed on the ferroelectric layer, wherein the conductive barrier connects the ferroelectric capacitor to an underlying device through the conductor.
- 37. The method for forming an integrated circuit according to claim 36, wherein a dielectric permittivity of the high permittivity dielectric layer is 5 to 10 times larger than a dielectric permittivity of the ferroelectric layer.
- 38. The method for forming an integrated circuit according to claim 36, wherein the ferroelectric layer includes a first PZT.
- 39. The method for forming an integrated circuit according to claim 38, wherein the high permittivity dielectric layer includes a second PZT, and a Pb (lead) concentration of the second PZT is lower than that of the first PZT.
- 40. The method for forming an integrated circuit according to claim 38, wherein the high permittivity dielectric layer includes a second PZT, and the second PZT has a different concentration of Pb (lead), Zr (zirconate) or Ti (titanate) than that of the first PZT.
- 41. The method for forming an integrated circuit according to claim 36, wherein the bottom electrode, the high permittivity dielectric layer and the conductive layer comprise a second capacitor.
- 42. The method for forming an integrated circuit according to claim 41, wherein a capacitance of the second capacitor is 5 to 10 times larger than a capacitance of the ferroelectric capacitor.
- 43. The method for forming an integrated circuit according to claim 36, wherein the ferroelectric capacitor is driven by a capacitive coupling.
- 44. The method for forming an integrated circuit according to claim 36, further comprising forming a metalization layer on the ferroelectric capacitor.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application claims benefit of U.S. Provisional Patent Application No. 60/214,207, entitled Capacitively-Coupled Ferroelectric Random Access Memory Cell with Capacitor over Plug Architecture, filed Jun. 26, 2000 which is hereby incorporated by reference.
Provisional Applications (1)
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Number |
Date |
Country |
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60214207 |
Jun 2000 |
US |