Patent Application
20250031388
Semiconductor devices that utilize on-chip capacitors may include, for example, dynamic random access memories (DRAMs), voltage controlled oscillators (VCOs), phase-locked loops (PLL), operational amplifiers (OP-AMPS), and switching (or switched) capacitors (SCs). Such on-chip capacitors may also be usable to decouple digital and analog integrated circuits (ICs) from electrical noise generated in or transmitted by other components of a semiconductor device.
Capacitor structures for ICs have evolved from the initial parallel plate capacitor structures, having two conductive layers separated by a dielectric, to more complex capacitor designs that may meet specifications for high capacitance in increasingly smaller devices. These more complex designs include, for example, metal-oxide-metal (MOM) capacitor designs and interdigitated finger MOM capacitor structures. Capacitors utilized in DRAM devices, for example, may include trench capacitors where the capacitor dielectric may separate the capacitor plates within trenches.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Unless explicitly stated otherwise, each element having the same reference numeral is presumed to have the same material composition and to have a thickness within a same thickness range. The term “source/drain region” may refer to a source or a drain, individually or collectively depending upon the context.
A typical DRAM device may include arrays of memory cells that may each comprise a charge storage device (e.g., a capacitor) coupled to a charge accessing device (e.g., a field effect transistor (FET), metal oxide semiconductor field effect transistor (MOSFET), etc.). Such devices may be referred to as a 1T1C device (one transistor, one capacitor device). The source electrode of the transistor may be connected to one plate of the storage capacitor. The drain electrode of the transistor may be connected to a conducting bit line. The gate electrode of the transistor may be connected to a conducting word line.
In operation, a logical 1 or a 0 may be written into or read out of the memory cell of the DRAM device. In order to access or select a specific memory cell, the intersecting word line and bit line for the transistor associated with the specified memory cell may be energized to write in or read out the value stored on the capacitor coupled to the access/select transistor. In a write operation, by applying a given potential to the word line turns on the access transistor and a given charge applied to the bit line will then be deposited on the capacitor plate and stored. Conversely, during a read operation, the word line again activates the access transistor and the presence of the charge in the capacitor may be sensed by appropriate circuitry and identified as a 1 or 0.
Some DRAM devices may utilize a planar-type storage capacitor. However, such DRAM devices that utilize a planar-type storage capacitor may occupy a large wafer surface area. Other DRAM devices may use a stacked capacitor to achieve higher capacitance with a reduced size. The stacked capacitor may be formed on top of the transistor which allows a smaller cell to be built without losing storage capacity.
Still other DRAM devices may use a trench capacitor to achieve higher capacitance with a reduced size. The trench capacitor may be formed in a trench or cavity that extends vertically into the substrate of an integrated circuit, and may be formed through a variety of etching processes. Such trench capacitors may increase plate area and, hence, capacitance, through an increased vertical extension rather than by horizontal extension of the metal plate surface. A first plate of such a trench capacitor may be defined by the surface of the inner wall of the doped region of the substrate within which the trench may be formed. Although such an inner wall forms the plate boundary, charge may also be stored within a depletion region formed beneath the wall surface and extending into the doped substrate. The opposing second plate of the trench capacitor, which may also be a storage plate, may be a conductive core that may be formed within the trench. An oxide layer may first be formed over the inner trench wall to serve as a dielectric medium and to insulate the first plate from the second plate.
Traditional DRAM devices may occupy a significant amount of silicon substrate area. They may also require a complex manufacturing process that utilizes a high temperature, resulting in a high manufacturing cost. In addition, the capacitor utilized by the DRAM devices for information storage may have a relatively low capacitance. For example, DRAM devices utilizing a plate capacitor may require a large area and may not reliably achieve a large capacitance. DRAM devices utilizing a finger capacitor may require a large area, have a limitation of pitch and a low dielectric constant insulator. DRAM devices utilizing a trench capacitor may suffer a limitation on via size, a limitation on via depth and a limitation on high-k dielectric thickness.
One or more embodiments of the present disclosure may include a capacitor having a significantly greater capacitance than a traditional capacitor. The capacitor may include a bottom capacitor plate including a rough upper surface with a root mean square (RMS) surface roughness of at least 1.14. The rough upper surface may increase a surface area of the bottom capacitor plate, and the increased surface area may result in an increased capacitance of the capacitor. The capacitor may further include a capacitor dielectric layer on the bottom capacitor plate and contacting the rough upper surface of the bottom capacitor plate, and an upper capacitor plate on the capacitor dielectric layer.
One or more embodiments may further include a semiconductor device such as a three-dimensional (3D) stacked DRAM device. The semiconductor device may include a transistor located on a substrate. The transistor may include, for example, a low-temperature processed select transistor. A dielectric layer including, for example, high-k dielectric material may be formed on the transistor. The semiconductor device may further include the capacitor described above in the dielectric layer and electrically coupled to the transistor. The capacitor may include, for example, a trench capacitor. In at least one embodiment, the capacitor may include a bottom capacitor plate connected to a first source/drain region of the transistor and having a rough upper surface with a root mean square (RMS) surface roughness of at least 1.14.
The semiconductor device may utilize the capacitor as information storage. The semiconductor device may include a very simple structure that allows the device to increase surface area (e.g., surface area of bottom capacitor plate of the capacitor). The semiconductor device may thereby significantly enhance the capacitance of the capacitor to provide a high performance.
In addition, a method of making the semiconductor device may utilize a simple (e.g., easy) and inexpensive process and may not require any additional masks or additional processes compared to a traditional method. In particular, the one or more embodiments may be fully compatible with a conventional process including a back end of line (BEOL) process.
One or more of the embodiments may include a method of making a semiconductor device such as a DRAM device. The method may include forming a capacitor having a bottom capacitor plate, a capacitor dielectric layer on the bottom capacitor plate, and an upper capacitor plate on the capacitor dielectric layer. The bottom capacitor plate and/or the upper capacitor plate may include a TiN layer. The rough upper surface of the bottom capacitor plate may include an upper surface of the TiN layer. In at least one embodiment, the bottom capacitor plate and/or the upper capacitor plate may be formed by atomic layer deposition (ALD). In at least one embodiment, the bottom capacitor plate and/or the upper capacitor plate may be formed by plasma enhanced atomic layer deposition (PEALD).
The capacitor may include a plurality of TiN layers having the same or different RMS surface roughness. In at least one embodiment, the bottom capacitor plate may include a first TiN layer having a first RMS surface roughness (e.g., at least 1.14) and the upper capacitor plate may include a second TiN layer having a second RMS surface roughness the same as or different than (e.g., greater than or less than) the first RMS surface roughness.
The TiN layer may be formed by PEALD to have a surface roughness that is greater, for example, than a surface roughness of a TiN layer formed by thermal atomic layer deposition (THALD) or physical vapor deposition (PVD). As a result, the TiN layer formed by PEALD may have a surface area that is greater than a surface area of the TiN layer formed by THALD or PVD. Thus, the capacitor having a bottom capacitor plate including the TiN layer formed by PEALD may have a capacitance that is greater than a capacitance of a capacitor including the TiN layer formed by THALD or PVD. In at least one embodiment, a capacitance of the capacitor including the TiN layer formed by PEALD may have a capacitance of 10.52 fF or more compared to a capacitance of about 9.97 fF or less where the TiN layer is formed by THALD.
One or more embodiments may include an embedded capacitor including a TiN layer formed by PEALD. In at least one embodiment, the bottom capacitor plate (e.g., rough electrode) of the embedded capacitor may include the TiN layer formed by PEALD. The embedded capacitor may be included, for example, in a 3D embedded transistor-capacitor structure of a semiconductor device (e.g., DRAM device).
One or more embodiments may be utilized, for example, in logic devices, memory devices, or any circuits needing large capacitance, for example DRAM, electrostatic discharge (ESD) devices, radio frequency (RF) devices, etc. One or more embodiments may be included, for example, in a BEOL transistor-capacitor such as in eDRAM, ESD devices, and RF devices.
Referring to the drawings,
As illustrated in
The FEOL device circuitry 12 may further include one or more dielectric material layers 11 and one or more levels of interconnect metallization 10 formed in and electrically insulated by the dielectric material layers 11. The interconnect metallization 10 may include any metal(s) suitable for FEOL and/or BEOL integrated circuit interconnection. The interconnect metallization 10, may include, for example, an alloy of predominantly Cu, an alloy of predominantly W, or an alloy of predominantly Al, etc. The dielectric material layers 11 may include any dielectric material known to be suitable for electrical isolation of monolithic ICs. In some embodiments, the dielectric material layers 11 may include silicon, and at least one of oxygen and nitrogen. The dielectric material layers 11 may include, for example, SiO, SiN, or SiON. The dielectric material layers 11 may also be a low-K dielectric material (e.g., having a dielectric constant below that of SiO2).
As further illustrated in
The transistor 120 may include a field effect transistor such as a MOSFET. In at least one embodiment, the transistor may include a low-temperature processed select transistor for a DRAM cell. The transistor 120 may be formed on a layer of crystalline semiconductor material layer 102 (e.g., semiconductor substrate or substrate) in the dielectric layer 101. The semiconductor material layer 102 may include at least a channel region of the transistor 120. The semiconductor material layer 102 may have a microstructure associated with that of a seed structure (not shown) in the dielectric layer 101.
The semiconductor material layer 102 may include a p-type, n-type, or intrinsic semiconductor material. The semiconductor material layer 102 may include a group IV semiconductor material such as silicon (Si), germanium (Ge), and alloys such as SiGe, GeSn, and SiGeSn. The semiconductor material layer 102 may have a melt temperature of at least 50° C. A localized/rapid thermal technique may be employed to generate a very high thermal gradient between the semiconductor material layer 102 and underlying materials so as to crystallize the semiconductor material of the semiconductor material layer 102 with minimal impact to the FEOL circuitry 12 or interconnect metallization 10. A thickness of the semiconductor material layer 102 may vary, but in one or more embodiments may be less than 50 nm, and advantageously less than 30 nm (e.g., in a range from 5 nm to 25 nm).
The transistor 120 may include a gate structure 121 on the semiconductor material layer 102 and a pair of source/drain regions 128 in the semiconductor material layer 102 adjacent the gate structure 121 (e.g., on opposing sides of the gate structure 121). The gate structure 121 may include a gate insulation layer 122 (e.g., gate oxide layer) on a surface of the semiconductor material layer 102. The gate insulating layer 122 may include one or more metal oxides such as Al2O3, HfO2, MgOx, and LaOx) and/or mixed-metal oxides (e.g., HfAlOx). The gate insulation layer 122 may additionally or alternatively include a thermal oxide layer. The gate insulation layer 122 may have a thickness in a range from about 50 Å to 100 Å.
The gate structure 121 may further include a gate electrode 123 on the gate insulation layer 122. The gate electrode 123 may include a conductive material such as polysilicon, a silicide material, a metal material or a metal composite material. The gate electrode 123 may also include alloy constituents such as C, Ta, W, Pt, and Sn. The gate electrode 123 may include a metal nitride (e.g., WN, TiN, or TaN) and may also include Al (e.g., TiAlN). In at least one embodiment the gate electrode 123 may include a doped polysilicon layer (e.g., doped with arsenic, phosphorus, etc.). Other suitable conductive materials are within the contemplated scope of disclosure. The gate electrode 123 may have a thickness in a range from about 500 Å to 2000 Å.
The gate structure 121 may further include a silicide layer 124 on the gate electrode 123. The silicide layer 124 may include a refractory metal silicide (e.g., tungsten silicide). The silicide layer 124 may also have a thickness in a range from about 500 Å to 2000 Å. The gate structure 121 may also include sidewall spacers 126 on a sidewall of the gate electrode 123 and a sidewall of the silicide layer 124. The sidewall spacers 126 may include, for example, one or more layers of silicon oxide (e.g., SiO2) and/or silicon nitride (e.g., Si3N4), silicon oxynitride, or any known low-k material. Other suitable materials are within the contemplated scope of disclosure.
The transistor 120 may further include source/drain regions 128 in the semiconductor material layer 102. In the case where the semiconductor material layer 102 includes a p-type substrate, the source/drain regions 128 may include n-type source/drain regions. The source/drain regions 128 may be doped, for example, with dopant ions such as arsenic, phosphorus, etc. The source/drain regions 128 may include lightly-doped extension regions (not shown) adjacent the gate structure 121 and under the sidewall spacers 126. A silicide layer (not shown) may be formed on an upper surface of the source/drain regions 128 to reduce contact resistance.
The semiconductor device 100 may further include a first dielectric layer 131 located on the semiconductor material layer 102 and over the gate structure 121. The first dielectric layer 131 may include a material that is substantially similar to the material of the dielectric material layers 11 in the FEOL device circuitry 12. In at least one embodiment, the first dielectric layer 131 may include interlayer dielectric (ILD) and may be formed of a dielectric material such as silicon dioxide (SiO2). Other suitable dielectric materials are within the contemplated scope of disclosure. The first dielectric layer 131 may have a thickness in a range from 3 nm to 20 nm.
The semiconductor device 100 may also include contact metallization 130 which may provide for electrically coupling the transistor 120. The contact metallization 130 may include a first source/drain contact 132, second source/drain contact 134 and gate electrode contact 136. The first source/drain contact 132 may be connected to a source/drain region 128. The second source-drain contact 134 may be connected to the other source/drain region 128. The gate electrode contact 136 may be connected to the gate electrode 123 through the silicide layer 125. In at least one embodiment, the first source/drain contact 132 may be connected to a source of the source/drain regions 128 and the second source-drain contact 134 may be connected to a drain of the source/drain regions 128. In at least one embodiment, the second source-drain contact 134 may connect the drain of the source/drain regions 128 to a bit line (not shown) of a DRAM device, and the gate electrode contact 136 may connect the gate electrode 123 to a word line (not shown) of the DRAM device.
The contact metallization 130 may have any composition known to provide a suitable contact to semiconductor materials. The contact metallization 130 may form a Schottky or ohmic junction with the source/drain semiconductor material of the source/drain regions 128. The contact metallization 130 may include, for example, one or more metals or metallic compounds. In some embodiments, the contact metallization 130 may include a metal nitride at the interface of (i.e., in direct contact with) the source/drain regions 128. The metal nitride may include TIN, TaN, and WN. The contact metallization 130 may also, or in the alternative, include a noble metal (e.g., Pt) at the interface of (i.e., in direct contact with) source/drain regions 128. Other suitable metal materials are within the contemplated scope of disclosure.
The semiconductor device 100 may further include a second dielectric layer 151 located on the first dielectric layer 131. An etching stop layer (not shown) such as silicon carbide, silicon nitride, or the like may be located on the first dielectric layer 131, in which case the second dielectric layer 151 may be located on the etching stop layer. The second dielectric layer 151 may include a material that is substantially similar to the material of the dielectric material layers 11 in the FEOL device circuitry 12. The second dielectric layer 151 (e.g., ILD layer) may be formed of a dielectric material such as silicon oxide. Other suitable dielectric materials are within the contemplated scope of disclosure. The second dielectric layer 151 may have a thickness in a range from 50 nm to 2500 nm.
The second dielectric layer 151 may include a trench 152 extending substantially perpendicular (e.g., in the z-direction) to the surface of the semiconductor material layer 102. The trench 152 may have a substantially circular cylindrical shape extending axially perpendicular to the surface of the semiconductor material layer 102. The depth (e.g., in the z-direction) of the trench 152 may be in a range from 50 nm to 2500 nm. The trench 152 may extend over an entire thickness of the second dielectric layer 151. That is, a depth of the trench 152 may be substantially equal to the thickness of the second dielectric layer 151. A width (e.g., diameter) of the trench 152 may be in a range from 20 nm to 200 nm.
The trench 152 may have a trench bottom 152a that is constituted in part by an upper surface of the first dielectric layer 131 and in part by an upper surface of the first source/drain contact 132. The trench bottom 152a may have a substantially circular shape. As illustrated in
The capacitor 160 may be located in the trench 152. The capacitor 160 may include a bottom capacitor plate 162, a capacitor dielectric layer 164 on the bottom capacitor plate 162 and an upper capacitor plate 166 on the capacitor dielectric layer 164. The capacitor 160 may substantially fill the trench 152 and may, therefore, have a size and shape substantially similar to the size and shape of the trench 152. In particular, the capacitor 160 may have a substantially circular cylindrical shape extending axially perpendicular to the surface of the semiconductor material layer 102.
A length Lc of the capacitor 160 may be in a range from 50 nm to 2500 nm and substantially equal to the thickness of the second dielectric layer 151. A width Wc (e.g., diameter) of the capacitor 160 may be in a range from 20 nm to 200 nm. In at least one embodiment, the capacitor 160 may have a capacitance of at least 10.52 fF. In at least one embodiment, the capacitor 160 may serve as an information storage element in a DRAM cell.
The bottom capacitor plate 162 may include a bottom capacitor plate bottom portion 162a and a bottom capacitor plate sidewall portion 162b extending substantially perpendicular to the bottom capacitor plate bottom portion 162a. The bottom capacitor plate 162 may have a substantially uniform thickness throughout the bottom capacitor plate bottom portion 162a and bottom capacitor plate sidewall portion 162b. In at least one embodiment, the thickness of the bottom capacitor plate 162 may be in a range from 2 nm to 150 nm. The bottom capacitor plate bottom portion 162a may located on the trench bottom 152a and the bottom capacitor plate sidewall portion 162b may be located on the trench sidewall 152b.
The bottom capacitor plate bottom portion 162a may contact the upper surface of the first source/drain contact 132. In at least one embodiment, an inner portion (e.g., inner diameter portion) of the bottom capacitor plate bottom portion 162a may contact the upper surface of the first source/drain contact 132 and an outer portion (e.g., outer diameter portion) of the bottom capacitor plate bottom portion 162a may contact the upper surface of the second dielectric layer 151.
It should be noted that it one or more embodiments, the bottom capacitor plate bottom portion 162a may not necessarily contact the upper surface of the first source/drain contact 132. There may be one or more intervening dielectric layers (e.g., intermetal dielectric (IMD) layers) between the first dielectric layer 131 and the second dielectric layer 151. In that case, the bottom capacitor plate bottom portion 162a may be electrically coupled to the upper surface of the first source/drain contact 132 by one or more metal layers in the one or more intervening dielectric layers.
In at least one embodiment, a centerpoint of the bottom capacitor plate bottom portion 162a may be substantially aligned with a centerpoint of the upper surface of the first source/drain contact 132. That is, the bottom capacitor plate bottom portion 162a and the upper surface of the first source/drain contact 132 may be concentrically arranged. In at least one embodiment, the first source/drain contact 132 may be connected to a source of the source/drain regions 128 and the bottom capacitor plate 162 is electrically coupled to the source through the first source/drain contact 132.
The bottom capacitor plate 162 may be formed of one or more layers of conductive material such as a metal or metal alloy. The conductive material may include, for example, Al, Ta, Ag, Cu, W, Co, Pd, Pt, Ni, Nb, other low resistivity metal constituent, an alloy thereof, or a combination thereof. In at least one embodiment, the bottom capacitor plate 162 may include a layer of TiN. Other suitable metal materials are within the contemplated scope of disclosure. The bottom capacitor plate 162 may also include a rough upper surface 162s. In at least one embodiment, the bottom capacitor plate 162 may include a layer of TiN and the rough upper surface 162s may include an upper surface of the layer of TiN. In at least one embodiment, the rough upper surface may have a root mean square (RMS) surface roughness of at least 1.14.
The capacitor dielectric layer 164 may include a capacitor dielectric layer bottom portion 164a and a capacitor dielectric layer sidewall portion 164b extending substantially perpendicular to the capacitor dielectric layer bottom portion 164a. The capacitor dielectric layer 164 may also include a capacitor dielectric layer upper portion 164c located on an upper surface of the second dielectric layer 151 outside the trench 152. The capacitor dielectric layer upper portion 164c may also be formed on an end of the bottom capacitor plate sidewall portion 162b. A length of the capacitor dielectric layer upper portion 164c (in the x-direction) may be at least three times the thickness of the bottom capacitor plate 162.
The capacitor dielectric layer 164 may have a substantially uniform thickness throughout the capacitor dielectric layer bottom portion 164a, capacitor dielectric layer sidewall portion 164b and capacitor dielectric layer upper portion 164c. The thickness of the capacitor dielectric layer 164 may be less than the thickness of the bottom capacitor plate 162. In at least one embodiment, the thickness of the capacitor dielectric layer 164 may be in a range from 2 nm to 20 nm. The capacitor dielectric layer bottom portion 164a may be located on the bottom capacitor plate bottom portion 162a and the capacitor dielectric layer sidewall portion 164b may be located on the bottom capacitor plate sidewall portion 162b.
The capacitor dielectric layer 164 may be formed of one or more layers of dielectric material (e.g., low-k dielectric material, high-k dielectric material, etc.). The dielectric material may include, for example, hafnium silicate, zirconium silicate, hafnium dioxide, zirconium dioxide, etc. Other suitable metal materials are within the contemplated scope of disclosure. The capacitor dielectric layer 164 may also include a lower surface 164s which may contact the rough upper surface 162s of the bottom capacitor plate 162. The lower surface 164s of the capacitor dielectric layer 164 may be located on the capacitor dielectric layer bottom portion 164a and the capacitor dielectric layer sidewall portion 164b.
The upper capacitor plate 166 may include an upper capacitor plate bottom portion 166a and an upper capacitor plate sidewall portion 166b extending substantially perpendicular to the upper capacitor plate bottom portion 164a. The upper capacitor plate 166 may also include an upper capacitor plate upper portion 166c located on the capacitor dielectric layer upper portion 164c outside the trench 152. An end of the upper capacitor plate upper portion 166c may have an end that is substantially aligned with an end of the capacitor dielectric layer upper portion 164c. A length of the upper capacitor plate upper portion 166c (in the x-direction) may be substantially the same as a length of the capacitor dielectric layer upper portion 164c.
The upper capacitor plate 166 may have a substantially uniform thickness throughout the upper capacitor plate bottom portion 166a, upper capacitor plate sidewall portion 164b and upper capacitor plate upper portion 166c. In at least one embodiment, the thickness of the upper capacitor plate 166 may have vary among the upper capacitor plate bottom portion 166a, upper capacitor plate sidewall portion 164b and upper capacitor plate upper portion 166c. For example, a thickness of the upper capacitor plate bottom portion 166a may be different than (e.g., greater than or less than) a thickness of the upper capacitor plate sidewall portion 164b and/or a thickness of the upper capacitor plate upper portion 166c, a thickness of the upper capacitor plate sidewall portion 164b may be different than a thickness of the upper capacitor plate bottom portion 166a and/or a thickness of the upper capacitor plate upper portion 166c, and a thickness of the upper capacitor plate upper portion 166c may be different than a thickness of the upper capacitor plate bottom portion 166a and/or a thickness of the upper capacitor plate sidewall portion 164b.
In at least one embodiment, the thickness of the upper capacitor plate 166 may be substantially the same as the thickness of the bottom capacitor plate 162. In at least one embodiment, the thickness of the upper capacitor plate 166 may be greater than the thickness of the capacitor dielectric layer 164 and less than the thickness of the bottom capacitor plate 162. In at least one embodiment, the thickness of the upper capacitor plate 166 may be in a range from 2 nm to 150 nm. The upper capacitor plate bottom portion 166a may be located on the capacitor dielectric layer bottom portion 164a and the upper capacitor plate sidewall portion 166b may be located on the capacitor dielectric layer sidewall portion 164b.
The upper capacitor plate 166 may be formed of one or more layers of conductive material such as a metal or metal alloy. The conductive material may include, for example, Al, Ta, Ag, Cu, W, Co, Pd, Pt, Ni, Nb, other low resistivity metal constituent, an alloy thereof, or a combination thereof. In at least one embodiment, the upper capacitor plate 166 may be formed of substantially the same material as the bottom capacitor plate 162. In at least one embodiment, the upper capacitor plate 166 may include a layer of TiN. Other suitable metal materials are within the contemplated scope of disclosure.
The capacitor 160 may include a plurality of TiN layers having the same or different RMS surface roughness. In at least one embodiment, the bottom capacitor plate 162 may include a first TiN layer having a first RMS surface roughness (e.g., at least 1.14) and the upper capacitor plate 166 may include a second TiN layer having a second RMS surface roughness the same as or different than (e.g., greater than or less than) the first RMS surface roughness.
The semiconductor device 100 may further include a third dielectric layer 171 located on the second dielectric layer 151. The third dielectric layer 171 may include a material that is substantially similar to the material of the dielectric material layers 11 in the FEOL device circuitry 12. The third dielectric layer 171 (e.g., ILD layer) may be formed of a dielectric material such as silicon oxide. Other suitable dielectric materials are within the contemplated scope of disclosure. The third dielectric layer 171 may have a thickness in a range from 50 nm to 2500 nm.
The third dielectric layer 171 may include a third dielectric layer projecting portion 171p that projects downwardly into the capacitor 160. In particular, a recess may be located in a central portion of the capacitor 160 on the upper capacitor plate 166. The third dielectric layer projecting portion 171p may project onto the upper capacitor plate 166 in the central portion of the capacitor 160 and fill the recess.
As illustrated in
Further, in at least one embodiment, a thickness of the capacitor dielectric layer 164 may be less than a depth of the recesses 162s-R and, therefore, not fill the recesses 162s-R. In that case the upper capacitor plate 166 may also project into the one or more recesses of the recessed portion 164s-R. In addition, in at least one embodiment, a combined thickness of the capacitor dielectric layer 164 and the upper capacitor plate 166 may be less than a depth of the recesses 162s-R and not fill the recesses 162s-R. In that case the third dielectric layer projecting portion 171p may project into the one or more recesses of the recessed portion 164s-R onto the upper capacitor plate 166.
As illustrated in
The dielectric layer 101 may be formed on the dielectric material layers 11 of the FEOL device circuitry 12. The dielectric layer 101 may be formed, for example, by depositing a layer of dielectric material (e.g., SiO2) on the dielectric material layers 11. The dielectric material may be deposited by chemical vapor deposition (CVD), PVD or other suitable deposition method. In at least one embodiment, the layer of dielectric material may include a layer of SiO2 deposited by low-pressure chemical vapor deposition (LPCVD) using tetraethosiloxane (TEOS) as the reactant gas. The layer of dielectric material may be deposited to a thickness in a range from 3000 Å to 8000 Å. An upper surface of the dielectric layer 101 may then be planarized by performing, for example, chemical/mechanical polishing (CMP) using an appropriate polishing slurry.
The semiconductor material layer 102 (e.g., semiconductor substrate, silicon wafer, SOI substrate, doped semiconductor substrate, etc.) may be formed in the dielectric layer 101. The semiconductor material layer 102 may be formed, for example, by forming a BEOL crystalline seed over the dielectric layer 101 which may be located over the FEOL device circuitry 12 which employs a monocrystalline substrate semiconductor. The BEOL crystalline seed may be epitaxial to the monocrystalline substrate semiconductor, or may have crystallinity independent of that of the monocrystalline substrate semiconductor. The BEOL crystalline seed may include a first material having a higher melt temperature than a melt material formed over the BEOL crystalline seed and over the dielectric layer 101. Through rapid melt growth, the melt material may be heated to a temperature sufficient to transition from an as-deposited state to a crystallized material that is derived from, and therefore associated with, the BEOL crystalline seed. The semiconductor material layer 102 may be constituted of the crystallized material.
The gate structure 121 and source/drain regions 128 may then be formed on the semiconductor material layer 102. First, an insulating layer (e.g., corresponding to the gate insulating layer 122) may be formed on the semiconductor material layer 102. The insulating layer may be formed, for example, by depositing an insulating material such as one or more metal oxides such as Al2O3, HfO2, MgOx, and LaOx) and/or mixed-metal oxides (e.g., HfAlOx), or by thermally oxidizing the semiconductor material layer 102. The insulating material may be deposited by CVD, PVD or other suitable deposition technique. The insulating layer may be formed to have a thickness in a range from 50 Å to 100 Å. Other suitable methods of forming the insulating layer are within the contemplated scope of disclosure.
An appropriately doped polysilicon layer (e.g., corresponding to the gate electrode 123) may then be deposited on the insulating layer. The polysilicon layer may be deposited by CVD, PVD or other suitable deposition method. In at least one embodiment, the polysilicon layer may be deposited by LPCVD to a thickness in a range from 500 Å to 2000 Å. The polysilicon layer may then be appropriately doped by an ion implantation process. In at least one embodiment, arsenic or phosphorus may be implanted where the transistor 120 includes an N-channel FET.
A silicide layer (e.g., corresponding to the silicide layer 125) may then be formed on the doped polysilicon layer. In at least one embodiment, the silicide layer may include tungsten silicide (WSi2). The silicide layer may be formed, for example, by reacting a surface of the polysilicon layer with tungsten hexafluoride (WF6) (e.g., deposited by chemical vapor deposition (CVD)) in the presence of silane (SiH4). the silicide layer may be formed to have a thickness in a range from 500 Å to 2000 Å.
A photolithographic process may then be performed to pattern the insulating layer, polysilicon layer and silicide layer. The photolithographic process may include forming a patterned photoresist mask (not shown) on the silicide layer, and etching (e.g., wet etching, dry etching, etc.) the silicide layer, polysilicon layer and insulating layer through openings in the photoresist mask to form the silicide layer 125, the gate electrode 123 and the gate insulating layer 122, respectively. The photoresist mask may be subsequently removed by ashing, dissolving the photoresist mask or by consuming the photoresist mask during the etch process.
The source/drain regions 128 may be formed in the semiconductor material layer 102 adjacent the gate insulating layer 122. The source/drain regions 128 may be formed by performing another ion implantation process. The ion implantation process may include ion implanting dopant ions such as arsenic or phosphorus in the semiconductor material layer 102.
The sidewall spacers 126 may then be formed on the sidewalls of the gate insulating layer 122, the gate electrode 123 and the silicide layer 125. The sidewall spacers 126 may be formed, for example, by depositing one or more layers of oxide (e.g. silicon oxide), nitride (e.g., silicon nitride) and/or oxynitride (e.g., silicon oxynitride) on the semiconductor material layer 102. The layers of oxide, nitride and/or oxynitride may be deposited by CVD, PVD or other suitable deposition method. In at least one embodiment, the layers of oxide, nitride and/or oxynitride may be deposited by LPCVD. The layers of oxide, nitride and/or oxynitride may then be anisotropically etched in a reactive ion etcher (RIE) to complete the formation of the gate structure 121.
Openings may then be formed in the first dielectric layer 131 in order to accommodate the contact metallization 130 including the first source/drain contact 132, second source/drain contact 134 and gate electrode contact 136. The openings may be formed, for example, by etching the first dielectric layer 131. The etching may be performed so as to expose an upper surface of the source/regions 128 and an upper surface of the silicide layer 125. In at least one embodiment, the openings may be etched in the first dielectric layer 131 by using a high-density-plasma (HDP) etcher and an etchant gas mixture that selectively etches the SiO2 of the first dielectric layer 131 to form self-aligned contacts (SAC). This selective etching may be achieved, for example, using a fluorine-based etchant gas mixture.
A conductive layer may then be formed on the first dielectric layer 131 and in the openings in the first dielectric layer 131. The conductive layer may include, for example, a metal material, polysilicon, etc. and may fill the openings. In at least one embodiment, the conductive layer may include a metal material (e.g., metal, metal alloy, metal compounds, metal nitrides such as TIN, TaN, and WN, etc.) and may be formed by depositing the metal material on the first dielectric layer 131 by CVD, plasma-enhanced CVD (PECVD), LPCVD, PVD or ALD. The metal material may then be planarized such as by CMP in order to make an upper surface of the contact metallization 130 (e.g., first source/drain contact 132, second source/drain contact 134 and gate electrode contact 136) to be coplanar with an upper surface of the first dielectric layer 131.
The second dielectric layer 151 may be formed on the upper surface of the first dielectric layer 131 and the upper surface of the contact metallization 130. The second dielectric layer 151 may be formed, for example, by depositing a layer of dielectric material (e.g., SiO2) on the first dielectric layer 131. The dielectric material may be deposited by CVD, PVD or other suitable deposition method. In at least one embodiment, the layer of dielectric material may include a layer of SiO2 deposited by LPCVD using tetraethosiloxane (TEOS) as the reactant gas. The layer of dielectric material may be deposited to a thickness in a range from 50 nm to 2500 nm. An upper surface of the second dielectric layer 151 may then be planarized by performing, for example, CMP using an appropriate polishing slurry.
The trench 152 may then be formed in the second dielectric layer 151 in order to accommodate the capacitor 160. The trench 152 may be formed, for example, by etching the second dielectric layer 151. The etching may be performed so as to expose the upper surface of the first dielectric layer 131 and the upper surface of the contact metallization 130. In at least one embodiment, the second dielectric layer 151 may be etched until the upper surface of the first source/drain contact 132 and the upper surface of the first dielectric layer 131 are exposed. In at least one embodiment, the trench 152 may be etched in the second dielectric layer 151 by using a high-density-plasma (HDP) etcher and an etchant gas mixture that selectively etches the SiO2 of the second dielectric layer 151.
The trench 152 may be formed so as to have a depth and width (e.g., diameter) that are substantially the same as the length Lc and width Wc of the capacitor 160, respectively. In particular, the trench 152 may be formed to have a depth in a range from 50 nm to 2500 nm and substantially equal to the thickness of the second dielectric layer 151. The trench 152 may be formed to have a width (e.g., diameter) in a range from 20 nm to 200 nm.
The bottom capacitor plate 162 may be formed so as to include the rough upper surface 162s on both the bottom capacitor plate bottom portion 162a and the bottom capacitor plate sidewall portion 162b. In at least one embodiment, the bottom capacitor plate 162 may be formed so that the rough upper surface 162s has a root mean square (RMS) surface roughness of at least 1.14 on both the bottom capacitor plate bottom portion 162a and the bottom capacitor plate sidewall portion 162b. In at least one embodiment, the bottom capacitor plate 162 may be formed so that the rough upper surface 162s has the recessed portion 162s-R on both the bottom capacitor plate bottom portion 162a and the bottom capacitor plate sidewall portion 162b.
The method of forming the bottom capacitor plate 162 may be selected so as to provide the bottom capacitor plate 162 with the rough upper surface 162s having the recessed portion 162s-R and an RMS roughness of at least 1.14. In at least one embodiment, no additional processing may be needed after the forming (e.g., depositing) of the conductive material to provide the bottom capacitor plate 162 with the rough upper surface 162s having the recessed portion 162s-R and an RMS roughness of at least 1.14. In at least one embodiment, the method may include CVD such as PECVD, HDP-CVD, thermal CVD, APCVD, etc. In at least one embodiment, the method may include ALD such as PEALD, thermal ALD, etc.
In at least one embodiment, the bottom capacitor plate 162 may be formed by PEALD to provide the rough upper surface 162s having the recessed portion 162s-R and an RMS roughness of at least 1.14. The PEALD method may utilize a low processing temperature (less than 250° C.) to form a TiN layer constituting the bottom capacitor plate 162.
The PEALD method of forming the TiN layer may use argon (99.999%) as a carrier gas and as a purging gas. In at least one embodiment, the steps (e.g., all steps) of the PEALD method may be performed in an ALD reaction chamber under vacuum at 250° C. The TiN layer may include one or more thin TiN films grown directly onto the surface of the second dielectric layer 151, onto a surface of the trench bottom 152a and onto a surface of the trench sidewall 152b.
The PEALD method may use tetrakis(dimethylamido) titanium (IV) (99%) (TDMAT) as the titanium precursor. The TDMAT may be heated to 65° C. to increase its vapor pressure. The TDMAT may be exposed to the chamber for at least 1000 milliseconds, followed by at least a 10 second purge under an argon-rich environment (e.g., at least 110 sccm argon). The ALD chamber may then be exposed to a NH3: Ar plasma for at leaset 20 seconds, followed by at least a 10 second purge under at least 110 sccm argon. The NH3: Ar may include, for example, a 300 W NH3: Ar plasma (10 sccm: 100 sccm, respectively). This may complete one cycle. The cycle may be repeated until the desired thickness (e.g., in a range from 2 nm to 150 nm) is reached.
An optional conditioning step may be used to condition the PEALD deposited TiN layer. The optional conditioning step may include a post-deposition hydrogen plasma treatment on the TiN layer. In this optional conditioning step, after the TIN layer is deposited, the intermediate structure may be maintained inside the ALD chamber at 250° C. and repeatedly exposed to 5 second intervals of hydrogen plasma (e.g., 300 W hydrogen plasma) balanced in argon. This may be repeated at least 600 times for a total 50 minute exposure of the TiN layer to the hydrogen plasma.
The conditioning step may further alter the properties of TiN while maintaining the thermal budget at the low temperature of 250° C. The conditioning step may reduce surface oxygen contamination and carbon contamination in the TiN layer. The conditioning step may also greatly improve a metallic quality of the TiN layer. In particular, the conditioning step may reduce the resistivity of the TiN layer.
After the TiN layer is deposited, a photolithographic process may be used to remove the TiN layer from the upper surface of the second dielectric layer 151. The photolithographic process may include forming a patterned photoresist mask (not shown) on the second dielectric layer 151, and etching (e.g., wet etching, dry etching, etc.) the conductive material (e.g. TiN) through openings in the photoresist mask. The photoresist mask may be subsequently removed by ashing, dissolving the photoresist mask or by consuming the photoresist mask during the etch process. A CMP step may alternatively or additionally be used to remove the conductive material and planarize the upper surface of the second dielectric material 151 with an end of the bottom capacitor portion sidewall portion 162b.
The layer of dielectric material for the capacitor dielectric layer 164 may be formed, for example, by depositing the layer on the second dielectric layer 151 and in the trench 152. The layer of dielectric material may be deposited by CVD, PVD or other suitable deposition method. The layer of dielectric material may be deposited to have a substantially uniform thickness in a range from 2 nm to 20 nm.
The upper capacitor plate 166 may be formed by depositing a layer of conductive material (e.g., TiN, a metal such as Al, Ta, Ag, Cu, W, Co, Pd, Pt, Ni, Nb, other low resistivity metal constituent, an alloy thereof, or a combination thereof) on the layer of dielectric material for the capacitor dielectric layer 164. The layer of conductive material may be deposited on the layer of dielectric material in the trench 152 and on the upper surface of the second dielectric layer 151. The layer of conductive material for the upper capacitor plate 166 may be conformally formed on the capacitor dielectric layer 164.
The layer of conductive material for the upper capacitor plate 166 may be deposited by CVD, PVD or other suitable deposition method. The layer of conductive material may be deposited to have a substantially uniform thickness in a range from 2 nm to 150 nm.
A photolithographic process may then be used to form the capacitor dielectric layer upper portion 164c and the upper capacitor plate upper portion 166c. The photolithographic process may include forming a patterned photoresist mask (not shown) on the second dielectric layer 151. The layer of dielectric material for the capacitor dielectric layer 164 and the conductive layer for the upper capacitor plate 166 may then be etched (e.g., by wet etching, dry etching, etc.) through openings in the photoresist mask. The photoresist mask may be subsequently removed by ashing, dissolving the photoresist mask or by consuming the photoresist mask during the etch process. A CMP step may alternatively or additionally be used to remove the dielectric material and conductive material.
The third dielectric layer 171 may be formed on the upper surface of the second dielectric layer 151 and on the upper capacitor plate 166 in the trench 152. The third dielectric layer 171 may be formed, for example, by depositing a layer of dielectric material (e.g., SiO2) on the second dielectric layer 151. The layer of dielectric material may be deposited so as to form the third dielectric layer projecting portion 171p on the upper capacitor plate 166. In at least one embodiment, the layer of dielectric material may fill the space remaining in the trench 152 over the upper capacitor plate 166.
The layer of dielectric material may be deposited by CVD, PVD or other suitable deposition method. In at least one embodiment, the layer of dielectric material may include a layer of SiO2 deposited by LPCVD using tetraethosiloxane (TEOS) as the reactant gas. The layer of dielectric material may be deposited to a thickness in a range from 50 nm to 2500 nm. An upper surface of the third dielectric layer 171 may then be planarized by performing, for example, CMP using an appropriate polishing slurry.
In the alternative design in
In at least one embodiment, the depth Dr of the recesses 162s-R may be greater than a combined thickness including the thickness TD of the capacitor dielectric layer 164 and a thickness TU of the upper capacitor plate 166. In that case, at least a portion of the third dielectric layer projecting portion 171p may be located in the recesses 162s-R.
The width Wr of the recesses 162s-R may also be greater than the thickness TD of the capacitor dielectric layer 164. In at least one embodiment, the width Wr of the recesses 162s-R may be greater than twice the combined thickness including the thickness TD of the capacitor dielectric layer 164 and the thickness TU of the upper capacitor plate 166.
In at least one embodiment, the elements of the transistor 120 in the first alternative design may be substantially the same as the elements in the original design in
The logic section 502 may include a plurality of logic devices (e.g., N-MOSFET devices, P-MOSFET devices, etc.) which are not shown in
The memory section 501 may include a plurality of DRAM cells 170 in the BEOL device circuitry 14. The DRAM cells 170 may include the transistor 120 (e.g., select transistor) and the capacitor 160 for information storage. As illustrated in
In at least one embodiment, the capacitor dielectric layer upper portion 164c of the DRAM cells 170 may be electrically coupled together. In at least one embodiment the capacitor dielectric layer upper portion 164c of the DRAM cells 170 may be integrally formed together as a unit. In at least one embodiment, the capacitor dielectric layer upper portion 164c of the DRAM cells 170 may be formed concurrently in the same processing step.
In at least one embodiment, the upper capacitor plate upper portion 166c of the DRAM cells 170 may be electrically coupled together. In at least one embodiment the upper capacitor plate upper portion 166c of the DRAM cells 170 may be integrally formed together as a unit. In at least one embodiment, the upper capacitor plate upper portion 166c of the DRAM cells 170 may be formed concurrently in the same processing step.
In the third alternative design of the semiconductor device 100, the logic section 501 may be located adjacent the memory section 501. The logic section 501 may be capable of performing processing operations (e.g., graphic processing operations) at a high speed. The logic section 501 may utilize the memory section for storing information (e.g., information used in the processing operations, information generated by the processing operations, etc.).
The DRAM section 501 may include a memory array 602 including the plurality of the DRAM cells 170. The DRAM cells 170 may include the transistor 120 and capacitor 160 as illustrated, for example, in
Referring to
Referring again to
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The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
