The invention concerns capacitors, especially capacitors, resonators and filters in sub-micrometer CMOS technology integrated circuits and is more particularly directed to a method of creating a high capacitance per unit area of a silicon chip, and capacitors, resonators, filters and transmission lines implementing the method.
There is a desire to be able to use integrated circuits for high frequency circuits, in the microwave range and higher. The desire to increase speed/frequency necessitates decreased size features, presently gate lengths well below 1.0 μm, in CMOS and related technologies. This results in a drastic increase in price per unit area, i.e. $/square mm, of the silicon chips.
There have been attempts to use high integration density, low cost standard silicon technology such as CMOS and bipolar. Such silicon technology has a low resistivity, less than 10-20 Ohm cm. To use such silicon for fabrication of microwave integrated circuits, for example high-speed digital integrated circuits, there will be high losses in passive components associated with the low resistivity silicon substrate. Passive components can for example be transmission lines, interconnections, inductors, and capacitors.
Traditionally two different types of on-chip capacitors have been used in standard silicon technology. A first type, Metal-Insulator-Metal (MIM) capacitors used in standard silicon integrated circuits have high losses and a low self-resonant frequency due to the small thickness and low conductivity of the capacitor plates. MIM capacitors could also be argued to have reliability problems. A second type, Metal-Insulator-Metal-Insulator-Metal (MIMIM) capacitors have similar disadvantages. There seems to be room for improvement of how to implement capacitors in an integrated circuit, such as CMOS or bipolar, especially in low resistivity integrated circuits.
An object of the invention is to define a method of creating a capacitor and to define a capacitor which overcome the above mentioned drawbacks.
Another object of the invention is to define a method of creating a capacitor and to define a capacitor, which requires a minimal unit area.
A further object of the invention is to define a method of creating passive components, such as transmission lines and to define passive components, such as transmission lines with low losses.
The aforementioned objects are achieved according to the invention by a method of creating a capacitor in an integrated circuit. According to a basic version of the invention the capacitor uses intensive fringing fields to create a capacitance. This is achieved by creating a capacitor with vertical overlapping conducting electrodes between two planes of the integrated circuit, instead of plates parallel to the planes. A capacitor according to the invention can additionally comprise horizontal, i.e. parallel plates. A capacitor according the method is also disclosed.
The aforementioned objects are also achieved by a method of arranging an on-chip capacitor. The on-chip capacitor creates a capacitance between a first conducting connection point in a first plane of the chip and a second conducting connection point in a second plane of the chip. According to the invention the method comprises creating at least one conducting extension of a first type from the first conducting point towards the second plane to a third plane. Extensions of the first type always originate at the first plane and extend towards the second plane. The method further comprises creating at least one conducting extension of a second type from the second conducting connection point towards the first plane to a fourth plane. Extensions of the second type always originate at the second plane and extend towards the first plane. The fourth plane is located between the first plane and the second plane. The third plane is located between the fourth plane and the second plane. The first conducting extension is isolated from the second conducting extension by a dielectric allowing an electrical field to be created between the extensions. The conducting extensions thus overlap and are suitably close together, but at a distance so that there is no flash-over or breakdown of the dielectric. Suitably the extensions of the first and of the second type extend in principal parallel to a normal of the plane that they extend from.
Suitably the method further comprises creating a plurality conducting extensions of the first type and/or of the second type. In these cases the first and second conducting points respectively as applicable would take the form of a conducting area. Sometimes the first plane is a side of a first metal layer, and the second plane is a side of a second metal layer, the first and the second metal layers being different metal layers. In some versions the third and fourth planes are different sides of a third metal layer. In other versions the third plane is a side of a third metal layer and the fourth plane is a side of a fourth metal layer, the third and the fourth metal layers being different metal layers.
In some versions of the method, the method further comprises originating the conducting extension or extensions of the first and/or second type in a metal layer and terminating the conducting extension or extensions of the first and/or second type in a metal layer. In these version it can sometimes be appropriate that the method further comprises extending conducting extension or extensions of the first type through at least one further metal layer. To increase the capacitance of the capacitor the method can suitably further comprise extending the first conducting connection point in the first plane of the chip to comprise a conducting plate and/or comprise extending the second conducting connection point in the second plane of the chip to comprise a conducting plate.
The conducting extensions are suitably manufactured as vias, either solid or hollow.
One or more of the features of the above-described different methods according to the invention can be combined in any desired manner, as long as the features are not contradictory.
The aforementioned objects are also achieved by a method of creating an on-chip resonant circuit. The method comprises arranging one or more capacitors according to any one of the above-described methods, and at least one other passive component to thereby create the resonant circuit.
The aforementioned objects are also achieved by a method of creating an on-chip transmission line. The method comprises arranging one or more capacitors according to any one of the above-described methods, in the transmission line.
The aforementioned objects are also achieved according to the invention by an on-chip capacitor with a capacitance between a first conducting connection point in a first plane of the chip and a second conducting connection point in a second plane of the chip. According to the invention the on-chip capacitor comprises at least one conducting extension of a first type from the first conducting point towards the second plane to a third plane. Extensions of the first type always originate at the first plane and extend towards the second plane. The on-chip capacitor further comprises at least one conducting extension of a second type from the second conducting connection point towards the first plane to a fourth plane. Extensions of the second type always originate at the second plane and extend towards the first plane. The fourth plane is located between the first plane and the second plane. The third plane is located between the fourth plane and the second plane. The first conducting extension is isolated from the second conducting extension by a dielectric allowing an electrical field to be created between the extensions. Suitably the extensions of the first and of the second type extend in principal parallel to a normal of the plane that they extend from.
The on-chip capacitor can suitably further comprise a plurality of conducting extensions of the first and/or the second type. In these cases the first and second conducting points respectively as applicable would take the form of a conducting area. The first plane can be a side of a first metal layer, and the second plane can be a side of a second metal layer, the first and the second metal layers being different metal layers. The third and fourth planes can be different sides of a third metal layer in some embodiments. In other embodiments the third plane can be a side of a third metal layer and the fourth plane can be a side of a fourth metal layer, the third and the fourth metal layers being different metal layers.
The conducting extension or extensions of the first and or the second type can suitably in some embodiments originate in a metal layer and terminate in a metal layer. In some of these embodiments the conducting extension or extensions of the first and/or the second type suitably extends through at least one further metal layer.
The first conducting connection point in the first plane of the chip can in some embodiments comprise a conducting plate. The second conducting connection point in the second plane of the chip can in the same or other embodiments comprise a conducting plate.
The conducting extensions are suitably vias, either solid or hollow.
The features of the above-described different embodiments of an on-chip capacitor according to the invention can be combined in any desired manner, as long as no conflict occurs.
The aforementioned objects are also achieved according to the invention by an on-chip resonant circuit, where the resonant circuit comprises one or more capacitors according to any one of the above-described embodiments.
The aforementioned objects are also achieved according to the invention by an on-chip transmission line, where the transmission line comprises one or more capacitors according to any one of the above-described embodiments.
The aforementioned objects are also achieved according to the invention by a transmission line based component such as a resonator, matching network, or power splitter, where the transmission line based component comprises a transmission line according to any one of the above described embodiments.
By providing a method of creating an on-chip capacitor, a transmission line, and other passive components and embodiments thereof according to the invention a plurality of advantages over prior art methods and components are obtained. Primary purposes of the invention are to propose new designs of high density and Q-factor capacitors, resonators, and related microwave components compatible with sub-micrometer CMOS and bipolar silicon processes. According to the invention this is enabled primarily by making use of vias in multilayer silicon processes to generate intensive fringing fields between the vias and optional plates of the capacitors and thus increase the capacitance per unit area. Other advantages of this invention will become apparent from the description.
The invention will now be described in more detail for explanatory, and in no sense limiting, purposes, with reference to the following figures, in which
In order to clarify the method and device according to the invention, some examples of its use will now be described in connection with FIGS. 1 to 8.
As mentioned above, there are several methods of creating an on-chip capacitance.
A radically different type of capacitor has been suggested where the capacitor plates are arranged adjacent in a same plane instead of on top of each other.
The present invention creates an optimum capacitance in a limited surface area. This is achieved by using a depth of a structure in which a capacitor is created to create surfaces between which fields can be created.
Instead of just having first and second conducting points 310, 320, it is advantageous to let the metal layers form conducting plates that contribute to the capacitance.
Manufacturing conducting extensions between two metal layers of an integrated circuit is difficult and therefore expensive and not usually the preferred method of executing the invention. A preferred method of manufacturing the invention is to make the conducting extensions in the form of vias. The vias can be filled, i.e. solid, or hollow, i.e. in the form of a conducting tubes.
The invention is not restricted to the number of metal layers a chip structure comprises.
As previously described, the invention is not limited to any particular number of conductive extensions of the first and/or the second type.
Depending on where the side view of
According to the invention, parts of the structure can be used to make other passive elements and active elements.
The capacitive structure according to the invention can advantageously be used in transmission lines due to its capability to be distributed. The characteristic impedance, i.e. the per unit length impedance, of a transmission line is directly proportional to the characteristic inductance and inversely proportional to the characteristic capacitance. This means that an increase in the characteristic inductance will increase the characteristic impedance, and that an increase in the characteristic capacitance will decrease the characteristic impedance. The electrical length is directly proportional to the characteristic inductance and directly proportional to the characteristic capacitance. This means that an increase in the characteristic inductance will increase the electrical length, and that an increase in the characteristic capacitance will also increase the electrical length. An ability to further control a transmission line's characteristic capacitance is thus a powerful tool in forming a transmission line with specific characteristics.
As a summary, the invention can basically be described as a method, which provides an efficient on-chip capacitor. This is accomplished by creating conductive extensions that extend at least substantially perpendicular from at least two metal layer planes and overlap with dielectric in between thus creating a capacitive coupling between them. The invention is not limited to the embodiments described above but may be varied within the scope of the appended patent claims.
100 dielectric,
110 first plate,
120 second plate,
150 distance between first and second plate.
100 dielectric,
105 silicon wafer,
110 first ordinary metal layer,
121 first part of second ordinary metal layer,
122 second part of second ordinary metal layer,
161 via(s) between first part of second ordinary metal layer and first special thin metal plate,
162 via(s) between second part of second ordinary metal layer and second special thin metal plate,
171 first special thin metal plate,
172 second special thin metal plate.
100 dielectric,
105 silicon wafer,
111 first part of first metal layer,
112 second part of first metal layer,
121 first part of second metal layer,
122 second part of second metal layer,
131 first part of third metal layer,
132 second part of third metal layer,
211 first part of metal layer,
212 second part of metal layer.
300 dielectric,
310 first metal layer, first conducting point in a first plane,
320 second metal layer, second conducting point in a second plane,
352 distance between first and second conducting extensions,
354 overlap distance of first and second conducting extensions,
365 first conducting extension from first conducting point towards second plane,
366 second conducting extension form second conducting point towards first plane.
300 dielectric,
315 first metal layer, a first conducting plate in first plane,
325 second metal layer, a second conducting plate in a second plane,
365 first conducting extension from first conducting point towards second plane,
366 second conducting extension form second conducting point towards first plane,
391 capacitive coupling between first and second conducting plates,
393 capacitive coupling between second conducting extension and first conducting plate,
394 capacitive coupling between first and second conducting extensions,
395 capacitive coupling between first conducting extension and second conducting plate.
315 first conducting plate,
365 cross section of first conducting extension,
366 cross section of second conducting extension.
315 first conducting plate,
325 second conducting plate,
365 first conducting extension,
366 second conducting extension.
315 first conducting plate,
365 cross section of alternative form of first conducting extension,
366 cross section of alternative form of second conducting extension.
400 dielectric,
416 first metal layer, and a first conducting plate,
426 part of second metal layer, termination of via(s) from first metal layer/first conducting plate,
427 part of second metal layer, termination of via(s) from third metal layer/second conducting plate,
436 third metal layer, and a second conducting plate,
465 part of first conducting extension, a via between first and second metal layers,
466 part of second conducting extension, a via between second and third metal layers,
491 capacitive coupling between first and second conducting plates,
493 capacitive coupling between second metal layer of second conducting extension and first conducting plate,
494 capacitive coupling between first and second conductive extensions in the overlap area, in this example in the second metal layer where the vias of the first and second conductive extensions are terminated,
495 capacitive coupling between second metal layer of first conducting extension and second conducting plate,
426 second metal layer part of first conductive extension,
427 second metal layer part of second conductive extension,
465 via part of first conductive extension,
466 via part of second conductive extension.
400 dielectric,
418 first metal layer, first conductive plate,
428 second metal layer, intermediate termination for via(s) of first conductive extension,
429 second metal layer, termination for via(s) of second conductive extension,
438 third metal layer, termination for via of first conductive extension,
439 third metal layer, intermediate termination for via of second conductive extension,
448 fourth metal layer, second conductive plate,
465 first via part of first conductive extension,
466 first via part of second conductive extension,
467 second via part of first conductive extension,
468 second via part of second conductive extension.
500 dielectric,
511 first metal layer, first conductive plate,
521 second metal layer, intermediate termination for via(s) of first conductive extension,
522 second metal layer, termination for via(s) of second conductive extension,
531 third metal layer, termination for via(s) of first conductive extension,
532 third metal layer, intermediate termination for via(s) of second conductive extension,
541 fourth metal layer, second conductive plate,
561 first via part of first conductive extension,
562 second via part of first conductive extension,
572 second via part of second conductive extension,
573 first via part of second conductive extension.
521 second metal layer, intermediate termination for via(s) of first conductive extension,
522 second metal layer, termination for via(s) of second conductive extension,
561 first via part of first conductive extension,
572 second via part of second conductive extension.
621 second metal layer, intermediate termination for via(s) of first conductive extension,
622 second metal layer, termination for via(s) of second conductive extension,
661 first via part of first conductive extension,
672 second via part of second conductive extension.
711 first metal layer/first conductive plate,
722 second metal layer, termination for via(s) of conductive extensions from fourth metal layer/second conductive plate,
731 third metal layer, intermediate termination for conductive extension to RL,
732 third metal layer, intermediate termination for via(s) of conductive extensions from fourth metal layer/second conductive plate,
741 fourth metal layer/second conductive plate,
761 first via part from first metal layer to RL of second metal layer,
772 second via part from fourth metal layer via third metal layer to RL of second metal layer,
773 first via part from fourth metal layer,
781 RL segment of second metal layer.
865 first conductive extension(s) from first metal strip,
866 second conductive extension(s) from second metal strip,
884 second metal strip,
886 first metal strip.
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/SE03/02068 | 12/23/2003 | WO | 5/24/2007 |