TREA

Carbon filament memory and method for fabrication

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Information

  • Patent Application
  • 20080102278
  • Publication Number
    20080102278
  • Date Filed
    October 27, 2006
    18 years ago
  • Date Published
    May 01, 2008
    16 years ago
Information
Abstract
A nonvolatile memory cell is described, including a carbon layer system that includes an sp2-rich amorphous carbon layer and an sp3-rich amorphous carbon layer, wherein information is stored in the nonvolatile memory cell by reversibly forming an sp2-rich filament in the sp3-rich amorphous carbon layer.
Description
TECHNICAL FIELD

The present invention relates generally to memories and in one embodiment to a carbon filament memory.


BACKGROUND

Nonvolatile memory retains its stored data even when power is not present. This type of memory is used in a wide variety of electronic equipment, including digital cameras, portable audio players, wireless communication devices, personal digital assistants, and peripheral devices, as well as for storing firmware in computers and other devices.


Nonvolatile memory technologies include flash memory, magnetoresistive random access memory (MRAM), phase change random access memory (PCRAM), and conductive bridging random access memory (CBRAM). Due to the great demand for nonvolatile memory devices, researchers are continually developing new types of nonvolatile memory.


SUMMARY OF THE INVENTION

The invention provides a nonvolatile memory cell including a carbon layer system that includes an sp2-rich amorphous carbon layer and an sp3-rich amorphous carbon layer, wherein information is stored in the nonvolatile memory cell by reversibly forming an sp2-rich filament in the sp3-rich amorphous carbon layer.


These and other features of the invention will be better understood when taken in view of the following drawings and a detailed description.





BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the invention are described with reference to the following drawings, in which:



FIGS. 1A and 1B show a conventional conductive bridging memory element;



FIGS. 2A, 2B, and 2C show a carbon filament memory element in accordance with an embodiment of the invention;



FIG. 3 is a graph showing different resistances in a carbon filament memory element in accordance with an embodiment of the invention;



FIG. 4 is a graph showing V-I curves that demonstrate the memory effect of a carbon filament memory element in accordance with an embodiment of the invention;



FIG. 5 is a block diagram of a method for storing information in accordance with an embodiment of the invention;



FIG. 6 is a schematic diagram of a memory cell in accordance with an embodiment of the invention;



FIG. 7 is a block diagram showing a method for fabricating an array of memory cells in accordance with an embodiment of the invention;



FIGS. 8A, 8B, and 8C show a top view and cross section views of a memory array in accordance with an embodiment of the invention, following an intermediate step in the fabrication of the memory array;



FIGS. 9A and 9B show a top view and a cross section view of a memory array in accordance with an embodiment of the invention, following another step in the fabrication of the memory array; and



FIG. 10 shows an example computing system including a memory device using memory cells in accordance with an embodiment of the invention.





DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS


FIG. 1A shows a conventional conductive bridging junction (CBJ) for use in a conductive bridging random access memory (CBRAM) cell. A CBJ 100 includes a first electrode 102, a second electrode 104, and a solid electrolyte block 106 sandwiched between the first electrode 102 and the second electrode 104. The first electrode 102 contacts a first surface 108 of the solid electrolyte block 106, the second electrode 104 contacts a second surface 110 of the solid electrolyte block 106. One of the first electrode 102 and the second electrode 104 is a reactive electrode, the other one an inert electrode. In this example the first electrode 102 is the reactive electrode, and the second electrode 104 is the inert electrode. The first electrode 102 includes silver (Ag), the solid electrolyte block 106 includes a silver-doped chalcogenide material.


When a voltage is applied across the solid electrolyte block 106, a redox reaction is initiated that drives Ag+ ions out of the first electrode 102 into the solid electrolyte block 106 where they are reduced to Ag, thereby forming Ag rich clusters within the solid electrolyte block 106. If the voltage applied across the solid electrolyte block 106 is applied for a long period of time, the size and the number of Ag rich clusters within the solid electrolyte block 106 is increased to such an extent that a conductive bridge 114 between the first electrode 102 and the second electrode 104 is formed.


As shown in FIG. 1B, when an inverse voltage to that applied in FIG. 1A is applied across the solid electrolyte 106, a redox reaction is initiated that drives Ag+ ions out of the solid electrolyte block 106 into the first electrode 102 where they are reduced to Ag. As a consequence, the size and the number of Ag rich clusters within the solid electrolyte block 106 are reduced, thereby reducing, and eventually removing the conductive bridge 114.


To determine the current memory state of the CBJ 100, a sensing current is routed through the CBJ 100. The sensing current encounters a high resistance if no conductive bridge 114 exists within the CBJ 100, and a low resistance when a conductive bridge 114 is present. A high resistance may, for example, represent “0”, while a low resistance represents “1”, or vice versa.


In accordance with the invention, a process of forming a reversible conductive filament may be used to construct an information storage element using a carbon layer system including layers of sp2-rich and sp3-rich (also known as diamond-like carbon, or DLC) amorphous carbon films.


Referring to FIG. 2A, an embodiment of a memory junction in accordance with the invention is described. A memory junction 200 includes a top contact 202, a first carbon layer 204 including an amorphous carbon material rich in sp2 hybridized carbon atoms, a second carbon layer 206 including an amorphous carbon material rich in sp3 hybridized carbon atoms, and a bottom contact 208. The first carbon layer 204 and second carbon layer 206 form a carbon bi-layer system 210 in which a conductive filament may be formed, as described further below. Generally, the sp2-rich carbon is conductive, while the sp3-rich carbon is an electrical insulator, having low conductivity. If the resistance of the first carbon layer 204 (i.e., the sp2-rich carbon layer) is denoted as R1, and the resistance of the second carbon layer 206 (the sp3-rich layer) is R2, for many embodiments the ratio R2/R1 may be greater than 100, for example greater than 1000, e.g., greater than 10000.


As shown in FIGS. 2B and 2C, by forcing a current through the carbon bi-layer system 210, an sp2 filament 250 can be formed in the sp3-rich second carbon layer 206, changing the conductivity (and resistance) of the carbon bi-layer system. Within the second carbon layer 206, the current causes a change in the structure of the material, from atomic scale sp2/sp3 disorder to a disordered graphitic sp2-domain network, through the migration of sp3 defects. The current induces the migration of sp2-rich clusters to form a percolation path network of graphitic sp2 domains, which causes an insulator-to-metal transition. Electron transport in the sp2-rich metallic state features weakly temperature-dependent conductivity with a majority of hole and a minority of electron carriers. A one-dimensional channel arises due to filamentary conduction through localized sp2-rich regions within the sp3 carbon barriers, and particularly within the barrier adjacent to the electron injector. This limits the electrical conduction at low bias. Additionally, this may involve the orientation of π orbitals of sp2-bonded carbon molecules when subject to a high electric field, leading to increased electron transmission, although the present invention is not limited to a particular theory of operation.


Application of a current with reversed polarity reverses the migration of sp2 domains in the sp3-rich second carbon layer 206, reducing the sp2 filament 250, and the conductivity (and increasing the resistance) of the carbon bi-layer system 210. The reversibility of the formation of sp2 filaments permits the carbon bi-layer system 210 to be used as the basis of a memory cell, in which the states of the memory cell are represented by the high and low conductivity (corresponding to low and high resistance) of the carbon bi-layer system 210.


While formation of filaments would occur even in the absence of the sp2-rich first carbon layer 204, the reliable creation of sp2 filaments in sp3-rich material can be substantially enhanced by the presence of an sp2-rich layer, such as the first carbon layer 204.


The thickness of the sp3-rich second carbon layer 206 is related to the desired voltages and speed for the operation of the memory. Switching (i.e., formation or removal of filaments) may occur in an electric field of less than one volt per nm of thickness of the material. For example, for an operating voltage of 3V, the thickness of the second carbon layer 206 may be approximately 4 nm. The thickness of the sp2-rich first carbon layer 204 does not have a substantial effect, and the first carbon layer 204 may have almost any thickness, from a monolayer to a thickness of hundreds of nm.


As the applied voltage is increased, additional conducting channels may form in the sp3-rich second carbon layer 206, providing different resistances that may be used in some embodiments for multi-bit storage in a single memory cell. FIG. 3 shows a curve 300 representing the resistance in an 8 nm thick sp3-rich film, as voltage varies. The curve 300 includes quantized resistance steps 302a-302e, in multiples of h/(2e2), where h is Planck's constant and e is the electron charge, indicating the formation of additional conducting channels in the sp3-rich carbon film.



FIG. 4 illustrates the memory effect following the application of voltage to an sp3-rich film. The I-V curve 400 shows the current/voltage relationship for an approximately 8 nm thick sp3-rich film prior to the formation of carbon filaments in the sp3 -rich film. The I-V curve 402 shows the current/voltage relationship after formation of filaments using a voltage pulse of approximately 6 volts, demonstrating the memory effect.



FIG. 5 shows a block diagram of a method for storing information according to an embodiment of the invention. In step 502, a carbon bi-layer system, as described above, including an sp2-rich amorphous carbon layer and an sp3-rich amorphous carbon layer is provided. In step 504, information is stored in the carbon bi-layer system by applying a current through the carbon bi-layer system to cause the growth of a filament of sp2-rich carbon in the sp3-rich layer, decreasing the resistance of the carbon bi-layer system. By applying a current with reversed polarity, the growth of the filament can be reversed. Additionally, quantized resistance steps, such as are shown in FIG. 3, can be used to store multiple bits of information in the carbon bi-layer system.



FIG. 6 shows an illustrative memory cell that uses a memory junction such as is shown in FIGS. 2A-2C, with still others being apparent to workers in the art and included herein. The memory cell 600 includes a select transistor 602 and a memory junction 604, which uses a carbon bi-layer system, in accordance with the invention. The select transistor 602 includes a source 606 that is connected to a bit line 608, a drain 610 that is connected to the memory junction 604, and a gate 612 that is connected to a word line 614. The memory junction 604 is also connected to a common line 616, which may be connected to ground, or to other circuitry, such as circuitry (not shown) for determining the resistance of the memory cell 600, for use in reading. It should be noted that as used herein the terms connected and coupled are intended to include both direct and indirect connection and coupling, respectively.


To write to the memory cell, the word line 614 is used to select the cell 600, and a current on the bit line 608 is forced through the memory junction 604, to form or remove filaments in the memory junction 604, changing the resistance of the memory junction 604. Similarly, when reading the cell 600, the word line 614 is used to select the cell 600, and the bit line 608 is used to apply a voltage across the memory junction 604 to measure the resistance of the memory junction 604.


The memory cell 600 may be referred to as a 1T1J cell, because it uses one transistor, and one memory junction. Typically, a memory device will include an array of many such cells. It will be understood that other configurations for a 1T1J memory cell could be used with a carbon bi-layer memory junction according to the invention. Additionally, cell configurations other than a 1T1J configuration may be used.


Referring to FIG. 7, an illustrative method for fabricating an array of 1T1J memory cells including a memory junction using a carbon bi-layer system is described. However, the fabrication may be accomplished by any method known in the art or hereafter developed that is suitable for forming the inventive structure.


At the start of the method 700, a shallow trench isolation (STI) structure in the array and periphery has been fabricated on a semiconductor wafer or other suitable substrate. In step 702, gates and word lines are formed above the STI structure. This involves the conventional application of a gate oxide layer, gate conductor deposition and structuring, sidewall spacer formation, and related implants.


In step 704 SiO2 is removed from the source and drain regions. This may be accomplished, for example, through the application of diluted HF. Optionally, selective epitaxial growth of Si may be used to form elevated source and drain regions.


This is followed, in step 706, by a salicidation process, for example forming CoSi, NiSi, TiSi, or another suitable silicide. Salicidation can be omitted in parts or all of the periphery by using a blocking mask. Optionally, salicided areas where no contacts will be fabricated may be covered with resist.


Step 708 is an ILD (Interlayer Dielectric) deposition step which can be, for example, an SiO2 deposition and planarization step, which is followed in step 710 by etching contact holes (vias) and filling them with contact plugs including a suitable conductive material, such as W, poly-Si, or a conductive carbon material. Back etching and planarization may be used to prepare a level surface for the wafer.


In step 712, bit lines are formed, which are connected to the common source of two neighboring transistors. This may be achieved by using a lithographic process to mask portions of the SiO2 layer, etching the SiO2 and the common source contact plug for formation of the bit lines. This is followed by deposition of the bit lines (using poly-Si, W, or other suitable conductive materials) and recess.


In step 714, further (ILD) SiO2 is deposited, burying the bit lines. Chemical mechanical polishing (CMP) may be used for planarization, stopping on the contact plugs, to prepare the surface for further steps.


In step 716, the sp3-rich and sp2-rich carbon layers are deposited to form the carbon bi-layer system for the memory junction. Deposition of these layers may be achieved by physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), ablation of a graphite target using a 248 nm pulsed ultraviolet excimer laser, or another suitable method of depositing a material on a substrate.


The sp2 to sp3 ratio in the deposited carbon materials may be varied by a number of methods, depending on the deposition technique used. For example, if the carbon layers are produced using PECVD deposition, the ratio may be controlled by adjusting the bias voltage, gas pressure, and temperature during the deposition of the material. For example, the PECVD process may be carried out in an inductively coupled high-density plasma with a stimulation frequency of approximately 20 MHz to approximately 40 MHz, e.g., with a stimulation frequency of approximately 25 MHz to approximately 30 MHz, e.g., with a stimulation frequency of approximately 27.26 MHz. In this case, the substrate, including the layer stack that has already been manufactured, is placed on a substrate holder where it is possible to apply an RF bias voltage. Additional ions having the appropriate energy can be pulled onto the substrate by means of the RF bias voltage. Additionally, the substrate can be heated. In some embodiments, CxHy (x and y are arbitrary natural number), e.g., C2H2 or CH4, can be used as the reactive gas. Optionally, the reactive gas can be diluted using Ne, H2 or Ar.


The level of the substrate bias voltage is determined by the reactor geometry (i.e. the ratio of the dimensions of the mass carrying electrode and the RF carrying electrode in the reactor), and by the self-bias, which is applied or is adjusted to by an externally applied capacitively coupled-in RF field. In particular, the externally applied capacitively coupled-in RF field determines the layer characteristics and, for example, the occurring bondings, such as sp3 or sp2 bondings, and their relative amount and mixture. In an exemplary embodiment, a negative voltage in the range of approximately 50 V to approximately 350 V is applied together with a gas pressure in the range of approximately 10 mTorr to approximately 500 mTorr. For a low conductivity layer a small voltage of, e.g., 50 V may be applied and for a highly conductive layer a voltage of, e.g., 300 V may be applied.


Alternatively, the ratio of sp2 to sp3 may be determined by forming the layers by sputtering. This may be achieved, for example, using a graphite target in an argon atmosphere, at a pressure of approximately 1 Pa, with the substrate approximately 3 cm from the target. By varying the temperature in a range of approximately 77 K to 500 K, and the sputtering power from approximately 5 W to approximately 300 W, the resistivity of the material may be varied. For a low conductivity layer a small power of, e.g., 5 W may be applied and for a highly conductive layer a power of, e.g., 300 W may be applied.


Alternatively, the ratio of sp2 to sp3 may be determined by forming the layers by laser ablation. A 248 nm pulsed ultraviolet excimer laser (e.g., Lambda Physik LPX 210i) at a chamber pressure of approximately 10−7 mbar may be employed, and the fluence of the laser may be varied to synthesize two types of amorphous-carbon layers (using, for example, approximately 4 J cm−2 for sp2-rich layers and approximately 20 J cm−2 for sp3-rich layers).


The amounts of sp2 and sp3 hybridized carbon present in a deposited film may also be adjusted by post-deposition annealing, or by other conventional techniques for depositing films of diamond-like carbon.


In step 718, the top electrode, including a highly conductive material such as poly-Si, W, Ti, or Ta is deposited above the carbon bi-layer system.


In step 720, lithography and etching are used to define the areas covered by the carbon bi-layer system and top electrode. Following this step, additional processing of the semiconductor wafer may be performed using conventional processes.



FIGS. 8A-8C illustrate one intermediate step in the above-described process. In particular, they show a portion of the array following step 710, in which the contact holes are etched and filled with a material such as W, poly-Si, or carbon. FIG. 8A shows a top view of a portion of a memory array 800, including active areas 802, word lines 804, and filled contact holes 806. As can be seen from the layout of the portion of the memory array 800, the density of memory cells in an array may be increased by sharing each active area 802 (in this case, sharing a source region) between two cells, each with its own word line. The staggered arrangement of the active areas 802 also contributes to increasing the density of memory cells in the array. It will be understood that other layouts of memory cells and active areas may also be used, and that the layout shown in FIGS. 8A-8C is for the purpose of illustration.



FIG. 8B shows a cross section of the portion of the memory array 800 along Cut A-A of FIG. 8A. This cross section shows one active area 802, and two word lines 804, connected to transistor gates 820. Filled contact holes 806 have been etched through an SiO2 layer 822 to connect to a source contact area 824, and to two drain contact areas 826. The active areas 802 are separated by STI areas 828.



FIG. 8C shows a second cross section of the portion of the memory array 800 along Cut B-B of FIG. 8A. This cross section shows portions of three active areas 802, separated by STI areas 828. Filled contact holes 806, etched through the SiO2 layer 822 connect to drain contact areas 826.



FIGS. 9A and 9B show a similar view, following step 720 of the method 700, described above with reference to FIG. 7. FIG. 9A is a top view, showing the portion of a memory array 900, which is the same as the portion of the memory array 800 described with reference to FIGS. 8A-8C, but at a later stage in processing. As can be seen, the portion of the memory array 900 now includes top electrodes 902, which are deposited above carbon bi-layer memory junctions.



FIG. 9B shows a cross section of the portion of the memory array 900 along Cut A-A, which is similar in location to the cross section shown above in FIG. 8B. The cross section shows an active area 920, and two word lines 922, connected to transistor gates 924. Vias (or contact plugs) 926 connect to two drain contact areas 928, and to carbon bi-layer memory junctions 930, which are connected to top electrodes 902. A bit line 932 connects to a source contact region 934 through a via 936. STI areas 938 separate the active area 920 from other active areas.


As can be seen in this cross section, the bit line 932, via 936, and source contact region 934 are shared by two memory cells, each of which includes a transistor and a carbon bi-layer memory junction 930. It will be understood that other layouts for memory cells may be used in accordance with the principles of the invention.


Memory cells such as are described above may be used in memory devices that contain large numbers of such cells. These cells may, for example, be organized into an array of memory cells having numerous rows and columns of cells, each of which stores one or more bits of information. Memory devices of this sort may be used in a variety of applications or systems, such as the illustrative system shown in FIG. 10.



FIG. 10 shows an example computing system that uses a memory device constructed of memory cells in accordance with the invention. The computing system 1000 includes a memory device 1002, which may utilize memory cells in accordance with the invention. The system also includes a processor 1004, and one or more input/output devices, such as a keypad 1006, display 1008, and wireless communication device 1010. The memory device 1002, processor 1004, keypad 1006, display 1008 and wireless communication device 1010 are interconnected by a bus 1012.


The wireless communication device 1010 may include circuitry (not shown) for sending and receiving transmissions over a cellular telephone network, a WiFi wireless network, or other wireless communication network. It will be understood that the variety of input/output devices shown in FIG. 10 is merely an example, in which the computing system 1000 may be configured as a cellular telephone or other wireless communications device. Memory devices including memory cells in accordance with the invention may be used in a wide variety of systems. Alternative system designs may include different input/output devices, multiple processors, alternative bus configurations, and many other configurations.


In summary, in some embodiments a nonvolatile memory cell includes a carbon layer system that includes an sp2-rich amorphous carbon layer and an sp3-rich amorphous carbon layer, wherein information is stored in the nonvolatile memory cell by reversibly forming an sp2-rich filament in the sp3-rich amorphous carbon layer. In some such embodiments, the sp2-rich filament changes the conductivity of the carbon layer system. In some embodiments, the sp3-rich amorphous carbon layer has a thickness of 5 nm or less. Some embodiments further include a select transistor coupled to the carbon layer system. In some embodiments, the carbon layer system stores multiple bits of information. In some of these embodiments different resistance states, for example, quantized resistance steps according to certain embodiments, of the carbon layer system are used to store the multiple bits of information. In some embodiments, application of a first current through the carbon layer system causes growth of the sp2-rich filament, and in some of these embodiments, application of a second current, having a reversed polarity with respect to the first current, causes reduction of the sp2-rich filament. In some embodiments, the carbon layer system may be a carbon bi-layer system.


In further embodiments of the invention, an information storage element includes a first carbon layer including an amorphous carbon film including sp2 hybridized carbon and sp3 hybridized carbon, the first carbon layer having a substantially higher proportion of sp2 hybridized carbon than sp3 hybridized carbon, and a second carbon layer disposed adjacent to the first carbon layer, the second carbon layer including an amorphous carbon film including sp2 hybridized carbon and sp3 hybridized carbon, the second carbon layer having a substantially higher proportion of sp3 hybridized carbon than sp2 hybridized carbon. Information is stored by forcing a first current through the first carbon layer and the second carbon layer to cause growth of a filament in the second carbon layer, the filament having a substantially higher proportion of sp2 hybridized carbon than sp3 hybridized carbon. In some of these embodiments, the filament is reduced by forcing a second current, having a reversed polarity with respect to the first current, through the first carbon layer and the second carbon layer. In some embodiments, the second carbon layer has a thickness of 5 nm or less.


In some embodiments, the first carbon layer has a resistivity (specific resistance) R1, the second carbon layer has a specific resistance R2, and a ratio R2/R1 is greater than 100 when the filament is absent, for example greater than 1000, e.g., greater than 10000. In certain embodiments, growth of the filament increases the conductivity of the information storage element. In some embodiments different resistance states of the information storage element are used to store multiple bits of information in the information storage element.


In some embodiments, the invention provides a nonvolatile memory cell including a transistor, and a carbon layer system, including a first carbon layer, having a first specific resistance R1, and a second carbon layer, having a second specific resistance R2, such that the ratio R2/R1 is greater than 100, for example greater than 1000, e.g., greater than 10000. One of the layers of the carbon layer system is connected to a drain portion of the transistor for use as a memory cell.


In some embodiments, the invention provides a method for storing information, including providing a carbon layer system that includes an sp2-rich amorphous carbon layer and an sp3-rich amorphous carbon layer, and reversibly forming an sp2-rich filament in the sp3-rich amorphous carbon layer to store the information. In some embodiments, reversibly forming an sp2-rich filament includes applying a first current through the carbon layer system to cause growth of the sp2-rich filament. In certain of these embodiments, reversibly forming an sp2-rich filament includes applying a second current, having a reversed polarity with respect to the first current, to cause reduction of the sp2-rich filament.


In some embodiments, reversibly forming an sp2-rich filament comprises changing the resistance of the carbon layer system, which includes changing the resistance continuously in certain of these embodiments, and changing the resistance in steps, for example, in quantized steps, in others of these embodiments. In some embodiments, changing the resistance in steps includes using the different steps to represent multiple bits of information, and in some embodiments, changing the resistance includes using the different resistance values to represent multiple bits of information.


In further embodiments, the invention provides a method of fabricating a nonvolatile memory device, including depositing a first carbon layer including an amorphous carbon film including sp2 hybridized carbon and sp3 hybridized carbon, the first carbon layer having a substantially higher proportion of sp2 hybridized carbon than sp3 hybridized carbon. The method also includes depositing a second carbon layer disposed adjacent to the first carbon layer, the second carbon layer including an amorphous carbon film including sp2 hybridized carbon and sp3 hybridized carbon, the second carbon layer having a substantially higher proportion of sp3 hybridized carbon than sp2 hybridized carbon. Additionally, the method includes forming contacts that permit a current to be selectively applied through the first carbon layer and second carbon layer. In some embodiments, the method further includes forming a transistor having a drain region that is coupled to at least one of the contacts to selectively apply current through the first carbon layer and second carbon layer.


In some embodiments, the invention provides a method of fabricating a nonvolatile memory device, including depositing on a semiconductor wafer a carbon layer system including a first layer, having a first resistance R1, and a second carbon layer, having a second resistance R2, such that R2/R1 is greater than 100, for example, greater than 1000, e.g., greater than 10000.


In additional embodiments of the invention, the invention provides a computing system including an input device, and output device, a processor, and a nonvolatile memory, the nonvolatile memory including a carbon layer system that has an sp2-rich amorphous carbon layer and an sp3-rich amorphous carbon layer, wherein information is stored in the nonvolatile memory cell by reversibly forming an sp2-rich filament in the sp3-rich amorphous carbon layer. In some such embodiments, the output device includes a wireless communications device.


While the invention has been shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes that come within the meaning and range of equivalency of the claims are intended to be embraced.

Claims
  • 1. A nonvolatile memory cell comprising: a carbon layer system that includes an sp2-rich amorphous carbon layer and an sp3-rich amorphous carbon layer,wherein information can be stored in the nonvolatile memory cell by reversibly forming an sp2-rich filament in the sp3-rich amorphous carbon layer.
  • 2. The nonvolatile memory cell of claim 1, wherein the sp2-rich filament changes a conductivity of the carbon layer system.
  • 3. The nonvolatile memory cell of claim 1, wherein the sp3-rich amorphous carbon layer has a thickness of 5 nm or less.
  • 4. The nonvolatile memory cell of claim 1, further comprising a select transistor coupled to the carbon layer system.
  • 5. The nonvolatile memory cell of claim 1, wherein the carbon layer system stores multiple bits of information.
  • 6. The nonvolatile memory cell of claim 5, wherein different resistance states of the carbon layer system are used to store the multiple bits of information.
  • 7. The nonvolatile memory cell of claim 1, wherein application of a first current through the carbon layer system causes growth of the sp2-rich filament.
  • 8. The nonvolatile memory cell of claim 7, wherein application of a second current, having a reversed polarity with respect to the first current, causes reduction of the sp2-rich filament.
  • 9. The nonvolatile memory cell of claim 1, wherein the carbon layer system comprises a carbon bi-layer system.
  • 10. An information storage element, comprising: a first carbon layer comprising an amorphous carbon film including sp2 hybridized carbon and sp3 hybridized carbon, the first carbon layer having a higher proportion of sp2 hybridized carbon than sp hybridized carbon; anda second carbon layer disposed adjacent to the first carbon layer, the second carbon layer comprising an amorphous carbon film including sp2 hybridized carbon and sp3 hybridized carbon, the second carbon layer having a higher proportion of sp3 hybridized carbon than sp2 hybridized carbon,wherein information is stored by forcing a first current through the first carbon layer and the second carbon layer to cause growth of a filament in the second carbon layer, the filament having a substantially higher proportion of sp2 hybridized carbon than sp3 hybridized carbon.
  • 11. The information storage element of claim 10, wherein the filament is reduced by forcing a second current, having a reversed polarity with respect to the first current, through the first carbon layer and the second carbon layer.
  • 12. The information storage element of claim 10, wherein the first carbon layer has a resistance R1, the second carbon layer has a resistance R2, and wherein a ratio R2/R1 is greater than 100 when the filament is absent.
  • 13. The information storage element of claim 10, wherein growth of the filament increases a conductivity of the information storage element.
  • 14. The information storage element of claim 10, wherein the second carbon layer has a thickness of 5 nm or less.
  • 15. The information storage element of claim 10, wherein different resistance states of the information storage element are used to store multiple bits of information in the information storage element.
  • 16. A nonvolatile memory cell comprising: a transistor; anda carbon layer system, comprising a first carbon layer, having a first resistance R1, and a second carbon layer, having a second resistance R2, such a ratio R2/R1 is greater than 100,wherein one of the layers of the carbon layer system is connected to a drain portion of the transistor.
  • 17. A method for storing information, comprising: providing a carbon layer system that includes an sp2-rich amorphous carbon layer and an sp3-rich amorphous carbon layer; andreversibly forming an sp2-rich filament in the sp3-rich amorphous carbon layer to store the information.
  • 18. The method of claim 17, wherein reversibly forming the sp2-rich filament comprises applying a first current through the carbon layer system to cause growth of the sp2-rich filament.
  • 19. The method of claim 18, wherein reversibly forming the sp2-rich filament further comprises applying a second current, having a reversed polarity with respect to the first current, to cause reduction of the sp2-rich filament.
  • 20. The method of claim 17, wherein reversibly forming the sp2-rich filament comprises changing a resistance of the carbon layer system.
  • 21. The method of claim 20, wherein changing the resistance of the carbon layer system comprises changing the resistance in steps.
  • 22. The method of claim 21, wherein changing the resistance in steps further comprises using different steps to represent multiple bits of information.
  • 23. A method of fabricating a nonvolatile memory device, comprising: depositing a first carbon layer comprising an amorphous carbon film including sp2 hybridized carbon and sp hybridized carbon, the first carbon layer having a higher proportion of sp2 hybridized carbon than sp3 hybridized carbon;depositing a second carbon layer adjacent to the first carbon layer, the second carbon layer comprising an amorphous carbon film including sp2 hybridized carbon and sp3 hybridized carbon, the second carbon layer having a higher proportion of sp3 hybridized carbon than sp2 hybridized carbon; andforming contacts that permit a current to be selectively applied through the first carbon layer and second carbon layer.
  • 24. The method of claim 23, further comprising forming a transistor having a drain region that is coupled to at least one of the contacts to selectively apply current through the first carbon layer and second carbon layer.
  • 25. A method of fabricating a nonvolatile memory device, comprising depositing on a semiconductor wafer a carbon layer system comprising a first carbon layer, having a first resistance R1, and a second carbon layer, having a second resistance R2, such that a ratio R2/R1 is greater than 100.
  • 26. A computing system comprising: an input device;an output device;a processor coupled to the input device and the output device; anda nonvolatile memory coupled to the processor, said nonvolatile memory comprising a carbon layer system that includes an sp2-rich amorphous carbon layer and an sp3-rich amorphous carbon layer, wherein information is stored in the nonvolatile memory by reversibly forming an sp2-rich filament in the sp3-rich amorphous carbon layer.
  • 27. The computing system of claim 26, wherein the output device comprises a wireless communications device.