Patent Application
20220141954
A carrier with downsized through-via is disclosed.
A printed circuit board is a carrier for electrical or electronic components and usually has a mounting surface comprising a plurality of connection pads, conductor tracks and closure caps. Their spacing from each other and their arrangement on the mounting surface are limited by minimum structural widths of the connection pads, conductor tracks and closure caps. Depending on the complexity of the wiring, a printed circuit board can be formed as a single-layer, double-layer or multilayer printed circuit board. A vertical connection between the layers is achieved in particular by through-vias, whose minimum diameter is often greater than 125 μm or greater than 150 μm in conventional producing processes. A closure cap covering the associated through-via thus has an even larger diameter, which is usually significantly larger than the minimum structure width of a layer. These typical structure widths and dimensions limit the design of the mounting surface and, in particular, the packing density of the components. Furthermore, difficulties arise in connecting components with closely spaced contact surfaces.
Embodiments provide a carrier which is suitable for accommodating electrical or electronic, in particular, optoelectronic components and has a particularly compact mounting surface for accommodating the largest possible number of components. Further embodiments provide a reliable and cost-efficient method for producing such a carrier.
Embodiments provide a carrier having a base substrate. In particular, the base substrate is formed with respect to its material composition and/or its layer thickness such that it mechanically supports and/or mechanically stabilizes the carrier. If the carrier has a plurality of further layers, these layers are also mechanically supported in particular by the base substrate. Of all the layers of the carrier, in particular the base substrate exhibits the highest mechanical stability. The base substrate can be a printed circuit board, a metal core board, a plastic body or a ceramic body. In particular, the base substrate has a plurality of glass fibers, which are for instance woven together and/or stacked on top of each other, and for instance embedded in an epoxy resin or epoxy-like resin. It is possible that the base substrate is formed from laminated layers of pre-impregnated fiber layers, so-called prepreg layers. Preferably, the base substrate is producible in a panel.
According to at least one embodiment of the carrier, it comprises an inner wiring layer and an outer wiring layer. In particular, the inner wiring layer is arranged on the base substrate, wherein a direct arrangement of the inner wiring layer on the base substrate is preferred. In the vertical direction, the inner wiring layer is spatially separated from the outer wiring layer, for example, by an insulating layer of the carrier. The outer wiring layer may be formed on the insulating layer, preferably directly on the insulating layer. The insulating layer and the base substrate may have different material compositions and/or different layer thicknesses. For example, the insulating layer is applied onto the base substrate and in this sense is mechanically supported by the base substrate. Further preferably, both the insulating layer and the base substrate are electrically insulating.
According to at least one embodiment of the carrier, it has at least one through-via in the insulating layer, which extends throughout the insulating layer and electrically connects the inner wiring layer to the outer wiring layer. Since the base substrate is formed, in particular with regard to its layer thickness and material composition, in such a way that the carrier is mechanically stabilized mainly by the base substrate and is thus mechanically supported by the base substrate, the insulating layer can be formed to be particularly thin. Since the insulating layer is not or hardly configured for mechanically stabilizing the carrier, this design of the insulating layer allows a wide range of materials for the insulating layer.
Due to the low layer thickness of the insulating layer, the through-via can be formed throughout the insulating layer in a comparatively simple manner. For example, an opening is formed throughout the insulating layer and subsequently filled with an electrically conductive material for forming the through-via. Due to the low layer thickness of the insulating layer, the opening can be made correspondingly small without any difficulties in filling the opening, for example, with regard to wetting or capillary effects. In particular, the through-via has a lateral cross-section that has a maximum lateral extent or diameter of at most 100 μm, 90 μm, 80 μm, 75 μm or of at most 50 μm. Further preferably, this maximum lateral extent or diameter is between 10 μm and 100 μm, inclusive.
A lateral direction is understood in the present context to be a direction parallel to a main extension surface of the carrier and/or of the base substrate, for example parallel to a mounting surface of the carrier. A vertical direction is herein understood to be a direction that is perpendicular to the main extension surface of the carrier and/or of the base substrate, for example perpendicular to the mounting surface of the carrier. The vertical direction and the lateral direction are arranged transversely or preferably orthogonally to each other.
In at least one embodiment of the carrier, it comprises a base substrate, at least one insulating layer, at least one inner wiring layer, at least one outer wiring layer, and at least one through-via in the insulating layer. In particular, the through-via extends throughout the insulating layer. Preferably, the base substrate and the insulating layer are formed of different materials. The base substrate is configured to mechanically stabilize the carrier and, in particular, supports the insulating layer. The inner wiring layer is arranged in the vertical direction at least in places between the base substrate and the insulating layer. The outer wiring layer is spatially separated from the inner wiring layer at least in places by the insulating layer. The through-via connects the inner wiring layer to the outer wiring layer in an electrically conductive manner. Particularly preferably, the through-via has a lateral cross-section with a maximum lateral extent of at most 100 μm.
The carrier thus has at least two different wiring layers which are separated from one another by a thin insulating layer and are electrically conductively connected to one another by the through-via. Since the carrier is formed at least in a double-layered manner, the outer wiring layer, whose surface in particular forms a mounting surface of the carrier, can have larger connection pads or a higher number of connection pads for accommodating a higher number of components. Since the wiring is realized in places via the through-via or via a plurality of through-vias, the number of conductor tracks on the mounting surface can be reduced. Since the through-via also has a comparatively small lateral cross-section, a closure cap of the through-via on the mounting surface can be formed to have smaller size.
Due to the multilayer design of the carrier and to the comparatively small dimensions of the through-via, more free space thus advantageously remains on the mounting surface for the formation of connection pads for receiving electrical components which are mounted on these connection pads. It is possible that the closure caps are formed as connection pads. Due to the reduced number of required conductor tracks and the reduced size of the closure caps, the mounting surface can have more or larger connection pads on which the components can be mounted. In this sense, the carrier may have a particularly compact design and/or accommodate a higher number of components.
According to at least one embodiment of the carrier, the inner wiring layer is arranged on the base substrate. In particular, the wiring layer is formed in a structured manner such that the insulating layer is directly adjacent to the base substrate in regions and directly adjacent to the inner wiring layer in other regions. For example, the inner wiring layer is formed from a structured cover layer of the base substrate. The structured cover layer of the base substrate may be divided into a plurality of spatially separated or interconnected subregions. These sub-regions may be in the form of conductor tracks and/or closure caps.
Corresponding to the inner wiring layer, the outer wiring layer may be formed as a structured cover layer comprising a plurality of connection pads, closure caps and/or conductor tracks. The outer wiring layer may be formed directly on the insulating layer. The through-via or the plurality of through-vias extend throughout the insulating layer, as a result of which the inner wiring layer is electrically conductively connected to the outer wiring layer. In particular, the size or geometry of the inner wiring layer is different from the size or geometry of the outer wiring layer. The closure caps of the outer wiring layer may be made larger or smaller than the corresponding closure caps of the inner wiring layer.
According to at least one embodiment of the carrier, it includes a through-via in the base substrate, which is electrically conductive and extends in particular throughout the base substrate. This through-via is referred to below as base through-via. Particularly preferably, the base through-via has a larger lateral cross-section than the through-via in the insulating layer. For example, the base through-via in the base substrate has a cross-section with a maximum lateral extent or diameter of at least 100 μm, 125 μm, 150 μm or 200 μm.
In particular, the through-via in the base substrate is not adjacent to, or does not extend through, the insulating layer. Thus, a closure cap of the outer wiring layer that completely covers the through-via in the insulating layer in top view may have a smaller cross-section or a smaller maximum lateral extent than a corresponding closure cap of the inner wiring layer that completely covers the through-via in the base substrate in top view. The through-via in the base substrate has a lateral diameter that is at least 25%, 50%, 75%, 100% or at least 200% larger than a lateral diameter of the through-via in the insulating layer. In case of doubt, the lateral diameter is to be understood as the maximum lateral extent of the through-via.
According to at least one embodiment of the carrier, it comprises a further wiring layer. The inner wiring layer and the further wiring layer are arranged in particular on opposite surfaces of the base substrate. The inner wiring layer and the further wiring layer can be electrically conductively connected to one another via the through-via or via the through-vias in the base substrate. The further wiring layer may be formed as a further inner wiring layer of the carrier or as an outer, rear-side wiring layer of the carrier.
According to at least one embodiment of the carrier, it comprises a further insulating layer, a further inner wiring layer, a further outer wiring layer and one or a plurality of further through-vias in the further insulating layer. The further through-via or through-vias extend throughout the further insulating layer. The base substrate is arranged in the vertical direction between the inner wiring layers as well as between the insulating layers. The further through-via can electrically conductively connect the further inner wiring layer to the further outer wiring layer.
The through-via and the further through-via in the insulating layer and in the further insulating layer, respectively, may have diameters or maximum lateral expansions of the same order of magnitude. For example, the through-via or the further through-via has a maximum diameter of at most 100 μm, 75 μm or of at most 50 μm. Preferably, the carrier in this case is at least four-layered. In other words, the carrier has at least four wiring layers.
For example, the carrier has two inner wiring layers arranged directly on the base substrate, namely on two opposite surfaces of the base substrate. The carrier may have two outer wiring layers, each of which is accessible from the outside, for example, and each of which is arranged in particular directly on one of the insulating layers. It is conceivable that additional wiring layers and/or additional insulating layers are arranged between an inner and an outer wiring layer. Furthermore, it may be provided that one of the outer wiring layers forms the mounting surface of the carrier and the other of the outer wiring layers forms a rear side of the carrier facing away from the mounting surface. In particular, the base substrate is located along the vertical direction between the insulating layer and the further insulating layer. The insulating layers may be formed of the same material or of different materials.
According to at least one embodiment of the carrier, the through-via in the insulating layer and/or the further through-via in the further insulating layer have/has a lateral cross-section with a maximum lateral extent of at most 75 μm or of at most 50 μm. For example, the maximum lateral extent is between 10 μm and 100 μm inclusive, for example between 30 μm and 100 μm inclusive or between 50 μm and 100 μm inclusive.
Along the vertical direction, the through-via and/or the further through-via may have a constant cross-section, a constant diameter or a constant maximum lateral extent. In contrast, it is possible that the through-via in the insulating layer and/or the further through-via in the further insulating layer have a decreasing lateral cross-section with a correspondingly decreasing lateral dimension or diameter as the vertical distance from the base substrate increases. At an outer wiring layer, the cross-section, diameter or maximum lateral extent of the through-via or further through-via can thus be made smaller. As a result, the lateral extent of the closure cap or the connection pad, which covers, in particular completely covers the through-via in top view, can also be further reduced.
According to at least one embodiment of the carrier, the inner wiring layer has an inner closure cap which, in top view, completely covers the through-via in the base substrate. The inner closure cap may be directly adjacent to the through-via in the base substrate. The outer wiring layer may have an outer closure cap adjacent to the through-vias in the insulating layer, wherein the outer closure cap covers, in particular completely covers the through-via in top view. Here, preferably, a maximum lateral offset between the outer closure cap and the through-via in the insulating layer is smaller than a maximum lateral offset between the inner closure cap and the through-via in the base substrate. For example, the maximum lateral offset between the outer closure cap and the through-via can be smaller than the maximum lateral offset between the inner closure cap and the through-via in the base substrate by at least 10 μm, 25 μm, 50 μm or 100 μm.
Deviating from this, it is possible that the maximum lateral offset between the outer closure cap and the through-via in the insulating layer is larger than a maximum lateral offset between the inner closure cap and the through-via in the base substrate. In general, the outer closure cap may be simultaneously formed as a connection pad for receiving a component. For example, a contact point of the component may be attached, in particular soldered, to the connection pad.
The carrier may have a plurality of pairs of connection pads, each pair being configured for receiving, mechanically securing, and/or electrically contacting at least one component. The connection pads of each pair may be associated with different electrical polarities. Furthermore, a lateral distance between the connection pads of the same pair or of the different adjacent pairs may be smaller than a lateral structural width of the conductor tracks or of the closure caps of the same wiring layer, in particular on the mounting surface. For example, this lateral distance may be smaller than 200 μm, 160 μm, 100 μm, 50 μm, 30 μm or 20 μm.
According to at least one embodiment of the carrier, the outer wiring layer forms a freely accessible mounting surface, which is configured to receive and make electrical contact with one component or with several electrical components. The mounting surface is in particular planar. In this context, a planar mounting surface is understood to mean in particular a mounting surface which has no local depressions or elevations, or which has only local depressions or elevations smaller than 50 μm, 40 μm, 30 μm, 20 μm or smaller than 10 μm. In particular, the mounting surface is formed in places by a surface of the insulating layer and in places by a surface of the outer wiring layer.
The planar mounting surface may have small local depressions or elevations, whose vertical depth or height is given by the vertical layer thickness of the outer wiring layer or is smaller than the vertical layer thickness of the outer wiring layer, i.e. is smaller than the layer thickness of the conductor tracks, the connection pads and/or the closure caps of the outer wiring layer. Along the vertical direction, the insulating layer may protrude in places beyond the outer wiring layer, or vice versa.
The carrier has a rear side facing away from the mounting surface. The rear side of the carrier may be formed in places by a surface of the further insulating layer and in places by a surface of the further outer wiring layer. Analogous to the mounting surface, the rear side of the carrier may be planar.
According to at least one embodiment of the carrier, the outer wiring layer has a plurality of conductor tracks and connection pads arranged next to one another. In particular, the outer wiring layer forms the mounting surface of the carrier. Preferably, the connection pads are densely packed, wherein a lateral distance between adjacent connection pads is in particular not greater than a minimum structural width of the conductor tracks and/or closure caps. Preferably, the mounting surface is free of conductor tracks and/or closure caps which, in top view, are arranged at least regionally between adjacent connection pads, for example between two adjacent rows or columns of connection pads, while being laterally spaced from these connection pads. For example, some of the connection pads are not via the through-vias in the insulating layer but exclusively via the conductor tracks of the outer wiring layer externally electrically contactable. This means that these connection pads are wired externally, in particular via the conductor tracks, and can thus be electrically conductively connected to an external voltage source. Some further of the connection pads, in particular the remaining of the connection pads, are electrically conductively connected to the inner wiring layer, for example, by the through-vias in the insulating layer.
The further connection pads can be wired to the outside via the inner wiring layer, for example via conductor tracks of the inner wiring layer and/or via through-via/s in the base substrate and/or via further through-via/s in the further insulating layer. Wiring of a connection pad to the outside means that the connection pad can be electrically contacted externally. If a connection pad is wired to the outside, it can be connected to an external voltage source, for example. Thus, the external electrical contacting of the connection pads on the mounting surface takes place on at least two, three or four wiring layers.
According to at least one embodiment of the carrier, at least some or all of the adjacently arranged connection pads are arranged as pairs. The connection pads of the same pair can be assigned to different electrical polarities of the carrier. In particular, in each case, one connection pad of a pair cannot be electrically contacted externally via the through-via but exclusively via conductor track/s of the outer wiring layer. The other connection pad of each pair is preferably electrically conductively connected to the inner wiring layer by a through-via in the insulating layer. In particular, the pair of connection pads is set up for receiving, mechanically fastening and/or electrically contacting a component.
It is further possible that at least one of the connection pads is electrically conductively connected from the inner wiring layer to the further inner wiring layer via the through-via in the base substrate. Via the further through-via in the further insulating layer, this connection pad can be wired to the further outer wiring layer, in particular wired to the outside. It is also possible that one of the connection pads of the same pair is wired to the outside exclusively via a conductor track on the mounting surface, while the other connection pad of the same pair is not electrically conductively connected to any of the conductor tracks on the mounting surface, but is at least partially wired via the through-via/s in the insulating layer and/or in the base substrate and/or in the further insulating layer.
According to at least one embodiment of the carrier, it has a plurality of through-vias in the insulating layer. The outer wiring layer may have a plurality of conductor tracks, which are in particular arranged on the edge side of the mounting surface. For example, the outer wiring layer has a plurality of electrically conductor tracks and a plurality of pairs of adjacent connection pads. At least some of the connection pads may be electrically conductively connected to the electrical conductor tracks. It is possible that the other connection pads are each electrically conductively connected to one of the through-vias in the insulating layer. The connection pads that are electrically conductively connected to the through-vias in the insulating layer are not electrically conductively connected to the conductor tracks on the mounting surface, for example. These connection pads are electrically contacted in particular by the through-vias in the insulating layer with the underlying wiring layer and in particular are electrically contacted externally from there.
The electrical contacting of the connection pads arranged on the same mounting surface can thus take place on different wiring layers. The number of electrical conductor tracks and/or of closure caps on the mounting surface can thus be reduced, since the electrical contacting of some connection pads takes place via the through-vias located underneath. The mounting surface can thus have a higher number of closely packed connection pads, as a result of which a higher number of components can be arranged on the mounting surface. The components can thus be arranged particularly close together on the mounting surface. Since the electrical contacting of the connection pads or of the components takes place via different wiring layers, the risk of electrical short circuits on the mounting surface is reduced.
According to at least one embodiment of the substrate, the insulating layer and/or the further insulating layer is a layer of a potting compound, an oxide layer, a nitride layer, a polyimide layer, a solder resist layer or a photoresist layer. The base substrate may be a printed circuit board, a metal core board, a plastic body, or a ceramic body.
Further embodiments provide a method for producing a carrier, in particular, a carrier described herein. The features described in connection with the carrier can therefore also be used for the method, and vice versa.
According to at least one embodiment of the method, a carrier having a base substrate, an insulating layer, an inner wiring layer, an outer wiring layer and a through-via extending throughout the insulating layer is produced. Via the through-vias in the insulating layer, the inner wiring layer is electrically connected to the outer wiring layer. The through-via in the insulating layer has a lateral cross-section whose maximum lateral extent is preferably at most 100 μm.
According to at least one embodiment of the method, the process for forming the base substrate and the process for forming the insulating layer differ from each other. For example, the base substrate is provided as a printed circuit board, a ceramic body, a plastic body, or a metal core board. The process for forming the insulating layer may include steps of applying the insulating layer to the base substrate and structuring the insulating layer to form the through-vias. For example, the insulating layer is applied onto the base substrate by a coating process. The base substrate may be formed by a casting process or by laminating a plurality of electrically insulating and/or electrically conductive layers. It is possible that the base substrate is provided as a prefabricated printed circuit board.
The base substrate may have a preliminary mounting surface with connection pads, conductor tracks and/or closure caps. By applying the insulating layer or insulating layers, the preliminary mounting surface is covered. The final mounting surface of the carrier is formed only after the outer wiring layer is applied onto the insulating layer. The mounting surface of the carrier may differ from the preliminary mounting surface of the base substrate in terms of the number and/or in terms of the geometry and size of the conductor tracks, of the connection pads and/or of the closure caps.
According to at least one embodiment of the method, an electrically insulating material is applied onto the inner wiring layer to form the insulating layer. An opening is formed in the insulating layer to partially expose the inner wiring layer, whereupon the opening is filled with an electrically conductive material for forming the through-via. A mechanical process, a chemical process, such as an etching process, or a laser drilling process may be used to form the opening or a plurality of openings. If the insulating layer is formed of a photostructurable material, such as a photoresist, the openings in the insulating layer may be formed by exposure to light, in particular using a mask.
According to at least one embodiment of the method, an electrically conductive material for forming the through-vias is applied in places to the inner wiring layer prior to forming the insulating layer. An electrically insulating material can be applied to the inner wiring layer to form the insulating layer, so that the insulating layer covers, in particular completely covers the through-via in top view. To expose the through-vias, the material of the insulating layer can be partially removed.
In this variant of embodiment, the through-via or the plurality of through-vias is/are applied to the wiring layer before the insulating layer is applied. In this case, the through-via is formed as a local elevation on the wiring layer before the insulating layer is applied to the wiring layer. Since the through-via or the through-vias is/are formed before the insulating layer, there is no need to form openings in the insulating layer and then fill them. In this case, the through-vias can each have a particularly small cross-section or diameter, since the difficulties of filling particularly small openings do not arise in this case.
In this case, the through-via or the through-vias may be formed in a drop-shape or hemispherical shape on the corresponding wiring layer. Such through-vias may each have a cross-section that tapers with increasing distance from the base substrate or from the corresponding wiring layer.
Further embodiments and further developments of the carrier or of the method for producing the carrier will be apparent from the embodiments explained below in connection with
Identical, equivalent or equivalently acting elements are indicated with the same reference numerals in the figures. The figures are schematic illustrations and thus not necessarily true to scale. Comparatively small elements and particularly layer thicknesses can rather be illustrated exaggeratedly large for the purpose of better clarification.
In particular, the wiring layer 2V is formed by a structured covering layer 1Z of the base substrate 1. The structured covering layer 1Z may have a plurality of interconnected sub-regions or laterally spaced sub-regions, for example, in the form of conductor tracks 2W or connection pads 2P or other structures on the mounting surface 10M.
The front-side wiring layer 2V can be formed from a structured cover layer 1Z of the base substrate 1, which has a plurality of sub-regions, which are formed, for example, as conductor tracks 2W, connection pads 2P or as closure caps 2C (cf.
The front-side wiring layer 2V is electrically conductively connected to the rear-side wiring layer 3R via a through-via 11 or via a plurality of through-vias 11. The closure caps 2C or 3C within the wiring layers 2V or 3R represent the end points of the through-vias 11.
Via the through-vias 21 and 31, the outer wiring layers 2V and 3R can be electrically conductively connected to the inner wiring layers 1V and 1R. The two inner wiring layers 1V and 1R may be electrically conductively connected to each other via the through-via/s 11.
In the carriers 10 shown in
The carriers 10 shown in
The through-vias 11, 21 and 23 each have a lateral diameter 11D, 21D and 31D, respectively. In conventional methods using conventional materials of the base substrate, the through-vias 11, 21 and 31 generally have a diameter of at least 125 μm or 150 μm. The closure caps 1C, 2C or 3C should be of such a size that, in top view, they reliably completely cover the respective associated through-vias 11, 21 or 31, even taking into account process-related offset tolerances. The size of the through-vias 11, 21 or 31 thus plays an important role in the design of the carrier 10, in particular of the mounting surface 10M of the carrier 10.
In
Referring to
The conductor tracks 2W have a minimum structural width (usually this is the conductor track width), which is given either by the producing process of the wiring layer 2V or by the application, for example, with respect to the required current carrying capacity.
The closure caps 2C have a minimum structure width (usually this is the cap diameter), which is given by the producing processes of the wiring layer 2V and of the through-vias 11 or 21.
There is a minimum distance between the connection pads 2P and/or the conductor tracks 2W and/or the closure caps 2C which is given either by the producing process of the wiring layer 2V or by the application, for example, in terms of the required dielectric strength.
Due to the presence of conductor tracks 2W and/or of closure caps 2C, as well as the minimum structure widths and minimum distances to be maintained, the design freedom of the connection pads 2P within the mounting surface 10M is limited, in particular with respect to their sizes and positions.
The designs of the wiring layer 2V, illustrated in
If a dense regular arrangement of components on the mounting surface 10M is desired, the mounting surface 10M will usually have a regular arrangement of densely packed connection pads 2P, each having different electrical potentials. This may result in insufficient remaining free space on the mounting surface 10M for the required conductor tracks 2W or for the closure caps 2C to connect or to wire each of the connection pads 2P in an electrically suitable manner.
An arrangement of closely packed small components such as closely packed light emitting diode flip chips on the carrier 10 according to
In the following, various exemplary embodiments of a carrier 10 are illustrated wherein the closure caps 2C can be reduced in size or the number of conductor tracks 2W and/or closure caps 2C on the mounting surface 10M can be reduced.
The exemplary embodiment for a carrier 10 shown in
Compared with conventional carriers (see for example
The mounting surface 10M is in particular planar and has a roughness of at most 50 μm, 40 μm, 30 μm, 20 μm or of at most 10 μm. In particular, the roughness of the mounting surface 10M is given by local depressions or local elevations, which are caused, for example, by the layer thickness of the conductor tracks 2W, the connection pads 2P and/or of the closure cap 2C. The conductor tracks 2W, the closure caps 2C and/or the connection pads 2P can have a vertical layer thickness of at most 50 μm, 40 μm, 30 μm, 20 μm or at most 10 μm.
The exemplary embodiment shown in
The exemplary embodiment shown in
According to the carriers 10 shown in
The exemplary embodiment shown in
The base through-via 11 has a lateral diameter 11D. In case of doubt, the diameter 11D is a maximum lateral extent of the cross-section of the base through-via 11. In particular, the diameter 11D is greater than 100 μm, particularly greater than 150 μm. It is possible that the diameter 11D of the base through-via 11 is at least 50%, 75%, 100% or 200% larger than the diameter 21D of the through-via 21. In top view, the base through-via 11 and the through-via 21 may overlap, partially overlap, or be arranged side by side.
The exemplary embodiment shown in
In
In top view, the closure cap 1C completely covers the associated base through-via 11. In ideal coverage, the closure cap 1C and the associated base through-via 11 may have the same cross-section or diameter. In practice, however, the diameter 1CD of the closure cap 1C is chosen to be the sum of the diameter 11D of the base through-via 11 and the producing tolerances. In general, the required diameter of the closure cap is preferably at least as large as the sum of the diameter of the through-via and twice the producing tolerances. For example, the diameter 1CD is at least 110 μm, 130 μm, 160 μm, 210 μm or 250 μm.
In
The example illustrated in
Because the through-vias 21 in the insulating layer 2 can have a smaller cross-section compared to the base through-vias 11 in the base substrate 1, it is possible that the minimum required diameter 2CD of the closure cap 2C is correspondingly smaller than the diameter 1CD of the closure cap 1C for the same maximum offset, and that the required area of the closure cap 2C is correspondingly smaller in square than the area of the closure cap 1C.
For some producing processes, the maximum occurring offset correlates with the size of the through-via and/or of the closure cap, so that a smaller closure cap 2C can be placed on a through-via 21 with a smaller offset V. This in turn further reduces the minimum required diameter 2CD of the closure cap 2C.
For example, for a base through-via 11 having a diameter 11D of 125 μm and extending throughout the base substrate 1, the offset V may be 50 μm, so that the minimum required diameter 1CD of the closure cap 1C is 225 μm, while for a through-via 21 having a diameter 21D of 30 μm and extending throughout an insulating layer 2, the offset V may be 25 μm, so that the minimum required diameter 2CD of the closure cap 2C is only 80 μm. The minimum required area of the closure cap 2C would be 5027 μm2, compared to 39761 μm2 for the closure cap 1C.
The exemplary embodiment shown in
According to
The exemplary embodiment shown in
The exemplary embodiment shown in
Starting from a carrier shown in
The mounting surface 10M has an arrangement of 8×4 connection pads 2P suitable for mounting 4×4 closely packed small bipolar components P. These may be, for example, light emitting diode flip chips.
Since the through-vias 21 within the insulating layer 2 have a smaller diameter 21D than the base through-vias 11 having diameter 11D, the smallest possible diameters of the closure caps 2C can be significantly smaller than the smallest possible diameters of the closure caps 1C.
Analogous to the explanation of
Thus, all 8×4 connection pads 2P can be electrically wired inside the carrier 10. For example, the external 20 connection pads can be electrically wired per conductor tracks 2W in the wiring layer 2V as illustrated. The inner 12 connection pads 2P can, for example, as illustrated, first be electrically wired via the through-vias 21 to the wiring layer 1V and then from there with conductor tracks 1W (see
In this way, the example illustrated in
Starting from the outer upper wiring layer 2V, all possible connection pads 2P are wired in each case per conductor tracks 2W within this wiring layer. These are usually the connection pads on the outside in the field. The potentials of the other, in particular of all other connection pads are routed to the next lower wiring layer via the through-vias 21. These are usually the inner connection pads.
There, the process is then successive in each case. This means that the potentials, usually the external potentials, are wired by conductor tracks in this wiring layer. The wiring of all other potentials, usually the inner potentials, is realized by through-vias in a lower wiring layer. This is realized by a sufficient number of wiring layers until sufficiently few potentials remain in wiring layer 1V to be wired there by conductor tracks 1W or by the through-vias 11 in base substrate 1.
Analogous to the explanation of
Thus, all 16×9 connection pads 2P can be electrically wired within the carrier 10. The 72 connection pads with the same potential and 18 connection pads with individual potential are wired by conductor tracks 2W in the wiring layer 2V, as illustrated in
The application illustrated in
Referring to
Those connection pads 2P which are not electrically connected or electrically wired via the conductor tracks 2W on the wiring layer 2V or on the mounting surface 10M, respectively, can be electrically wired via the through-vias 21 to the conductor tracks in a lower-lying wiring layer, in particular in the inner wiring layer 1V.
Analogously to the outer wiring layer 2V, the connection pads 2P of the same row, which are not already electrically wired via the conductor tracks 2W on the mounting surface 10M, are electrically conductively connected to each other via the conductor tracks 1W in the inner wiring layer 1V according to
In all of the exemplary embodiments for a carrier 10 described so far, the conductor tracks 1W, 2W, 3W, the closure caps 1C, 2C, 3C, the connection pads 2P and/or 3P may be formed of a metal such as copper, nickel or aluminum. The cover layer 1Z of the base substrate 1 may also be formed of such a material. The insulating layers 2 and 3 may each be formed from a solder resist, a photoresist, a potting compound, silicon oxide or from silicon nitride. The maximum possible offset between the through-via 21 or 31 and the associated closure cap 2C or 3C is preferably less than 100 μm, 50 μm, for instance less than 30 μm, in particular less than 25 μm or less than 20 μm.
It is possible that further layers are used at the joining locations between two electrically conductive layers to improve electrical contact, to improve thermal contact, to improve mechanical strength or to suppress diffusion. Such further layers may be formed of titanium, platinum, palladium, tungsten nitride or alloys of these layers.
The connection pads 2P or 3P, which are configured for electrical contacting the component, and/or the contact points of the component can be formed from titanium, platinum, palladium, tungsten nitride, gold, tin, silver, copper or from aluminum or alloys thereof. If the insulating layer 2 or 3 has openings 20 or 30, wherein the contact connection pads 2P or 3P are accessible at least in places, the insulating layer 2 or 3 can project beyond the contact connection pad 2P or 3P along the vertical direction. The opening 20 or 30 may serve as a collecting basin for excess solder material.
According to
Referring to
Referring to
According to
According to
According to
Analogously to the through-vias 21 and to the outer wiring layer 2V on the front side 1F of the base substrate 1, a plurality of further through-vias 31 and an outer wiring layer 3R comprising a plurality of possible connection pads 3P, conductor tracks 3W and a plurality of possible closure caps 3C are formed on the rear side 1B of the base substrate 1. The exemplary embodiment shown in
According to
The exemplary embodiment illustrated in
According to
The exemplary embodiment shown in
According to
According to
According to
Using the method illustrated in
The invention is not restricted to the exemplary embodiments by the description of the invention made with reference to the exemplary embodiments. The invention rather comprises any novel feature and any combination of features, including in particular any combination of features in the claims, even if this feature or this combination is not itself explicitly indicated in the patent claims or exemplary embodiments.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10 2019 108 870.4 | Apr 2019 | DE | national |
This patent application is a national phase filing under section 371 of PCT/EP2020/057673, filed Mar. 19, 2020, which claims the priority of German patent application 102019108870.4, filed Apr. 4, 2019, each of which is incorporated herein by reference in its entirety.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/EP2020/057673 | 3/19/2020 | WO | 00 |
