Patent Application
20240120153
This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2022-161773, filed on Oct. 6, 2022, the entire contents of which are incorporated herein by reference.
A certain aspect of the present disclosure relates to a ceramic electronic device and a manufacturing method of the ceramic electronic device.
In high-frequency communication systems typified by mobile phones, there is a demand for small-sized, large-capacity multilayer ceramic capacitors to add further functionality. To reduce the size and increase the capacity, it is effective to reduce the thickness of the dielectric layers and internal electrode layers and increase the number of layers. However, when the dielectric layer is made thinner, the electric field intensity is lowered when the capacitor is used, which is disadvantageous in terms of insulation reliability. Therefore, as a measure to ensure insulation reliability in thin dielectric layers, there is disclosed a method of adding an additive metal element to the dielectric layer and the internal electrode layer, and forming a thin layer of the additive metal element between the internal electrode layer and the dielectric layer (see, for example, Japanese Patent Application Publication No. 2003-7562).
According to an aspect of the embodiments, there is provided a ceramic electronic device including: a multilayer chip in which each of a plurality of dielectric layers including ceramic as a main component and each of a plurality of internal electrode layers including a first metal as a main component are alternately stacked, and each of the plurality of internal electrode layers is exposed alternately to a plurality of portions of the multilayer chip; and external electrodes, each of which is provided on each of the plurality of portions of the multilayer chip, wherein a dielectric pattern is provided in end margins where internal electrode layers connected to one of the external electrodes face each other with no internal electrode layer connected to the other of the external electrodes interposed therebetween, wherein the plurality of internal electrode layers include one or more type of a second metal which is different from the first metal, and wherein a concentration of the second metal in the plurality of dielectric layers is higher than a concentration of the second metal of the dielectric pattern.
According to another aspect of the embodiments, there is provided a ceramic electronic device including: a multilayer chip in which each of a plurality of dielectric layers including ceramic as a main component and each of a plurality of internal electrode layers including a first metal as a main component are alternately stacked, and each of the plurality of internal electrode layers is exposed alternately to a plurality of portions of the multilayer chip; and external electrodes, each of which is provided on each of the plurality of portions of the multilayer chip, wherein the plurality of internal electrode layers include one or more type of a second metal which is different from the first metal, wherein a concentration of the second metal in the plurality of internal electrode layers is higher in a capacity section where two adjacent internal electrode layers connected to different external electrodes face each other than in end margins where internal electrode layers connected to one of the external electrodes face each other with no internal electrode layer connected to the other of the external electrodes interposed therebetween.
According to another aspect of the embodiments, there is provided a ceramic electronic device including: a multilayer chip in which each of a plurality of dielectric layers including ceramic as a main component and each of a plurality of internal electrode layers including a first metal as a main component are alternately stacked, and each of the plurality of internal electrode layers is exposed alternately to a plurality of portions of the multilayer chip; and external electrodes, each of which is provided on each of the plurality of portions of the multilayer chip, wherein a dielectric pattern is provided in end margins where internal electrode layers connected to one of the external electrodes face each other with no internal electrode layer connected to the other of the external electrodes interposed therebetween, wherein the plurality of internal electrode layers include one or more type of a second metal which is different from the first metal, and wherein a difference between electronegativity of the second metal of the plurality of dielectric layers and electronegativity of the second metal of the dielectric pattern is within ±0.4.
According to another aspect of the embodiments, there is provided a manufacturing method of a ceramic electronic device including: preparing a multilayer structure in which a plurality of stack units are stacked, each of the stack units having a structure in which an internal electrode pattern including powder of a first metal as a main component and powder of a second metal and a dielectric pattern including ceramic powder arranged around the internal electrode pattern are formed on a dielectric green sheet including ceramic powder; and firing the multilayer structure, wherein a concentration of the second metal in the dielectric green sheet is higher than a concentration of the second metal in the dielectric pattern, in the multilayer structure before the firing.
By adding an additive metal element to the internal electrode layer, an electrical barrier is formed between the internal electrode layer and the dielectric layer, ensuring insulation reliability. However, if the additive metal element is present in the extraction portions of the internal electrode layers, the bondability between the internal electrode layers and the external electrodes may deteriorate, and sufficient electrical characteristics may not be obtained.
Hereinafter, an exemplary embodiment will be described with reference to the accompanying drawings.
(Embodiment)
In
The multilayer chip 10 has a structure designed to have dielectric layers 11 and internal electrode layers 12 alternately stacked. The dielectric layer 11 contains a ceramic material acting as a dielectric material. The internal electrode layer 12 contains a base metal. End edges of the internal electrode layers 12 are alternately exposed to a first end face of the multilayer chip 10 and a second end face of the multilayer chip 10 that is different from the first end face. The external electrode 20a is provided on the first end face. The external electrode 20b is provided on the second end face. Thus, the internal electrode layers 12 are alternately electrically connected to the external electrode 20a and the external electrode 20b. Accordingly, the multilayer ceramic capacitor 100 has a structure in which a plurality of the dielectric layers 11 are stacked with the internal electrode layers 12 interposed therebetween. In the multilayer structure of the dielectric layers 11 and the internal electrode layers 12, the outermost layers in the stack direction are the internal electrode layers 12, and cover layers 13 cover the top face and the bottom face of the multilayer structure. The cover layer 13 is mainly composed of a ceramic material. For example, the main component of the cover layer 13 is the same as the main component of the dielectric layer 11.
For example, the multilayer ceramic capacitor 100 may have a length of 0.25 mm, a width of 0.125 mm, and a height of 0.125 mm. The multilayer ceramic capacitor 100 may have a length of 0.4 mm, a width of 0.2 mm, and a height of 0.2 mm. The multilayer ceramic capacitor 100 may have a length of 0.6 mm, a width of 0.3 mm, and a height of 0.3 mm. The multilayer ceramic capacitor 100 may have a length of 0.6 mm, a width of 0.3 mm, and a height of 0.110 mm. The multilayer ceramic capacitor 100 may have a length of 1.0 mm, a width of 0.5 mm, and a height of 0.5 mm. The multilayer ceramic capacitor 100 may have a length of 1.0 mm, a width of 0.5 mm, and a height of 0.1 mm. The multilayer ceramic capacitor 100 may have a length of 3.2 mm, a width of 1.6 mm, and a height of 1.6 mm. The multilayer ceramic capacitor 100 may have a length of 4.5 mm, a width of 3.2 mm, and a height of 2.5 mm. However, the size of the multilayer ceramic capacitor 100 is not limited to the above sizes.
A main component of the dielectric layer 11 is a ceramic material having a perovskite structure expressed by a general formula ABO3. The perovskite structure includes ABO3-α having an off-stoichiometric composition. For example, the ceramic material is such as BaTiO3 (barium titanate), CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), MgTiO3 (magnesium titanate), Ba1-x-yCaxSryTi1-zZrzO3 (0≤x≤1, 0≤y≤1, 0≤z≤1) having a perovskite structure. Ba1-x-yCaxSryTi1-zZrzO3 may be barium strontium titanate, barium calcium titanate, barium zirconate, barium titanate zirconate, calcium titanate zirconate, barium calcium titanate zirconate or the like.
Additives may be added to the dielectric layer 11. As additives to the dielectric layer 11, molybdenum (Mo), niobium (Nb), tantalum (Ta), tungsten (W), magnesium (Mg), manganese (Mn), vanadium (V), chromium (Cr), rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm) and ytterbium (Yb)) or an oxide of cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K) or silicon (Si), or a glass including cobalt, nickel, lithium, boron, sodium, potassium or silicon.
The main component (first metal) of the internal electrode layer 12 is not particularly limited, but is a base metal such as Ni, Cu (copper), Sn (tin). As a main component of the internal electrode layers 12, noble metals such as Pt (platinum), Pd (palladium), Ag (silver), Au (gold), and alloys containing these may be used.
The internal electrode layer 12 contains an additive metal element (second metal) in addition to the main component metal. Although the additive metal element is not particularly limited, it is preferably a metal that is nobler than the main component metal of the internal electrode layers 12. The additive metal element is, for example, one or more selected from Au, Sn, Cr, Fe (iron), Y, In (indium), As (arsenic), Co, Cu, Ir (iridium), Mg, Os (osmium), Pd, Pt, Re (rhenium), Rh (rhodium), Ru (ruthenium), Se (selenium), Te (tellurium), W, and Zn (zinc).
As illustrated in
The section where the internal electrode layers 12 connected to the external electrode 20a face each other with no internal electrode layer 12 connected to the external electrode 20b interposed therebetween is referred to as an end margin 15. The section where the internal electrode layers 12 connected to the external electrode 20b face each other with no internal electrode layer 12 connected to the external electrode 20a interposed therebetween is also the end margin 15. That is, the end margin 15 is a section where the internal electrode layers 12 connected to one of the external electrodes face each other with no internal electrode layer 12 connected to the other of the external electrodes interposed therebetween.
As illustrated in
In order to increase the size and capacity of such multilayer ceramic capacitors, there is a demand for thinner dielectric layers, thinner internal electrode layers, and higher stacking. However, thinning the dielectric layer is accompanied by an increase in electric field strength, making it more difficult to ensure long lifetime. In addition to the study of dielectric material design, such as solid-solving small amount of additives such as rare earth oxides in dielectric materials such as barium titanate, in recent years, dissimilar metal elements have been added to internal electrode layers as additive metal elements. And, a study by designing the interface between the dielectric layer and the internal electrode layer has been reported. It is thought that by forming a segregation layer containing an additive metal element at the interface between the dielectric layer and the internal electrode layer, the electrical barrier is strengthened and the lifetime is improved.
In the internal electrode layers 12, it is preferable that a large amount of the additive metal element exists near the interface between the dielectric layers 11 and the internal electrode layers 12.
The segregation layer 122 is a layer in which the additive metal element segregates. In addition, in each of the main component metal layer 121 and the segregation layer 122, not only a single metal exists, but each metal partially diffuses into each layer. The main component metal layer 121 contains, for example, 98 at % or more of the main component metal. The main component metal layer 121 may contain the additional metal element contained in the segregation layer 122. The segregation layer 122 may contain the main component metal of the main component metal layer 121.
For example, by performing line analysis in the stacking direction, it is possible to confirm that the segregation layer 122 is formed in the internal electrode layer 12. For example, in a TEM (transmission electron microscope) analysis of a cross section along the stacking direction, line analysis of each component element concentration for each sample point along the stacking direction of the dielectric layer 11 and the internal electrode layer 12 is performed. If it can be confirmed that a peak appears in the concentration of the additive metal element between the interface of the main component metal layer 121 and the interface of the dielectric layer 11, it can be confirmed that the segregation layer 122 is formed. In order to reduce noise, measurement results may be smoothed by averaging at about nine points during line analysis.
For example, the thickness of the segregation layer 122 is 0.5 nm or more and 2.8 nm or less, 0.5 nm or more and 2.0 nm or less, or 0.5 nm or more and 1.3 nm or less. The thickness of the segregation layer 122 is defined by the half width of the concentration peak of the additive metal element obtained by the line analysis.
Since the internal electrode layer 12 has the segregation layer 122 at the interface with the dielectric layer 11 in this manner, the electrical barrier between the internal electrode layer 12 and the dielectric layer 11 is strengthened, and the lifetime of the multilayer ceramic capacitor 100 is extended.
However, the presence of the additive metal element in the internal electrode layer at the end margin causes a difference in thermal conductivity, and the temperature at which the internal electrode layer and the external electrode undergo sintering shrinkage differs. There is a possibility that the bondability between the internal electrode layer and the external electrode deteriorates due to the formation of a gap between the internal electrode layer and the external electrode, and sufficient electrical characteristics cannot be obtained.
Therefore, the multilayer ceramic capacitor 100 according to the present embodiment has a configuration capable of improving the bondability between the internal electrode layers 12 and the external electrodes 20a and 20b.
First, in the internal electrode layer 12, as illustrated in
The method of measuring the concentration of the additive metal element is not particularly limited, but the following methods can be mentioned, for example. Specifically, the multilayer ceramic capacitor 100 is polished from the side margin 16 side to expose the XZ cross section at the center in the Y-axis direction. In the internal electrode layer 12 in this XZ cross section, SEM (scanning electron microscope), TEM (transmission electron microscope), EDS (energy dispersive X-ray analysis) using STEM (scanning transmission electron microscope), EPMA (electron probe micro analyzer)), LA-ICP-MS (Laser Ablation Inductively Coupled Plasma Mass Spectrometry) or the like is used to measure the number of atoms of the main component metal and the number of atoms of the additive metal element in the internal electrode layer 12. Thus, the concentration of the additive metal element can be measured.
If the concentration of the additive metal element is low in the entire internal electrode layer 12, the segregation layer 122 of the additive metal element may not be sufficiently formed in the first section 31. Therefore, it is preferable to set a lower limit for the concentration of the additive metal element in the entire internal electrode layer 12. In the present embodiment, the concentration of the additive metal element in the entire internal electrode layer 12 is preferably 0.01 at % or more, more preferably 0.05 at % or more, and 0.1 at % or more.
On the other hand, if the concentration of the additive metal element is high in the entire internal electrode layer 12, the effect of improving the bondability due to the difference in concentration between the first section 31 and the second section 32 will not work sufficiently, poor contact between the internal electrode layer and the external electrode may occur. Therefore, it is preferable to set an upper limit for the concentration of the additive metal element in the entire internal electrode layer 12. In this embodiment, the concentration of the additive metal element in the entire internal electrode layer 12 is preferably 5 at % or less, more preferably 3 at % or less, and even more preferably 1 at % or less.
From the viewpoint of sufficiently increasing the concentration of the additive metal element in the first section 31 and sufficiently decreasing the concentration of the additive metal element in the second section 32, it is preferable to set a lower limit to the concentration ratio. In the present embodiment, it is preferable to set a lower limit to the ratio of the concentration of the additive metal element in the first section 31 and the concentration of the additive metal element in the second section 32. Specifically, first, attention is paid to the specific internal electrode layer 12 in the XZ cross section at the center in the Y-axis direction. As illustrated in
The thickness of the dielectric layer 11 per layer is, for example, 0.3 μm or more and 10 μm or less, or 0.4 μm or more and 8 μm or less, or 0.5 μm or more and 5 μm or less, more preferably 0.3 μm or more and 3 μm or less. In general, the thinner the dielectric layer 11 is, the more likely it is to be affected by the diffusion of the additive metal element added to the internal electrode layer 12 and the local oxidation of the internal electrode layer 12, so that the electrical characteristics are likely to fluctuate. Also in the present embodiment, as the dielectric layer 11 is made thinner, it is expected that a greater effect will be exhibited. The thickness of the dielectric layer 11 per layer is obtained by exposing the cross section of the multilayer ceramic capacitor 100, for example, as illustrated in
The thickness of the internal electrode layer 12 per layer is, for example, 0.1 μm or more and 2 μm or less, or 0.2 μm or more and 1 μm or less, or 0.3 μm or more and 0.8 μm or less. As the internal electrode layer 12 becomes thinner, local oxidation is more likely to occur due to an increase in the surface ratio. In this embodiment, it is expected that a greater action and effect will be exhibited. However, when the thickness of the internal electrode layer 12 is less than 0.05 μm, the thickness ratio of the segregation layer 122 becomes too high with respect to the thickness of the internal electrode layer 12. In this case, there is a possibility that influences of an increase in ESR (equivalent series resistance), oxidizing of the internal electrode layer, sinterability of the internal electrode layer cannot be ignored. The thickness of the internal electrode layer 12 per layer is measured by exposing the cross section of
The additive metal element may be of one type, or may be of two or more types. For example, the additive metal element may include at least two types of the first additive metal element and the second additive metal element. When there are two or more additive metal elements, the concentration of the additive metal elements in the internal electrode layer 12 is the total concentration of the two or more additive metal elements.
Next, the concentration of the additive metal element forming the segregation layer 122 of the internal electrode layer 12 in the dielectric layer 11 and the dielectric pattern layer 17 will be described. In this embodiment, the dielectric layer 11 and the dielectric pattern layer 17 also contain the additive metal element. The concentration of the additive metal element in the dielectric layer 11 is higher than the concentration of the additive metal element in the dielectric pattern layer 17. Therefore, the concentration of the additive metal element in the dielectric portion of the capacity section 14 is higher than the concentration of the additive metal element in the dielectric portion of the end margin 15.
According to this configuration, the diffusion of the additive metal element from the internal electrode layer 12 to the dielectric pattern layer 17 is faster than the diffusion of the additive metal element from the internal electrode layer 12 to the dielectric layer 11 in the firing process. This is because the concentration of the additive metal element is set lower in the dielectric pattern layer 17 than in the dielectric layer 11, so that the additive metal element in the internal electrode layer 12 in the capacity section 14 with high concentration of the additive metal element easily diffuses into the dielectric pattern layer 17 with low concentration of the additive metal element. As a result, the diffusion amount of the additive metal element into the dielectric layer 11 can be suppressed, and deterioration of characteristics can be prevented. As a result, the bondability between the internal electrode layers 12 and the external electrodes 20a and 20b is improved. The concentration of the additive metal element in the dielectric layer 11 and the dielectric pattern layer 17 can be defined as at % of the additive metal element when the B site element of the main component ceramic is 100 at %.
If the concentration of the additive metal element in the dielectric layer 11 of the capacity section 14 is low, the diffusion of the additive metal element from the internal electrode layer 12 to the dielectric layer 11 may be promoted. Therefore, it is preferable to set a lower limit for the concentration of the additive metal element in the dielectric layer 11 of the capacity section 14. In the present embodiment, the concentration of the additive metal element in the dielectric layer 11 of the capacity section 14 is preferably 0.01 at % or higher, more preferably 0.2 at % or higher, and even more preferably 0.5 at % or higher.
On the other hand, if the concentration of the additive metal element in the dielectric layer 11 of the capacity section 14 is high, the additive element dissolves in BaTiO3, which is the main ingredient, and may greatly change the dielectric properties. Therefore, it is preferable to set an upper limit for the concentration of the additive metal element in the dielectric layer 11 of the capacity section 14. In the present embodiment, the concentration of the additive metal element in the dielectric layer 11 of the capacity section 14 is preferably 1 at % or less, more preferably 0.7 at % or less, and even more preferably 0.5 at % or less.
When the dielectric layer 11 and the dielectric pattern layer 17 contain the additive metal element, it is preferable that the dielectric layer 11 and the dielectric pattern layer 17 contain the same kind of additive metal element as the additive metal element of the internal electrode layers 12. For example, when the internal electrode layers 12 contain Au as the additive metal element, it is preferable that the dielectric layers 11 and the dielectric pattern layers 17 also contain Au as the additive metal element. Moreover, when the internal electrode layers 12 contain Au and Sn as additive metal elements, the dielectric layers 11 and the dielectric pattern layers 17 preferably also contain Au and Sn as additive metal elements.
The additive metal element contained in the dielectric pattern layer 17 may be different from the additive metal element contained in the dielectric layer 11. In this case, the segregation layer 122 of the additive metal element contained in the dielectric pattern layer 17 is formed in the end margin 15, and the segregation layer 122 of the additive metal element contained in the dielectric layer 11 is formed in the capacity section 14. For example, it is preferable that the difference in electronegativity between the additive metal element contained in the dielectric layer 11 of the capacity section 14 and the additive metal element contained in the dielectric pattern layer 17 of the end margin 15 is within ±0.4, so that the two additive metal elements are easily alloyed. For example, the following combinations are preferable because the difference in electronegativity is 0.4 or less. Preferably, Sn—Cu is 0.06, Sn—Zn is 0.31, Fe—Al is 0.22, and Fe—Cr is 0.17. For example, the dielectric layer 11 of the capacity section 14 may contain Sn as the additive metal element, and the dielectric pattern layer 17 of the end margin 15 may contain Cu as the additive metal element. By using two types of additive metal elements that are easily alloyed, the two types of additive metal elements can be easily diffused.
The cover layer 13 preferably contains 1 at % or more and 2 at % or less of the main component metal of the internal electrode layers 12. For example, if the main component metal of the internal electrode layers 12 is Ni, the cover layer 13 preferably contains 1 at % or more and 2 at % or less of Ni. In this case, since the cover layer 13 is densified, the occurrence of cracks and chipping can be suppressed. Moreover, the side margins 16 preferably contain 1 at % or more and 2 at % or less of the main component metal of the internal electrode layers 12. For example, if the main component metal of the internal electrode layers 12 is Ni, the side margins 16 preferably contain 1 at % or more and 2 at % or less of Ni.
Next, a description will be given of a manufacturing method of the multilayer ceramic capacitors 100.
(Making process of raw material powder) An A site element and a B site element are included in the dielectric layer 11 in a sintered phase of grains of ABO3. For example, BaTiO3 is tetragonal compound having a perovskite structure and has a high dielectric constant. Generally, BaTiO3 is obtained by reacting a titanium material such as titanium dioxide with a barium material such as barium carbonate and synthesizing barium titanate. Various methods can be used as a synthesizing method of the ceramic structuring the dielectric layer 11. For example, a solid-phase method, a sol-gel method, a hydrothermal method or the like can be used. The embodiments may use any of these methods.
A predetermined additive compound is added to the obtained dielectric powder according to the purpose. The additive compounds include oxides of Mo, Nb, Ta, W, Mg, Mn, V, Cr, rare earth elements (Y, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm and Yb), or oxides containing Co, Ni, Li, B, Na, K or Si, or glasses containing Co, Ni, Li, B, Na, K or Si. Among these, SiO2 mainly functions as a sintering aid.
Also, the additive metal element of the internal electrode layer 12 is added to the dielectric powder. A dielectric material is obtained by the above processes.
(Making process of dielectric pattern material) Dielectric powder is made by the same process as the making process of the dielectric material. Next, an additive metal element for the internal electrode layers 12 is added to the dielectric powder. A dielectric pattern material is obtained by the above process. However, the concentration of the additive metal element in the dielectric pattern material is made lower than the concentration of the additive metal element in the dielectric material.
(Stacking process) Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained dielectric material and wet-mixed. Using the obtained slurry, a dielectric green sheet 51 is formed on the substrate by, for example, a die coater method or a doctor blade method, and dried. The substrate is, for example, polyethylene terephthalate (PET) film.
Next, as illustrated in
Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol and toluene, and a plasticizer are added to the dielectric pattern material are wet-mixed. As illustrated in
Thereafter, as illustrated in
Next, as illustrated in
(Firing process) The binder is removed from the resulting ceramic multilayer structure in N2 atmosphere. After that, a metal paste to be the base layer of the external electrodes 20a and 20b is applied to the resulting ceramic multilayer by a dipping or the like. The resulting ceramic multilayer structure is fired in a reducing atmosphere with an oxygen partial pressure of 10-5 to 10-8 atm in a temperature of 1100° C. to 1300° C. for 10 minutes to 2 hours. Thus, the multilayer ceramic capacitor 100 is formed.
(Re-oxidation process) After that, the multilayer ceramic capacitor 100 may be subjected to a re-oxidation process in a temperature range of 600 degrees C. to 1000 degrees C. in N2 gas atmosphere.
(Plating process) After that, metal layers such as Cu, Ni, and Sn may be formed on the external electrodes 20a and 20b by plating.
According to the manufacturing method according to the present embodiment, since the concentration of the additive metal element in the dielectric green sheet 51 is higher than the concentration of the additive metal element in the dielectric pattern 53, in the capacity section 14, the diffusion of the additive metal element from the internal electrode layer 12 to the dielectric layers 11 is suppressed. As a result, the concentration of the additive metal element is lower in the second section 32 than in the first section 31 of
The dielectric green sheet 51 and the dielectric pattern 53 preferably contain the same kind of additive metal element as the additive metal element of the internal electrode layers 12. The additive metal element contained in the dielectric pattern 53 may be different from the additive metal element contained in the dielectric green sheet 51. In this case, the segregation layer 122 of the additive metal element contained in the dielectric pattern layer 17 is formed in the end margin 15, and the segregation layer 122 of the additive metal element contained in the dielectric layer 11 is formed in the capacity section 14.
In the embodiments, the multilayer ceramic capacitor is described as an example of ceramic electronic devices. However, the embodiments are not limited to the multilayer ceramic capacitor. For example, the embodiments may be applied to another electronic device such as varistor or thermistor.
Next, the multilayer ceramic capacitors in accordance with the embodiment were made. And the characteristics of the multilayer ceramic capacitors were measured.
(Example 1) In Example 1, Au was used as the additive metal element. The concentration of the additive metal element in the dielectric green sheet was 1 at %, and on the dielectric green sheet, a Ni paste containing 1 at % of the additive metal element was printed as an internal electrode pattern, and the dielectric pattern containing 0.5 at % or more of the additive metal element was printed around the Ni paste. Thus, a stack unit was obtained. Barium titanate was used as the main component ceramic of the dielectric green sheet and the dielectric pattern. A plurality of stack units thus obtained were stacked and cut to obtain a compact. The number of stack units was 500 layers. Ni paste was applied to the two end faces of the compact obtained, and the compact was fired. The obtained multilayer ceramic capacitor had a shape of 1005 (length 1.0 mm, width 0.5 mm, height 0.5 mm). The thickness of the dielectric layer was 0.6 μm.
(Example 2) In Example 2, the concentration of the additive metal element in the internal electrode pattern was set to 5 at %. Other conditions were the same as in Example 1.
(Example 3) In Example 3, the concentration of the additive metal element in the internal electrode pattern was set to 5 at %. The concentration of the additive metal element in the dielectric pattern was set to 0 atomic %. Other conditions were the same as in Example 1.
(Example 4) In Example 4, Sn was used as the additive metal element instead of Au. Other conditions were the same as in Example 1.
(Example 5) In Example 5, Sn was used as the additive metal element instead of Au. Other conditions were the same as in Example 2.
(Example 6) In Example 6, Sn was used as the additive metal element instead of Au. Other conditions were the same as in Example 3.
(Comparative example 1) In Comparative Example 1, no additive metal element was used. Therefore, the concentration of the additive metal element in the dielectric green sheet was set to 0 at %, the concentration of the additive metal element in the internal electrode pattern was set to 0 at %, and the concentration of the additive metal element in the dielectric pattern was set to 0 at %. Other conditions were the same as in Example 1.
(Comparative example 2) In Comparative Example 2, Au was used as the additive metal element. The concentration of the additive metal element in the dielectric green sheet was 0 at %, the concentration of the additive metal element in the internal electrode pattern was 1 at %, and the concentration of the additive metal element in the dielectric pattern was 0 at %. Other conditions were the same as in Example 1.
(Comparative Example 3) In Comparative Example 3, Au was used as the additive metal element. The concentration of the additive metal element in the dielectric green sheet was 1 at %, the concentration of the additive metal element in the internal electrode pattern was 1 at %, and the concentration of the additive metal element in the dielectric pattern was 1 at %. Other conditions were the same as in Example 1.
When the vicinity of the interface between the internal electrode layer and the dielectric layer in the capacity section was analyzed for Examples 1 to 3, a segregation layer of Au was confirmed. In Examples 4 to 6, when the vicinity of the interface between the internal electrode layer and the dielectric layer in the capacity section was analyzed, a segregation layer of Sn was confirmed.
The concentration ratio R of the additive metal element was measured for each of the multilayer ceramic capacitors of Examples 1-6 and Comparative Examples 1-3. SEM-EDS was used for the measurement. The concentration ratio R was 1.7 in Example 1, 1.2 in Example 2, 1.6 in Example 3, 1.9 in Example 4, and 1.5 in Example 5, 1.8 in Example 6, 1.0 in Comparative Example 2, 1.0 in Comparative Example 3. In Comparative Example 1, no additive metal element was added, so the concentration ratio R could not be measured.
Next, an electrostatic capacity test was conducted on each of the multilayer ceramic capacitors of Examples 1 to 6 and Comparative Examples 1 to 3. In the electrostatic capacity test, the sample was left at 150° C. for 1 hour and under standard conditions for 24 hours, and then the electrostatic capacity was measured using an LCR meter under conditions of 0.5 V-1 kHz. The electrostatic capacity was 22 μF in Example 1, 20 μF in Example 2, 22 μF in Example 3, 22 μF in Example 4, 21 μF in Example 5, and 22 μF in Example 6, 22 μF in Comparative Example 1, 15 μF in Comparative Example 2, and 15 μF in Comparative Example 3. When the measured electrostatic capacity was 20 μF or more, it was judged as good, and when the measured electrostatic capacity was less than 20 μF, it was judged as bad. It is thought that if the bondability between the internal electrode layers and the external electrodes ss good, the electrostatic capacity will increase. In Examples 1 to 6 and Comparative Example 1, the electrostatic capacity was judged to be good, and in Comparative Examples 2 and 3, the electrostatic capacity was judged to be bad.
Next, a reliability test was conducted on each of the multilayer ceramic capacitors of Examples 1 to 6 and Comparative Examples 1 to 3. In the reliability test, a voltage of 6.3 V was applied at 85° C. for 1000 hours and 2000 hours, and then left at room temperature for 24 hours, after which insulation resistance was evaluated. An insulation resistance value of less than 10 MΩ was regarded as failure. If no failure occurred even after 1000 hours, it was judged as good “0”. If no failure occurred even after 2000 hours, it was judged as very good “double circle”. If failure occurred until 1000 hours, it was judged as bad “x”. In the reliability test, Example 1 was judged to be good “∘”, Example 2 was judged to be very good “double circle”, Example 3 was judged to be very good “double circle”, Example 4 was judged to be good “∘”, Example 5 was judged to be very good “double circle”, Example 6 was judged to be very good “double circled”, Comparative Example 1 was judged to be bad “x”, Comparative Example 2 was judged to be bad “x”, and Comparative Example 3 was judged to be good “∘”.
If it was not judged to be bad in either the reliability test or the electrostatic capacity test, the overall judgment was “good”. If any one of the reliability test and the electrostatic capacity test was judged to be bad, the overall judgment was “bad”.
All of Examples 1 to 6 were judged to be “good” in the overall evaluation. It is thought that this was because the concentration of the additive metal element in the dielectric green sheet was higher than the concentration of the additive metal element in the dielectric pattern, diffusion of the additive metal element from the internal electrode layer to the dielectric layer was suppressed in the capacity section, and the concentration of the additive metal element was lower in the second section 32 than in the first section 31. On the other hand, in Comparative Examples 1 to 3, the overall judgment was “bad”. In Comparative Example 1, it is thought that the additional metal element was not added to the internal electrode pattern, and a segregation layer of the additional metal element was not formed, so that sufficient reliability was not obtained. In Comparative Example 2, it is thought that the additive metal element diffused from the internal electrode pattern to the dielectric layer and the dielectric pattern, and a sufficient segregation layer was not formed. In Comparative Example 3, it is thought that the diffusion of the additive metal element from the internal electrode layer to the dielectric pattern was suppressed, and the concentration of the additive metal element in the internal electrode layer of the end margin was increased. In Examples 2, 3, 5, and 6, it is thought that the addition of a large amount of the additive metal element to the internal electrode pattern increased the concentration of the additive metal element in the segregation layer, resulting in high reliability. In Examples 3 and 6, as compared with Examples 2 and 5, it is thought that diffusion of the additive metal element into the dielectric pattern was promoted, and high electrostatic capacity was obtained. Further, comparing the concentration ratio R, it is confirmed that Sn diffuses more easily into barium titanate than Au.
(Example 7) In Example 7, Sn was used as the additive metal element in the dielectric green sheet and the internal electrode pattern, and Cu was used as the additive metal element in the dielectric pattern. The concentration of Sn in the dielectric green sheet was set to 1 at %, and a Ni paste containing 1 at % of Sn was printed on the dielectric green sheet as an internal electrode pattern. And the dielectric pattern containing 0.5 at % or more of Cu was printed around the Ni paste. Thus, a stack unit was obtained. Barium titanate was used as the main component ceramic of the dielectric green sheet and the dielectric pattern. A plurality of stack units thus obtained were stacked and cut to obtain a compact. The number of the stack units was 500 layers. Ni paste was applied to the two end faces of the compact obtained, and the compact was fired. The obtained multilayer ceramic capacitor had a shape of 1005 (length 1.0 mm, width 0.5 mm, height 0.5 mm). The thickness of the dielectric layer was 0.6 μm.
(Example 8) In Example 8, Sn was used as the additive metal element in the dielectric green sheet and the internal electrode pattern, and Zn was used as the additive metal element in the dielectric pattern. The concentration of Sn in the dielectric green sheet was set to 1 at %, the concentration of Sn in the internal electrode pattern was set to 1 at %, and the concentration of Zn in the dielectric pattern was set to 0.5 at %. Other conditions were the same as in Example 7.
(Example 9) In Example 9, Fe was used as the additive metal element in the dielectric green sheet and the internal electrode pattern, and Al was used as the additive metal element in the dielectric pattern. The concentration of Fe in the dielectric green sheet was set to 1 at %, the concentration of Fe in the internal electrode pattern was set to 1 at %, and the concentration of Al in the dielectric pattern was set to 0.5 at %. Other conditions were the same as in Example 7.
(Example 10) In Example 10, Fe was used as the additive metal element in the dielectric green sheet and the internal electrode pattern, and Cr was used as the additive metal element in the dielectric pattern. The concentration of Fe in the dielectric green sheet was set to 1 at %, the concentration of Fe in the internal electrode pattern was set to 1 at %, and the concentration of Cr in the dielectric pattern was set to 0.5 at %. Other conditions were the same as in Example 7.
(Comparative Example 4) In Comparative Example 4, Sn was used as the additive metal element in the dielectric green sheet and the internal electrode pattern, and Au was used as the additive metal element in the dielectric pattern. The concentration of Sn in the dielectric green sheet was set to 1 at %, the concentration of Sn in the internal electrode pattern was set to 1 at %, and the concentration of Au in the dielectric pattern was set to 1 at %. Other conditions were the same as in Example 7.
(Comparative Example 5) In Comparative Example 5, Fe was used as the additive metal element in the dielectric green sheet and the internal electrode pattern, and Au was used as the additive metal element in the reverse pattern. The concentration of Fe in the dielectric green sheet was set to 1 at %, the concentration of Fe in the internal electrode pattern was set to 1 at %, and the concentration of Au in the reverse pattern was set to 1 at %. Other conditions were the same as in Example 7.
The concentration ratio R of the additive metal element was measured for each of the multilayer ceramic capacitors of Examples 7 to 10 and Comparative Examples 4 and 5. SEM-EDS was used for the measurement. The concentration ratio R was 2.2 in Example 7, 2.0 in Example 8, 1.8 in Example 9, 1.8 in Example 10, and 1.0 in Comparative Example 4, and 1.0 in Comparative Example 5.
Next, the electrostatic capacity test was conducted on each of the multilayer ceramic capacitors of Examples 7-10 and Comparative Examples 4 and 5. In the electrostatic capacity test, the sample was left at 150° C. for 1 hour and under standard conditions for 24 hours, and then the electrostatic capacity was measured using an LCR meter under conditions of 0.5 V-1 kHz. The electrostatic capacity was 22 μF in Example 7, 22 μF in Example 8, 22 μF in Example 9, 22 μF in Example 10, 15 μF in Comparative Example 4, and 15 μF in Comparative Example 5. When the measured electrostatic capacity was 20 μF or more, it was judged as good, and when the electrostatic capacity was less than 20 μF, it was judged as bad. In Examples 7 to 10, the electrostatic capacity was judged to be good, and in Comparative Examples 4 and 5, the electrostatic capacity was judged to be bad.
Next, the reliability test was conducted on each of the multilayer ceramic capacitors of Examples 7-10 and Comparative Examples 4 and 5. In the reliability test, a voltage of 6.3 V was applied at 85° C. for 1000 hours and 2000 hours, and then left at room temperature for 24 hours, after which insulation resistance was evaluated. An insulation resistance value of less than 10 MΩ was regarded as failure. If no failure occurred even after 1000 hours, it was judged as good “∘”. If no failure occurred even after 2000 hours, it was judged as very good “double circle”. If failure occurred until 1000 hours, it was judged as bad “x”. In the reliability test, Example 7 was judged to be good “∘”, Example 8 was judged to be good “∘”, Example 9 was judged to be good “∘”, Example 10 was judged to be good “∘”, Comparative Example 4 was judged to be good “∘”, and Comparative Example 5 was judged to be good “∘”.
If it was not judged to be bad in either the reliability test or the electrostatic capacity test, the overall judgment was “good”. If any one of the reliability test and the electrostatic capacity test was judged to be bad, the overall judgment was “bad”.
Regarding Examples 7 to 10, even if the additive metal element added to the internal electrode pattern and the additive metal element added to the dielectric pattern were different from each other, the overall judgment was “good”. It is thought that this was because Sn and Cu were easily alloyed, Sn and Zn were easily alloyed, Fe and Al were easily alloyed, or Fe and Cr were easily alloyed. On the other hand, in Comparative Examples 4 and 5, the overall judgment was “bad”. It is thought that this was because the diffusion of the additive metal element from the internal electrode layer to the dielectric pattern was suppressed, and the concentration of the additive metal element in the internal electrode layer of the end margin was increased.
Although the embodiments of the present invention have been described in detail, it is to be understood that the various change, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-161773 | Oct 2022 | JP | national |
