Charge coupled eeprom device and corresponding method of operation

Abstract

This invention provides a semiconductor memory device and a corresponding method of operation. The semiconductor memory device comprises a semiconductor substrate (1) having a first conductivity (p); a plurality of gate structures (CG1, FG1; . . . ; CGn, FGn) for storing charge in a non-volatile manner regularly arranged in above the surface of the semiconductor substrate (1) and electrically isolated therefrom; a plurality of wordlines (WL1-WL5), each of said gate structures (CG1, FG1; . . . ; CGn, FGn) being connected to one of said wordlines (WL1-WL5) and a group of said gate structures (CG1, FG1; . . . ; CGn, FGn) being connected to a common wordline (WL1-WL5); and a plurality of active regions (10, 20), each of said active regions (10, 20) being individually connectable to at least one of said gate structures (CG1, FG1; . . . ; CGn, FGn).

Description

[0001] The present invention relates to a semiconductor memory device and a corresponding method of operation. S. K. Lahiri: MNOS/Floating-Gate Charge Coupled Devices for High Density EEPROMs: A New Concept, Physics of Semiconductor Devices, V. Kumar and S. K. Agarwal (eds.), Narosa Publishing House, New Delhi, India, 1998, pages 951-956, the basic. idea of CCD EEPROMS is known. Particularly, this conference paper discloses the general idea to arrange EEPROM gate structures each having a floating and a control (CCD) gate above a substrate in rows separated by rails of active areas or injectors provided in said substrate. However, S. K. Lahiri fails to disclose a suitable memory address scheme for such a CCD EEPROM taking into consideration a dynamic clocking. Moreover, this document also fails to disclose appropriate cells layouts and operation modi.

[0002] For example, CCD devices are known from W. S. Boyle, G. E. Smith: Charge Coupled Semiconductor Devices. The Bell System Technical Journal. American Telephone and Telegraph Company: New York, April 1970. Pages 587-593; Rudolf Müller: Bauelemente der Halbleiter-Elektronik. Springer Verlag: Berlin, Heidelberg, New York, London, Paris, Tokyo 1987. Seiten 192-195; Kurt Hoffmann: VLSI-Entwurf. Modelle und Schaltungen. Oldenbourg Verlag: München, Wien 1996. Seiten 296-297; and Lev I. Berger: Semiconductor Materials. CRC-Press: 1997. Page 445.

[0003] EEPROM devices are generally well known in the state of the art. EEPROM cells are used to store information, which should be still accessable after switching the power supply off and on again, while being able to modify the stored information multiple times by pure electrical means. EEPROM cells usually have source and drain contacts forming a MOS transistor. Information is read out by measuring the attributes of the output characteristic, which is dependent of the information stored in a gate structure having floating and control gate.

[0004] The overall transfer characteristic (programming conditions to read current) is highly nonlinear and strong dependent on several side effects and production fluctuations. I.e. the Fowler Nordheim tunnelling current is more than exponentially dependent on the electric field across the oxide. So the programming voltage and the oxide thickness have severe influence on the programming process. Thus, these parameters must be adjusted with high precision. These accuracy problems limit the multilevel ability of known cell concepts to 2 bits per cell.

[0005] Fast cells are critical and must be handled with complex algorithms. Usually, only cells of a single wordline can be programmed at the same time. During sensing, there is a static current consumption through S and D of the MOS transistor. During parallel programming of cells in the test phase, there is a static current due to the gate induced drain leakage, which must be supplied by a charge pump. This current driving pump is area consuming.

[0006] Using drain and source contacts, the cell area of typical cells in embedded EEPROM modules results in 22*F2 to 70*F2. The world record for cells with drain and source contacts is 8.8*F2.

[0007] Nowadays new applications for non-volatile memories are borne, one of that is the possibility to store photos or music in solid state device. In this kind of application is required a sequential data access to the memory.

[0008] Therefore, it is an object of the present invention to provide an improved semiconductor memory device and a corresponding method of operation providing sequential data access.

[0009] According to the present invention this object is achieved by the device defined in claim 1 and the method defined in claim 13.

[0010] The idea underlying the present invention is to combine the charge shifting, receiving or providing (from now on denoted only by shifting) ability and the possibility to store charge non-volatile in an oxide or on a floating gate (EEPROM) or a similar structure. The device or memory cells according to the invention will therefore be called charge coupled EEPROM cells or CC-EEPROM cells herein below.

[0011] In fact, by combining CCD and EEPROM technologies, it is possible to increase the density of the memory and—at the same time—to build a non-volatile memory that is sequentially addressable itself and even usable as a volatile memory.

[0012] CCD technique is known to operate with 8 bit resolution. In combination with the linear transfer characteristic of the charge coupled EEPROM and the self limiting programming, this should provide deep multilevel ability. Fast cells do not have any influence on the programming process, because the programming stops, when all charge carriers tunnelled to the floating gate. It is possible, to shift charge carriers into the cell area and to program a huge number of wordlines in parallel. This cuts the programming time of some order of magnitude. There is no static current consumption during read. Minimum size cells (4F2) are possible, because the cell does not have drain or source contacts. Reduction of logic in the bitline and wordline section result in less chip area. There is an additional volatile memory functionality (i.e. using the same technology, it is also possible to implement high density memory buffer).

[0013] Preferred embodiments are listed in the respective dependent claims.

[0014] According to a preferred embodiment, a plurality of wordlines is provided and a respective group of said gate structures being connected to a respective wordline.

[0015] According to another preferred embodiment, said plurality of gate structures for storing charge in a non-volatile manner is arranged in rows and columns.

[0016] According to another preferred embodiment, each row has an associated first active region located at a first end of said row.

[0017] According to another preferred embodiment, each row has an associated second active region located at a second end of said row.

[0018] According to another preferred embodiment, said wordlines are located above said columns.

[0019] According to another preferred embodiment, between each of said active regions and said at least one of said gate structures a gate structure for storing charge in a volatile manner is arranged.

[0020] According to another preferred embodiment, a voltage generation means for applying individual voltages between said wordlines and said active regions such that charge may be programmed, read, shifted, and erased from said gate structures is provided.

[0021] According to another preferred embodiment, said substrate includes a body contact which is connected to said voltage generation means for applying individual voltages between said wordlines, said active regions and said substrate.

[0022] According to another preferred embodiment, the doping of the substrate is non-uniformly under said gate structures on the one hand and under a spacing between two of said gate structures of the other.

[0023] According to another preferred embodiment, a sense amplifier connected to said active regions.

[0024] According to another preferred embodiment, a gate for separating said at least one active region from said gate structures to selectively connect said at least one active region to said gate structures for programming or reading said gate structures is provided.

[0025] According to another preferred embodiment, a programming of a gate structure is arranged by supplying it with a programming voltage and by supplying the other gate structures of the corresponding row with a select voltage which is greater than said programming voltage.

[0026] According to another preferred embodiment, a programming of a gate structure is arranged by supplying it with a programming voltage and by supplying the gate structures of the corresponding row lying between said gate structure and the active region with a select voltage which is greater than said programming voltage.

[0027] According to another preferred embodiment, a programming of a gate structure is arranged by adjusting a charge quantity to be programmed under one of said gate structures; shifting said charge quantity to be programmed from said one of said gate structures to another one of said gate structures; and programming said charge quantity to said another one of said gate structures.

[0028] According to another preferred embodiment, a programming of a gate structure is arranged by adjusting a charge quantity to be programmed beneath a gate structure to be programmed; and programming said charge quantity to said gate structure.

[0029] According to another preferred embodiment, a reading of a gate structure is arranged by supplying it with a read voltage and by supplying the other gate structures of the corresponding row with a select voltage which is greater than said read voltage such that there is a static current flow between a first and second active region connected to the ends of said row; and by sensing said static current flow.

[0030] According to another preferred embodiment, a read adjusting of a gate structure is arranged by adjusting a charge quantity to be read under one of said gate structures by supplying it with a read adjust voltage and by supplying the gate structures of the corresponding row lying between said gate structure and the active region with a select voltage which is greater than said read adjust voltage.

[0031] According to another preferred embodiment, a reading of a gate structure is arranged by said charge quantity to be read being shifted from said one of said gate structures to one of said active regions and sensed by a sense amplifier connected thereto.

[0032] According to another preferred embodiment, an erase operation is performed by applying an erase voltage across at least one of said gate structures and said substrate.

[0033] According to another preferred embodiment, a multilevel programming of said gate structures is performed.

[0034] According to another preferred embodiment, a block programming is performed by adjusting a respective programming charge beneath a plurality of said gate structures to be programmed and by simultaneously programming said plurality of said gate structures by applying a programming voltage.

[0035] According to another preferred embodiment, the semiconductor memory device according to the invention is used as a volatile memory.

[0036] Embodiments of the present invention are illustrated in the accompanying drawings and described in detail in the following.

[0037] In the Figures:

[0038] FIG. 1 shows a CC-EEPROM cell arrangement according to an embodiment of the invention;

[0039] FIG. 2 shows the erase mode for a specific gate structure of the CC-EEPROM cell arrangement according to the embodiment of the invention;

[0040] FIG. 3 shows the channel hot electron programming mode for a specific gate structure of the CC-EEPROM cell arrangement according to the embodiment of the invention;

[0041] FIG. 4 shows. the Fowler Nordheim programming mode for a specific gate structure of the CC-EEPROM cell arrangement according to the embodiment of the invention;

[0042] FIG. 5 a,b show the adjust charge mode for programming a limited charge for a specific gate structure of the CC-EEPROM cell arrangement according to the embodiment of the invention;

[0043] FIG. 6 a -c show the charge shifting mode for shifting a limited charge for a specific gate structure of the CC-EEPROM cell arrangement according to the embodiment of the invention;

[0044] FIG. 7 shows the Fowler Nordheim programming mode for programming a limited charge for a specific gate structure of the CC-EEPROM cell arrangement according to the embodiment of the invention;

[0045] FIG. 8 shows the NAND reading mode for a specific gate structure of the CC-EEPROM cell arrangement according to the embodiment of the invention;

[0046] FIG. 9 a,b show the adjust charge mode for reading a limited charge for a specific gate structure of the CC-EEPROM cell arrangement according to the embodiment of the invention; and

[0047] FIG. 10 a -c show the charge sink and sense amplifier for a specific gate structure of the CC-EEPROM cell arrangement according to the embodiment of the invention; und

[0048] FIG. 11 shows a possible two-dimensional CC-EEPROM cell arrangement according to an embodiment of the invention.

[0049] Throughout the figures the same reference numbers indicate the same or functionally equivalent means. It should be noted that the individual figures for explaining specific modes of operation do not include all details, but just the details needed for explaining the respective mode.

[0050] FIG. 1 shows a CC-EEPROM cell arrangement according to a embodiment of the invention in a schematic representation.

[0051] In FIG. 1, reference sign 1 denotes a p-type semiconductor substrate, f.e. a silicon substrate, having an n+-type source and drain region 10 and 20, respectively, and having a p+-type body contact 30.

[0052] Between the n+-type source and drain regions 10, 20 there is a plurality of aligned gate structures. The gate structures include floating gates FG1, FG2, . . . , FGn−1, and FGn above the substrate surface and electrically isolated therefrom. Moreover, each of the floating gates FG1, FG2, . . . , FGn−1, and FGn has a corresponding control gate CG1, CG2, . . . , CGn−1, CGn which is electrically isolated therefrom. Thus the gate structures are similar to the gate structure of an EEPROM, however, here a plurality of gate structures each consisting of a floating and control gate pair is aligned with preferably equidistant spacing.

[0053] S, G1, G2, . . . , Gn−1, Gn, D, B denote respective contacts of the corresponding source, drain, bulk, and gate regions. Only schematically shown in FIG. 1 is a voltage generation means 100 for applying individual voltages between said gate structures CG1, FG1; . . . ; CGn, FGn and said active regions 10, 20 and body contact 30 such that charge may be programmed, read, shifted, and erased from said gate structures CG1, FG1; . . . ; CGn, FGn. The voltage generation means 100 is connected to the respective contacts of the corresponding source, drain, bulk, and gate regions S, G1, G2, . . . , Gn−1, Gn, D, B. The associated functions will be described later.

[0054] The direction SD pointing from the source region 10 to the drain region 20 along the gate structures is called shifting direction. In this shifting direction SD, the intermediate cell gate structures are not flanked by a heavy source/drain doping like in normal EEPROM cells or MOS transistors—otherwise the charge isolating and conserving capability for the adjusted charge to be described later would vanish. However, to a certain limit, light source/drain doping may be acceptable.

[0055] The CC-EEPROM cell arrangement of FIG. 1 is arranged in a way, that charge can be shifted from one gate structure to another, i.e. CCD like. The cell arrangement contains a minimum of one non-volatile cell. Gate structures of this arrangement need not all to be non-volatile cells (f.e. there may be gates just for shifting, gates just supplying volatile memory or gates next to a heavy source or drain doping) or need not all to be used for non-volatile storing (f.e. there may be dummy cells or gates next to a heavy source or drain doping). The gate alignment needs not to have straight line characteristic, but meander, tree, parallel, . . . structures are also possible.

[0056] The arrangement normally has a minimum of one contacted or uncontacted source/drain doping, which can act as a charge source or sink. This doping can be located on the beginning or end (edge) of the arrangement. There might be a bulk contact. Bulk can but needs not to be isolated from the substrate by any means (junction, oxide, insulator). A minimum cell area is feasible due to the minimum number of drain and source contacts.

[0057] Doping is somehow a subject for trade off (see below) and can be done non-uniformly or differently under the tunnel oxide on the one hand and under the spacing between two gates of the other. However, also uniform doping is possible.

[0058] For shifting inversion charge from one gate structure to the other, the depletion regions, which are induced by these gates, must touch laterally. This is achieved at relatively low or medium voltages, when the effective doping between these gates is low. Thus, a low intrinsic bulk doping or a contra doping is preferred.

[0059] Programming voltage is shared by the inter poly oxide (between floating and control gate), the tunnel oxide (both effects known from normal EEPROM cells) and an unwanted, extending depletion region under the cell.

[0060] In order to achieve the electrical field in the tunnel oxide, needed for Fowler Nordheim tunneling, at a minimum programming voltage, this depletion region can be limited by a heavy doping beneath the tunnel oxide, eventually spaced to the semiconductor surface.

[0061] Heavy doping is in contradiction to the need mentioned above regarding charge shifting. Therefore, the above mentioned trade-off should be found in practice. In any case, low doping is needed only at the surface.

[0062] Generation and recombination limit the available time after start of adjusting charge quantities to completion of reading or programming. The buried CCD approach known from R. H. Walden, R. H. Krambeck, R. J. Strain, J. McKenna, N. L. Schryer, G. E. Smith: The Buried Channel Charge Coupled Devices. The Bell System Technical Journal. American Telephone and Telegraph Company: New York, September 1972. Pages 1635-1640; and D. J. Burt: Basic Operation of the Charge Coupled Device. Proc. Int. Conf. Technol. Applic. CCD. Edinburgh University: Edinburgh 1974, Pages 1-12, which is used to cope with the high generation and recombination at the semiconductor/oxide interface, increases the read immunity and requires increased program voltage.

[0063] FIG. 2 shows the erase mode for a specific single gate structure CG1, FG1 of the CC-EEPROM cell arrangement according to the embodiment of the invention.

[0064] In order to explain that this embodiment of the invention is compatible with normal non-volatile memory operation, here is showed, how to erase one cell having control gate CG1 and floating gate FG1 or all in parallel, applying appropriate bias and using the well known Fowler Nordheim tunneling.

[0065] Erasing is done by applying an electrical field to the tunnel oxide in the orientation, that majority charge carriers, here holes (+), are accumulating on the semiconductor surface in an accumulation region AC. Thereby, electrons (−) stored in the floating gate FG1 may be extracted. Therefore, an erase voltage Ver is applied across a minimum of one CCD cell line bulk on the one hand and a minimum or one cell control gate on the other. This erase voltage Ver of typically 16-18 V physically adds to the source-bulk-voltage VSB of typically >−0.7 V. It should be mentioned that here and in the following description all voltages are referred to the source voltage, however, this is just one of several possibilities.

[0066] Erase is not self-limiting and cells behave differently, so one or more read verify plus program cycles may complete the erase step.

[0067] Next, programming of the CC-EEPROM cells will be explained. In known memory devices, programming was always performed with unlimited charge for a predetermined time period. However, according to this embodiment programming can either be done with unlimited charge or with limited charge.

[0068] Particularly, programming with an unlimited charge source provides a random access possibility.

[0069] Programming voltage and/or programming time adjust the amount of charge, which is tunneling from the inversion layer through the tunnel oxide to the floating gate (Fowler Nordheim tunneling) or is injected into the tunnel oxide (channel hot electron).

[0070] FIG. 3 shows the channel hot electron programming mode for a specific gate structure of the CC-EEPROM cell arrangement according to the embodiment of the invention.

[0071] This structure is operated somehow similar to a NAND CHE (channel hot electron) EEPROM. The source/drain doping in-between two cells is functionally substituted by supplying an appropriate Vsel to all cells, which should not be programmed, so that the gaps between cells have a continuous inversion layer INV. The cell having the gate structure FG3, CG3 to be programmed is supplied with a programming voltage Vpr which is smaller than Vsel, while Vse1 is greater than VDS. These voltages add to the source-bulk-voltage VSB.

[0072] By supplying these voltages, a charge density CDE is created below the gate structure. FG3, CG3. At the location where this charge density CDE is nearly zero, a channel hot electron region CHE is created from where hot electrons can enter into the floating gate FG3.

[0073] It should be noted that when using channel hot electron programming, it is also possible to use a SONOS gate structure leaving out the floating gate, as described in Boaz Eitan, Paolo Pavan, Ilar Bloom, Efraim Aloni, Aviv Frommer, David Finzi: NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell. IEEE Electron Device Letters, Vol. 21, No. 11. IEEE: November 2000. Pages 543-545.

[0074] FIG. 4 shows the Fowler Nordheim programming mode for a specific gate structure of the CC-EEPROM cell arrangement according to the embodiment of the invention with unlimited charge source.

[0075] An inversion layer INV is built up from the source 10 to the cell having the gate structure FG3, CG3 which should be programmed. This can be done by selecting and deselecting other cells in an appropriate manner or by another special gate structure, which is placed near by every cell (f.e. in the third dimension).

[0076] Here, the select voltage Vsel is applied to the two left hand cells and a deselect voltage Vdesel is applied to the right hand neighbour cell. The cell having the gate structure FG3, CG3 to be programmed is supplied with a programming voltage V′pr which is greater than Vpr in the case of channel hot electron programming. Fowler Nordheim programming mode has the advantage that it is current saving in comparison to channel hot electron programming, because no current flow exists between source and drain 10, 20.

[0077] Next, programming with a limited charge will be explained. Programming with a limited charge source is done in three steps: adjusting charge quantity, shifting the charge to the cell to be programmed and finally programming, which means that this charge is tunneled to the floating area of the cell to be programmed.

[0078] Adjusting and shifting charge can be done in parallel, so that a huge fraction of the sector can be filled with this information carrying charge quantities, which can finally be programmed in parallel (burst programming). In other words, having a two-dimensional array of CC EEPROM cells, first the information of all cells may be shifted under the array, and then all the information may be programmed in a single step. Because programming is time consuming (several milliseconds for Fowler Nordheim tunneling), this parallel programming dramatically speeds up the memory filling with a continuous data stream (burst).

[0079] There is no need for a special page buffer, which results in a smaller chip area due to the reduced logic in the bitline section.

[0080] The programming of a cell ends automatically, when all charge beneath the tunnel oxide is tunneled to the floating gate. A self-limiting programming is achieved, supplying a multilevel ability, even in case of fast cells.

[0081] FIG. 5 a,b show the adjust charge mode for programming a limited charge for a specific gate structure of the CC-EEPROM cell arrangement according to the embodiment of the invention.

[0082] Techniques for adjusting the charge quantity which will be programmed later on are well known from charge coupled devices (CCD filters).

[0083] First, as illustrated in FIG. 5a a continuous inversion layer INV is built up from the source 10 to the adjusting gate structure CG2, FG2 by selecting the gate structure CG1, FG1 inbetween. Moreover, the right hand neighbor gate structure CG3, FG3 is deselected.

[0084] The amount of charge QIpr is adjusted by the program adjust voltage Vprad which is linearly related by the following formula:

Q Ipr =−A ox (Cox″(Vprad−VFB−2ΦF)−{square root}{square root over (2qε0εSiNA(2ΦF+VSB))})  (0)

[0085] which is valid in the case that the adjusting MOSFET does not have a floating gate. Here ΦF is the Fermi potential, VFB the flatband voltage, VSB the source-bulk voltage, and the remaining terms are constants. If the adjusting MOSFET has a floating gate, then formula 11 below applies.

[0086] Then, with reference to FIG. 5b this adjusted charge is separated from the source 10 by deselecting the gate structure CG1, FG1 between the source 10 and the adjusting gate structure CG2, FG2.

[0087] Instead of adjusting the charge quantity by the Vprad voltage, the desired charge amount could also be brought in via the source contact S (see FIG. 1) which would not be at a fixed potential in this case. The charge can also be delivered by a charge adjusting circuitry which is connected to the source contact.

[0088] The cell having the gate structure CG1, FG1 next to the source 10 is a dummy cell (no information storage is possible in limited charge programming mode) and in principle needs not to have a floating gate. The next cell, to which Vprad is applied, could also be a dedicated-transistor.

[0089] Adjusting can be done in parallel to reading another wordline as explained later.

[0090] FIG. 6 a -c show the charge shifting mode for shifting a limited charge for a specific gate structure of the CC-EEPROM cell arrangement according to the embodiment of the invention.

[0091] Charge shifting from one cell to another is well known and vastly documented for charge coupled devices (CCD camera, CCD filter).

[0092] The easiest way to achieve this is to interconnect the control gate of every third cell. This results in only three wordlines, which must be driven in an appropriate manner. So, a corresponding wordline section needs less control logic and less driving units, resulting in a reduced chip area.

[0093] As shown in FIG. 6a, the starting situation is identical with the situation of FIG. 5b. Additionally shown is the gate structure having control gate CG4 and floating gate FG4 which is also deselected.

[0094] Having regard to FIG. 6b, the gate structure CG3, FG3 is then selected by applying selection voltage Vsel. As a consequence, inversion layer INV expands to the gate structure CG3, FG3.

[0095] Now, as shown in FIG. 6c, the gate structure CG2, FG2 is deselected by applying deselection voltage Vdesel. As a consequence, inversion layer INV contracts to the gate structure CG3, FG3 which remains selected.

[0096] By the above process sequence, the limited charge quantity is shifted from one cell to the other.

[0097] FIG. 7 shows the Fowler Nordheim programming mode for programming a limited charge for a specific gate structure of the CC-EEPROM cell arrangement according to the embodiment of the invention.

[0098] Non-volatile programming is done by applying programming voltage Vpr to the control gates of cell having the gate structure CG3, FG3 which should be programmed, leaving the neighbor cells deselected.

[0099] The equation for the Fowler Nordheim tunneling current density according to Georg Tempel: Reprogrammable Silicon-based Non Volatile Memories. Infineon Technologies AG. CPD IPD RC IMEC: Leuven, Belgium 2001. Page 1-29, reads: 1$\begin{array}{cc}{J}_{\mathrm{FG}}=\alpha E_{\mathrm{tox}}^2{\epsilon }^{\frac{\beta }{E_{\mathrm{tox}}}}& \left(1\right)\\ E_{\mathrm{tox}}=\frac{V_{\mathrm{FG}}-V_l}{d_{\mathrm{tox}}}& \left(2\right)\\ \alpha =\frac{m}{m*}\frac{q^3}{8\pi h{\Phi }_b}& \left(3\right)\\ \beta =4\sqrt{2m*}\frac{2\pi }{3\mathrm{hq}}{\Phi }_b^{\frac{3}{2}}& \left(4\right)\end{array}$

[0100] with

	h	6.6 · 10−34 Js	Planck's constant
	Φb	3.2 eV	energy barrier
		(Si—SiO2)	at injecting interface
	q	1.6 · 10−19 C	charge of single electron
	m	9.1 · 10−31 kg	mass of free electron
	m*	0.42 m	effective mass of
		(SiO2)	electron in band gap

[0101] and was originally derived under the assumption that the conduction band is filled with charge carriers.

[0102] However, when using the CCD principle for shifting charge beneath the floating gate in order to program, this charge is limited and steadily decreasing when charge carriers tunnel onto the floating gate during programming phase. Therefore it is assumed that the tunneling probability for each charge carrier is identical. This results in an approximately exponential tunneling current drop by time (neglecting electric field reduction due to charging of the floating gate).

[0103] Thus, using the CCD principle, a single programming procedure will approximately take 3 times longer than usually as rule of thumb. However, using burst programming, there will be still an enormous time saving compared to conventional programming time.

[0104] The limited charge programming procedure may also be done in two steps, namely first program adjust beneath the cell to be programmed (like read adjust in FIG. 5) and secondly program the charge to the floating gate as mentioned above.

[0105] Next, reading of the cells will be explained. There are two different possible reading modes, the NAND mode and the CCD mode.

[0106] The NAND mode reading provides a random access. The situation of reading in NAND mode is very similar to channel hot electron programming. Only the applied read voltage Vread is different.

[0107] FIG. 8 shows the NAND reading mode for a specific gate structure of the CC-EEPROM cell arrangement according to the embodiment of the invention.

[0108] As a consequence of the applied voltages, namely Vsel to the cells not to be read and Vread to the cell to be read, there is a static current flow Is which may be sensed by a sense amplifier SA.

[0109] In analogy with the CCD programming mode, the CCD reading mode consists of three operation procedures: adjusting read charge, shifting charge towards the output and sensing the charge. There is no static current consumption. As a consequence of the shifting procedure, there is only a burst reading without a random access possibility.

[0110] Here, the charge density CDE in the reading region RR depends on the information stored in the cell.

[0111] FIG. 9 a,b show the adjust charge mode for reading a specific gate structure of the CC-EEPROM cell arrangement according to the embodiment of the invention.

[0112] Adjusting the reading charge is a preparation phase for the reading. It can be done in parallel to reading another wordline.

[0113] According to FIG. 9a, an inversion layer INV is built up from the source 10 to the cell having gate structure CG3, FG3 which is to be prepared. This can be done by selecting and deselecting other cells in an appropriate manner or by another special gate structure, which is placed near by every cell.

[0114] Here, the select voltage Vsel is applied to the two left hand cells and a deselect voltage Vdesel is applied to the right hand neighbour cell. The cell having the gate structure FG3, CG3 to be prepared is supplied with a read adjust voltage Vreadad such that the charge of the inversion layer INV under the cell is a function of the charge on the floating gate. Vsel is greater than Vreadad, so that the depletion region under the shifting cell is independent of the stored charge on the floating gate of other cells.

[0115] According to FIG. 9b, the inversion layer charge is finally separated from the continuous inversion layer INV to the source 10 by deselecting the neighbour gate having the gate structure CG2, FG2.

[0116] After adjusting the charge for reading, the charge must be shifted towards the output node by the shifting mode explained above with regard to FIG. 6.

[0117] FIG. 10 a -c show the charge sink and sense amplifier for a specific gate structure of the CC-EEPROM cell arrangement according to the embodiment of the invention.

[0118] Sensing is done in parallel to the charge shifting. The sense amplifier SA is connected to the output node, which acts as a charge sink for the shifted charge. As the output node, either the drain 20 or the source 10 can be used. The cell next to the drain 10 is a dummy cell and needs not to have a floating gate (i.e. floating gate may be omitted or floating gate and control gate may be shorted).

[0119] Sensing is well known and documented for charge coupled devices such as CCD camera, CCD filter etc. These known sensing devices proved to be capable sensing at an 8 bit resolution, and facilitate deep multilevel sensing ability for CC-EEPROM cells according to this embodiment.

[0120] According to FIG. 10a, the cell having gate structure CG2, FG2 is deselected, and the cells having gate structures CG3, FG3 and CG4, FG4 are selected. So, the charge to be read is shifted to the drain 20 from the gate structure FG3, CG3.

[0121] According to FIG. 10b, the cell having gate structure CG4, FG4 is selected, and the cells having gate structures CG2, FG2 and CG3, FG3 are deselected. So, the charge to be read is isolated at the drain 20 from the gate structure FG3, CG3.

[0122] According to FIG. 10c, the cell having gate structure CG2, FG2 is selected, and the cells having gate structures CG3, FG3 and CG4, FG4 are deselected. So, new charge to be read coming from gate structure CG1, FG1 (not shown in FIG. 10c) is transferred to the gate structure FG2, CG2.

[0123] Next, the read transfer characteristic will be evaluated. Heretofore, the following physical quantities must be considered:

Ctox   tunnel oxide capacitance
CD,abs absolute depletion region capacitance
Csp    inter poly capacitance
Cfr    fringing capacitance
QA     ambient charge
QCG    control gate charge
QD     depletion region charge
QFG    floating gate charge
QI     inversion layer charge
VA     ambient voltage
VCG    control gate voltage
VFG    floating gate voltage
VI     inversion layer voltage
Vb     bulk voltage

[0124]

VCG = Vadjust − VFB + Vb + VSB control gate potential
(where Vadjust is the respective adjust voltage)
VFB = −kT/q ln(NA ND,CG/ni2)   flat band voltage
VI = 2 ΦF + VSB + Vb           inversion layer potential
ΦF = kT/q ln(NA/ni)            Fermi potential

[0125] In order to be neutral outside of the structure, the sum of all charges must be zero.

Q FG +Q CG +Q A +Q I +Q D =0  (5)

[0126] The equations for the oxide capacitances are

Q CG =C ip (VCG−VFG)  (6)

Q A =C fr (VA−VFG)  (7)

Q I +Q D =C tox (VI−VFG)  (8)

[0127] Equation (8) is rewritten to be 2$\begin{array}{cc}{V}_{\mathrm{FG}}=V_I-\frac{Q_1+Q_D}{C_{\mathrm{tox}}}& \left(9\right)\end{array}$

[0128] The equation for the depletion region capacitance is

Q D =−{square root}{square root over (2qε0εSiNA(VI−Vb))}* A tox   (10)

[0129] where CD,abs denotes an absolute capacitance. Equations (6), (7), (9) and (10) inserted in equation (5) result in

Q I =−γQ FG +Q 0   (11) 3 $$ γ = C tox C tox + C ip + C fr ( 12 ) with   Q 0 = ⁢ 2 ⁢ q ⁢   ⁢ ε 0 ⁢ ε Si ⁢ N A ⁡ ( 2 ⁢ Φ F - V SB ) * A tox - ⁢ γ ⁢   ⁢ C ip ⁡ ( V adjust - V FB - 2 ⁢ Φ F ) - ⁢ γ ⁢   ⁢ C fr ⁡ ( V A - 2 ⁢ Φ F - V SB - V b ) ( 13 )

[0130] This equation shows that the inversion layer charge is linear dependent of the floating gate charge. This clearly reveals the multilevel ability of of the CC-EEPROM cell arrangement according to the embodiment of the invention.

[0131] A volatile memory functionality of unused memory sectors is achieved by the following steps: adjusting charge quantity, shifting this charge under the desired gate structure, storage phase, shifting the charge to the output node and finally sensing the charge. This storage mode has either a first in first out or a first in last out behavior, namely dependent on what the output node is, i.e. source or drain. It can be used e.g. for storing the data to be programmed in another sector in order to realize a target programming algorithm.

[0132] FIG. 11 shows a possible two-dimensional top view of a CC-EEPROM cell arrangement according to an embodiment of the invention.

[0133] In FIG. 11, reference signs WL1-W15 denote five different wordlines arranged in parallel and equidistantly. S1-S4 and D1-D4 denote respective source and drain regions.

[0134] Between source S1 and drain D1, there are five gate structures each consisting of a floating gate and a control gate, the control gates being connected to the wordlines WL1-WL5 at contacts K11, K21, K31, K41, K51.

[0135] Between source S2 and drain D2, there are five gate structures each consisting of a floating gate and a control gate, the control gates being connected to the wordlines WL1-WL5 at contacts K12, K22, K32, K42, K52.

[0136] Between source S3 and drain D3, there are five gate structures each consisting of a floating gate and a control gate, the control gates being connected to the wordlines WL1-WL5 at contacts K13, K23, K33, K43, K53.

[0137] Between source S4 and drain D4, there are five gate structures each consisting of a floating gate and a control gate, the control gates being connected to the wordlines WL1-WL5 at contacts K14, K24, K34, K44, K54.

[0138] Not shown in FIG. 11 for simplification are isolation structures between shifting channels.

[0139] By sequentially applying appropriate voltages to the wordlines WL1-WL5 and to the source and drain regions S1-S4 and D1-D4, information can be shifted in parallel along the shiftig direction SD under the gate structures of wordline WL2 and WL4 and simultaneously be programmed with a single programming burst. In analogy reading may be performed by shifting out the information in parallel along the shifting direction SD to the drains D1-D4.

[0140] In order to prove the most critical aspects to work—charge transfer, charge isolation and applying programming voltage—a device simulation was done. This simulation showed that it is possible to build up a structure, which can shift charge, isolate it and apply a programming voltage while the quantity of isolated charge is only hardly altered by leakage current and thermal generation.

[0141] Although the present invention has been described with regard to specific embodiments, it is not limited thereto, but may be modified in many ways.

[0142] Particularly, CC-EEPROM cells or arrangements can also be mixed with other, well known EEPROM cells or cell elements in order to bring in their functionality.

[0143] Just for generality, it is possible to add some more gates or doping profiles to the arrangement mentioned above, which are added perpendicular to (or better: not in the same direction of) the shifting direction SD. These means can provide additional functionality.

[0144] The floating gates of a CC-EEPROM cell can be routed out of the cell shifting area and can be connected to other structures (gate, flanked doping, transistor, tunnel oxide, . . . ) or in order to provide additional functionality or to combine known NVM (non-volatile memory) principles (channel hot electron, Fowler Nordheim tunneling, reading via MOSFET, . . . ) or charge shifting principles (CCD) with the CC-EEPROM cell principle. So, a minimum of one CCD principle is used in order to erase, program, read non-volatile memory.

Claims

1. A semiconductor memory device comprising: a semiconductor substrate (1) having a first conductivity (p); a plurality of gate structures (CG1, FG1; . . . ; CGn, FGn) for storing charge in a non-volatile manner regularly arranged in above the surface of the semiconductor substrate (1) and electrically isolated therefrom; and at least one active region (10, 20) of the second conductivity (n+), each of said active regions (10, 20) being individually connectable to at least one of said gate structures (CG1, FG1; . . . ; CGn, FGn).

2. The semiconductor memory device according to claim 1, wherein a plurality of wordlines (WL1-WL5) is provided and a respective group of said gate structures (CG1, FG1; . . . ; CGn, FGn) being connected to a respective wordline (WL1-WL5).

3. The semiconductor memory device according to claim 1 or 2, wherein said plurality of gate structures (CG1, FG1; . . . ; CGn, FGn) for storing charge in a non-volatile manner is arranged in rows and columns.

4. The semiconductor memory device according to claim 3, wherein each row has an associated first active region (10) located at a first end of said row.

5. The semiconductor memory device according to claim 4, wherein each row has an associated second active region (20) located at a second end of said row.

6. The semiconductor memory device according one of the preceding claims 2 to 4, wherein said wordlines (WL1-WL5) are located above said columns.

7. The semiconductor memory device according one of the preceding claims, wherein between each of said active regions (10, 20) and said at least one of said gate structures (CG1, FG1; . . . ; CGn, FGn) a gate structure for storing charge in a volatile manner is arranged.

8. The semiconductor memory device according one of the preceding claims, further comprising a voltage generation means for applying individual voltages between said wordlines (WL1-WL5) and said active regions (10, 20) such that charge may be programmed, read, shifted, and erased from said gate structures (CG1, FG1; . . . ; CGn, FGn).

9. The semiconductor memory device according claim 8, wherein said substrate (1) includes a body contact (30) which is connected to said voltage generation means for applying individual voltages between said wordlines (WL1-WL5), said active regions (10, 20) and said substrate (1).

10. The semiconductor memory device according one of the preceding claims, wherein doping of the substrate (1) is non-uniformly under said gate structures (CG1, FG1; . . . ; CGn, FGn) on the one hand and under a spacing between two of said gate structures (CG1, FG1; . . . ; CGn, FGn) of the other.

11. The semiconductor memory device according one of the preceding claims, further comprising a sense amplifier (SA) connected to said active regions (10, 20).

12. The semiconductor memory device according one of the preceding claims, further comprising a gate for separating said at least one active region (10, 20) from said gate structures (CG1, FG1; . . . ; CGn, FGn) to selectively connect said at least one active region (10, 20) to said gate structures (CG1, FG1; . . . ; CGn, FGn) for programming or reading said gate structures (CG1, FG1; . . . ; CGn, FGn).

13. A method of operating the semiconductor memory device of at least one of claims 3 to 12, comprising the steps of: programming a gate structure (FG3, CG3) by supplying it with a programming voltage (Vpr) and by supplying the other gate structures (FG1, CG1; FG2, CG2; FG4, CG4) of the corresponding row with a select voltage (Vsel) which is greater than said programming voltage (Vpr).

14. A method of operating the semiconductor memory device of at least one of claims 3 to 12, comprising the steps of: programming a gate structure (FG3, CG3) by supplying it with a programming voltage (Vpr′) and by supplying the gate structures (FG1, CG1; FG2, CG2) of the corresponding row lying between said gate structure (FG3, CG3) and the active region (10) with a select voltage (Vsel) which is greater than said programming voltage (Vpr).

15. A method of operating the semiconductor memory device of at least one of claims 3 to 12, comprising the steps of: adjusting a charge quantity to be programmed under one of said gate structures (FG2, CG2); shifting said charge quantity to be programmed from said one of said gate structures (FG2, CG2) to another one of said gate structures (FG3, CG3); and programming said charge quantity to said another one of said gate structures (FG3, CG3).

16. A method of operating the semiconductor memory device of at least one of claims 3 to 12, comprising the steps of: adjusting a charge quantity to be programmed beneath a gate structure (FG3, CG3) to be programmed; and programming said charge quantity to said gate structure (FG3, CG3).

17. A method of operating the semiconductor memory device of at least one of claims 3 to 12, comprising the steps of: reading a gate structure (FG3, CG3) by supplying it with a read voltage (Vread) and by supplying the other gate structures (FG1, CG1; FG2, CG2; FG4, CG4) of the corresponding row with a select voltage (Vsel) which is greater than said read voltage (Vread) such that there is a static current flow (Is) between a first and second active region (10, 20) connected to the ends of said row; and sensing said static current flow (Is).

18. A method of operating the semiconductor memory device of at least one of claims 3 to 12, comprising the steps of: adjusting a charge quantity to be read under one of said gate structures (FG3, CG3) by supplying it with a read adjust voltage (Vreadad) and by supplying the gate structures (FG1, CG1; FG2, CG2) of the corresponding row lying between said gate structure (FG3, CG3) and the active region (10) with a select voltage (Vsel) which is greater than said read adjust voltage (Vreadad).

19. The method according to claim 18, wherein said charge quantity to be read is shifted from said one of said gate structures (FG3, CG3) to one of said active regions (10, 20) and sensed by a sense amplifier (SA) connected thereto.

20. A method of operating the semiconductor memory device of at least one of claims 3 to 12, comprising the steps of: applying an erase voltage (Ver) across at least one of said gate structures (CG1, FG1; . . . ; CGn, FGn) and said substrate (1).

21. A method of operating the semiconductor memory device of at least one of claims 3 to 12, comprising the steps of: multilevel programming said gate structures (CG1, FG1; . . . ; CGn, FGn).

22. A method of operating the semiconductor memory device of at least one of claims 3 to 12, comprising the steps of: adjusting a respective programming charge beneath a plurality of said gate structures (CG1, FG1; . . . ; CGn, FGn) to be programmed; and simultaneously programming said plurality of said gate structures (CG1, FG1; . . . ; CGn, FGn) by applying a programming. voltage (Vpr).

23. Use of the semiconductor memory device of at least one of claims 3 to 12 as a volatile memory.