This application claims priority to Taiwan Patent Document No. 103113160, filed on Apr. 10, 2014 with the Taiwan Patent Office, which is incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to a chip packaging structure, more particularly, to a chip packaging structure of lead frame packaging.
2. Description of the Prior Art
As the consumer market changes, consumer demands for lightness, thinness and small form factor for products are increasingly strong, especially for the electronic products, in which the capability to provide more functions, greater data capacity and faster processing speed within a limited volume is needed. However, in the semiconductor technology the integration density of chips are continuously upgraded due to the development of nanotechnology. Accordingly, higher density and pin counts are also requested for the semiconductor chip packaging. Therefore, the stacking and integration of the chips inside a package or the stacking of the packages are widely applied in many electronic devices. For example, in the dynamic random access memory (DRAM), flash memory, solid state drives (SSD), etc., can all find the application of chip stacking technology or package stacking technology (Package on Package, PoP) so as to increase the memory capacity. Furthermore, the package stacking technology can also be applied to the stacking of a memory chip package and a logic chip package.
Thus, either the chip stacking package or the stacking of packages is recently an important topic of research in this field.
One aspect of the present invention is to provide a chip packaging structure, in which two leadframe type semifinished products of Lead On Chip (LOC)/Chip On Lead (COL) are stacked together to form a package unit which are favorable for the stacking of the packages.
Another aspect of the present invention is to provide a chip packaging structure, which uses the attachment of the lead frames to combine two identical or different chips in a package unit so as to benefit the stacking of the packages.
Yet another aspect of the present invention is to provide a chip packaging structure, in which two lead frames are bonded to form a package unit with external contact points on both the top and bottom surfaces of the package unit so as to benefit the stacking of multiple packages.
An object of the present invention is to provide a chip packaging structure comprising an encapsulating material, a plurality of first leads, a first chip, a plurality of second leads, a second chip, and an adhesion layer. The encapsulating material has a top package surface and a bottom package surface opposite to the top package surface. Each of the first leads has a first inner lead and a first outer lead. The first leads are disposed in the encapsulating material. A first surface of the first outer leads is exposed on the top package surface. The first chip is disposed in the encapsulating material. The first chip is located on the first inner leads and electrically coupled to the first leads. Each of the second leads has a second inner lead and a second outer lead. The second leads are disposed in the encapsulating material. A second surface of the second outer leads is exposed on the bottom package surface. The second chip is disposed in the encapsulating material. The second chip is located on the second inner leads and electrically coupled to the second leads. The adhesion layer is disposed in the encapsulating material and located between the first leads and the second leads so that the first leads and the second leads are connected to each other.
Another object of the present invention is to provide an electronic device comprising a chip packaging structure and a circuit board. The chip packaging structure comprises an encapsulating material, a plurality of first leads, a first chip, a plurality of second leads, a second chip, and an adhesion layer. The encapsulating material has a top package surface and a bottom package surface opposite to the top package surface. Each of the first leads has a first inner lead and a first outer lead. The first leads are disposed in the encapsulating material. A first surface of the first outer leads is exposed on the top package surface. The first chip is disposed in the encapsulating material. The first chip is located on the first inner leads and electrically coupled to the first leads. Each of the second leads has a second inner lead and a second outer lead. The second leads are disposed in the encapsulating material. A second surface of the second outer leads is exposed on the bottom package surface. The second chip is disposed in the encapsulating material. The second chip is located on the second inner leads and electrically coupled to the second leads. The adhesion layer is disposed in the encapsulating material and located between the first leads and the second leads so that the first leads and the second leads are connected to each other. The chip packaging structure is disposed on the circuit board and electrically coupled to the circuit board through the second surface of the second outer leads.
For the chip packaging structure of the present invention, two leadframe type semifinished products of Lead On Chip (LOC)/Chip On Lead (COL) are stacked together to form a package unit which are favorable for the stacking of the packages. Moreover, in the invention the thickness of the inner leads is thinned to form a space for accommodating the chip so that the chip packaging structure can also be thinned.
The chip packaging structure of the present invention uses the attachment of the lead frames to combine two identical or different chips in a package unit so as to benefit the stacking of the packages, wherein by using the electrically conductive adhesive and/or the electrically non-conductive adhesive to bond the outer leads of the two lead frames, the outer leads can then be selectively electrically coupled to or electrically isolated from each other for some particular pins according to the requirements so that the circuit design and pin assignment of the chip packaging structure can be more flexible.
For the chip packaging structure of the present invention, two lead frames are bonded to form a package unit with external contact points on both the top and bottom surfaces of the package unit so as to benefit the stacking of multiple packages. Moreover, the stacked package structure can always have the external contact points on both the uppermost surface and the bottommost surface for additional connection to other devices such that the circuit design and pin assignment of the chip packaging structure are more flexible.
To facilitate understanding, identical reference numerals have been used, where it is possible to designate identical elements that are common to the figures.
In order to allow the advantages, spirit and features of the present invention to be more easily and clearly understood, the embodiments and appended drawings thereof are discussed in the following. However, the present invention is not limited to the embodiments and appended drawings.
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The structure of the bottom lead frame is similar to the foregoing structure but inverted. The bottom lead frame has a plurality of second leads 110. Each of the second leads 110 has a second inner lead 110A and a second outer lead 110B. Similarly, the thickness of the second inner leads 110A is smaller than the thickness of the second outer leads 110B so that a second accommodation space 130 is formed in the region of the second inner leads 110A. A second chip 112 is disposed in the second accommodation space 130 and located on the second inner leads 110A, which is also a Chip On Lead (COL) structure. The second chip 112 has a second active surface 112A and a second rear surface 128. The second chip 112 is attached to the second inner leads 110A with the second rear surface 112B, preferably by an insulating adhesive paste or an insulating tape (not shown). A plurality of contact points (not shown) are disposed on the second active surface 112A of the second chip 112 and are electrically coupled to the second leads 110 through the bonding wires 108 respectively, where the connection positions are preferably at the second inner leads 110A.
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In another embodiment of the present invention, the first chip 106 and the second chip 112 can be different kinds of chips. For example, the first chip 106 is a memory chip, while the second chip 112 is a logic chip. Therefore, a portion of the contacts of the first chip 106 requires independent input or output, and a portion of the contacts of the second chip 112 also requires independent input or output. As shown in
Next, an encapsulation process is conducted to cover the two lead frames with the chips which are attached to each other so that the encapsulating material 102 covers the first chip 106, the second chip 112, the bonding wires 108, the first inner leads 104A, the second inner leads 110A, part of the first outer leads 104B, and part of the second outer leads 110B and exposes a first surface 104C of the first outer leads 104B and a second surface 110C of the second outer leads 110B. The material of the encapsulating material 102 can be an epoxy resin or other suitable insulating material. The encapsulating material 102 has a top package surface 102A and a bottom package surface 102B opposite to the top package surface 102A. The first surface 104C of the first outer leads 104B is exposed on the top package surface 102A, and the second surface 110C of the second outer leads 110B is exposed on the bottom package surface 102B. The subsequent sawing/punching process of the lead frame or the packaging structure, the dejunk/deflash process, and the electroplating process of the leads are similar to the prior art, and hence are not discussed in detail herein.
The first surface 104C and the second surface 110C serve as the external contact points of the first leads 104 and the second leads 110 respectively so that the chip packaging structure 100 can further be stacked with other packaging structures or connected to other devices such as the circuit board. As described in the embodiment above, at some pin locations where the first leads 104 and the second leads 110 are electrically connected to each other by the adhesion layer 114, either the first surface 104C or the second surface 110C can be selected to serve as the external contact points. It is worth mentioning that some leads of a particular lead frame can be electrically unconnected to the chip located thereon in some embodiments. For example, one of the first leads 104 can be a dummy lead for the first chip 106, namely that it is not electrically coupled to the first chip 106 but is electrically coupled to one of the second leads 110 by the adhesion layer 114, so that the pin can connect to other packages and/or the circuit board(s) via the first surface 104C and the second surface 110C respectively. In other words, some contact point of the second chip 112 can be connected to external devices through the second lead 110 and/or the first lead 104, so that pin assignments can be more flexible.
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To summarize the chip packaging structure of the present invention, two leadframe type semifinished products of Lead On Chip/Chip On Lead are stacked together to form a package unit which are favorable for the stacking of the packages. Moreover, in the invention the thickness of the inner leads is thinned to form a space for accommodating the chip so that the chip packaging structure can also be thinned. The chip packaging structure of the present invention uses the attachment of the lead frames to combine two identical or different chips in a package unit so as to benefit the stacking of the packages, wherein by using the electrically conductive adhesive and/or the electrically non-conductive adhesive to bond the outer leads of the two lead frames, the outer leads can then be selectively electrically coupled to or electrically isolated from each other for some particular pins according to the requirements, or can be selectively electrically coupled to the chips so that the circuit design and pin assignment of the chip packaging structure can be more flexible. Furthermore, for the chip packaging structure of the present invention, two lead frames are bonded to form a package unit with external contact points on both the top and bottom surfaces of the package unit so as to benefit the stacking of multiple package units. Therefore, the stacked package structure always has the external contact points on both the uppermost surface and the bottommost surface for additional connection to other devices such that the circuit design and pin assignment of the chip packaging structure are more flexible.
With the examples and explanations mentioned above, the features and spirits of the invention are hopefully well described. More importantly, the present invention is not limited to the embodiment described herein. Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Number | Date | Country | Kind |
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103113160 | Apr 2014 | TW | national |