Patent Application
20210215749
The present disclosure relates to semiconductor circuits and more specifically to circuits for detecting and recording events of electrical overstress and/or electrical static discharge and methods of manufacturing the same.
Semiconductor circuit/components may be damaged by electrical overstress (EOS) and/or electrical static discharge (ESD). After damage occurs, however, determining the cause as EOS or ESD can be difficult. It is in this context that implementations of the disclosure arise.
In at least one aspect, the present disclosure generally describes a circuit for recording an electrical event. The circuit includes a spark-gap circuit with at least one metal trace that defines at least one spark gap. The at least one spark gap is configured to conduct a signal during the electrical event. The circuit also include a recording device that is coupled to the spark-gap circuit and is configured to have an electrical property that is altered by the signal conducted during the electrical event. The circuit also includes a diagnostic port that is configured to provide electrical access to the recording device for an electrical test of the electrical property that was altered by the signal during the electrical event.
In one possible implementation, the circuit is directly coupled to an input/output (I/O) port of an internal circuit to monitor the electrical event at the I/O of the internal circuit. For example, the electrical event may be an electrostatic discharge (ESD) at the I/O port of the internal circuit or an electrical over stress (EOS) on the internal circuit.
In another aspect, the present disclosure generally describes a method for diagnosing damage to an internal circuit. In the method a signal is received at an input/output port of the internal circuit. The signal is also received at a spark-gap circuit, which includes at least one metal trace defining at least one spark gap, and which is coupled to the input/output port. The method includes conducting the signal through the at least one spark gap during an electrical event (e.g., ESD, EOS). The method further includes receiving the signal conducted by the at least one spark gap at a recording device coupled to the spark-gap circuit, where the recording device is configured to have an electrical property altered by the conducted signal. The method further includes coupling test equipment to a diagnostic port of the recording device and performing an electrical test on the recording device to determine the electrical property altered by the conducted signal. Based on the results of the electrical test, the damage to the internal circuit is diagnosed.
In one possible implementation of the method the at least one spark gap is a plurality of spark gaps that are each configured to couple a signal of a different amplitude. In this implementation, the method may further include visually inspecting the plurality of spark gaps to determine which spark gap (or spark gaps) of the plurality coupled the signal during the electrical event. The one or more determined spark gaps can then be correlated with a signal amplitude in order to determine an amplitude of the signal during the electrical event (or events).
In another possible implementation of the method, the recording device is a transistor; the electrical property that is altered by the conducted signal is a threshold voltage of the transistor; and the electrical test performed on the transistor is a measurement of the threshold voltage of the transistor.
In another possible implementation of the method, the recording device is a field-effect device; the electrical property that is altered by the conducted signal is a capacitance or an inductance of the field-effect device; and the electrical test performed on the field-effect device is a measurement of the capacitance or the inductance of the field-effect device.
In another possible implementation of the method, the recording device is a resistor; the electrical property that is altered by the conducted signal is a resistance of the resistor; and the electrical test performed on the resistor is a measurement of the resistance of the resistor.
In another possible implementation of the method, a control device that is substantially equivalent to the recording device is provided. The control device does not receive a signal from the spark-gap circuit during the electrical event. According, test equipment may be coupled to a control-diagnostic port of the control device so that an electrical test may be performed on the control device to determine an electrical property of the control device. The electrical property of the control device is then compared to the electrical property of the recording device altered by the conducted signal, and the damage to the internal circuit may be diagnosed based on the comparison.
In another aspect, the present disclosure generally describes a semiconductor device that includes an internal circuit having an input/output port. The semiconductor device further includes an event-recording circuit that is configured to record an electrical event at the input/output port of the internal circuit to facilitate diagnosis of damage to the internal circuit. The event-recording circuit includes a spark-gap circuit, a recording device, and a diagnostic port. The spark-gap circuit includes at least one metal trace that defines at least one spark gap. The at least one spark gap is an air-gap structure encapsulated by an inorganic dielectric that is configured to conduct a signal during the electrical event. The recording device is coupled to the at least one spark gap and is configured to have a property that is altered by the signal. The diagnostic port is configured to provide access to the recording device for a test of the property altered by the signal.
The foregoing illustrative summary, as well as other exemplary objectives and/or advantages of the disclosure, and the manner in which the same are accomplished, are further explained within the following detailed description and its accompanying drawings.
The components in the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding parts throughout the several views.
The present disclosure describes a circuit for recording an electrical event (i.e., an event-recording circuit). When the event-recording circuit is coupled to an input/output (I/O) port of an internal circuit (e.g., an integrated circuit) then the event-recording circuit may be used to record one or more electrical events at the input/output port. Further, in some implementations the recording provided by the event-recording circuit (i.e., the recording) may be able to provide information regarding the severity of the ESD events or the EOS events. Accordingly, the recording may provide information including (but not limited to) whether or not an electrical event has occurred, how many times the electrical event has occurred, and the severity of the electrical event (or events). This information can be used to interpret (i.e., conclude) electrical conditions experienced by the internal circuit. For example, the recording can provide a historic record of the electrical conditions experienced by the internal circuit. This historic record may provide information that can be used for a variety of purposes related to the service of the internal circuit. For example, the recording may help diagnose a cause of a malfunction or damage to the internal circuit. This diagnosis may be used to service the internal circuit or may be used to gain information helpful for future designs and/or specifications of the internal circuit.
The electrical events at the I/O port 101 generally include signals that cause electrical stress on the internal circuit. The electrical stress may be an electrical over stress (EOS) in which a signal (e.g., a voltage) is outside an operating range of the internal circuit. The EOS may occur for a period, which may be short, long, periodic, transient, or continuous, causing damage resulting from excess power dissipated in the internal circuit in the form of heat. One type of EOS that is severe in amplitude and transient in nature is electro-static discharge (ESD) that can be caused from a static discharge at the I/O port 101. EOS is a common failure in semiconductor circuits (i.e., integrated circuits). When a device 100 (e.g., semiconductor device) is returned to a vendor for failure, often EOS is the cause. Diagnosing EOS as the cause of the failure, however, can be difficult. Accordingly, it may be desirable to detect and record one or more electrical events (e.g., EOS events, ESD events) at the I/O port 101 of the internal circuit 110.
The device 100 further includes an event-recording circuit 200 that is configured to detect and record one or more electrical events at the I/O port 101 of the internal circuit 110. The event recording circuit is coupled to the I/O port 101 and is configured to monitor the signals to and from the internal circuit 110. When a signal at the I/O port reaches a condition corresponding to an electrical event, the event-recorded circuit 200 is configured to receive the signal and is altered by the signal. The event recording circuit 200 may include one or more diagnostic ports 102 (i.e., test ports, monitoring ports) in which the event-recording circuit can be accessed (e.g., by electrical test equipment) to obtain the recorded information.
In some implementations, the device 100 may include a bias circuit 120 that is configured to provide an electrical signal (e.g., voltage, current) to condition the operation of the event recording circuit 200. For example, the condition corresponding to an electrical event may correspond to a bias signal (e.g., a voltage) applied to the event-recording circuit 200 by the bias circuit 120. The device 100 may further include an ESD/EOS protection circuit 130. The ESD/EOS protection circuit 130 may be coupled to the I/O port 101 of the device (e.g., coupled in parallel with the event-recording circuit 200) and may be configured to couple (i.e., short circuit) an ESD/EOS signal to ground to prevent it from reaching the internal circuit 110. The threshold at which the ESD/EOS protection circuit 130 couples the ESD/EOS signal to ground may be adjusted to be greater than the threshold at which the ESD/EOS signal is coupled to event recording circuit 200 so that an increasing ESD/EOS signal is recorded by the event-recording circuit 200 before being shorted to ground by the ESD/EOS protection circuit 130. Alternatively, the threshold at which the ESD/EOS signal is coupled to event recording circuit 200 may be higher than the threshold at which the ESD/EOS protection circuit 130 couples the ESD/EOS signal to ground so that the recording circuit does not record until the ESD/EOS protection circuit 130 ceases to protect the internal circuit from an electrical event.
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The diagnostic port may be other than electrical port described above. For example, the diagnostic port 201 can a port for a visual inspection. Further, the diagnostic port for visual inspection may include or may be exclusively directed to the spark-gap circuit 210. In these implementations, the diagnosis port may facilitate a visual inspection of the spark-gap circuit 210 and/or the recording device 260 for damage and/or discoloration. This visual inspection may include optical viewing devices (e.g., magnifying optics) and/or optical recording devices (e.g., camera). The damage and/or discoloration information obtained through the visual inspection that the spark-gap circuit 210 has experienced one or more electrical events.
The spark-gap circuit 210 includes at least one spark gap. A spark gap includes a first electrode (i.e., conductor, trace) and a second electrode (i.e., conductor, trace) separated by a gap-width. An electric spark may pass between the first electrode and the second electrode when a voltage exists between the first electrode and the second electrode that is higher than a breakdown voltage (i.e., trigger voltage) of the gap-width. The breakdown voltage of the spark-gap may correspond to the gap-width so that a larger gap-width has a larger breakdown voltage than a smaller gap-width.
The spark gap may be an air-gap structure in which no material fills the gap-width between the first electrode and the second electrode. Further, the air-gap structure may be encapsulated. An encapsulated-air-gap structure can allow for a vacuum to be created in the gap-width between the first electrode and the second electrode. The vacuum created may be characterized by a pressure level that is less than an ambient pressure level (e.g., in a range from 1 milli-Torr to 100 milli-Torr). The breakdown voltage of the spark-gap may further correspond to the pressure level of the vacuum in the gap-width so that a lower-pressure vacuum has a higher breakdown voltage than a higher-pressure vacuum. The spark-gap circuit 210 may include multiple spark gaps implemented as encapsulated air-gap structures to provide multiple breakdown voltages or to create an overall breakdown voltage for the spark-gap circuit that is higher than provided by a single encapsulated air-gap structure.
The spark-gap circuit 210 may include multiple spark gaps arranged in various configurations.
A spark-gap circuit 210 may be fabricated as a metallic (e.g., Al, Cu, W, TiN, doped poly-Si) circuit trace or circuit traces. The material of the metal trace may be chosen based on a melting point, which can correspond to a current carrying capability of the trace. The circuit trace or traces a disposed on a substrate using photolithographic and chemical processing steps associated with semiconductor processing.
In another possible implementation the parallel-connected spark gaps each have the same gap-width. In other words, the spark-gap circuit may include a plurality of redundant spark gaps. One of the redundant spark gaps (i.e., a first spark gap) may be triggered during a first electrical event. Subsequently a second spark gap of may be triggered during a second electrical event. In this way multiple electrical events can be accommodated. Further, a visual examination of the redundant spark gaps for damage may reveal the number of electrical events experienced because each electrical event damages one of the redundant spark gaps.
The recording device 260 of the event-recording circuit 200 may be implemented variously.
When an electrical event occurs, the transistor may experience a voltage at the gate terminal that is large enough to affect (e.g., irreversibly affect) the operation of the transistor. In other words, a change (e.g., a non-transitory change, a permanent change, a non-volatile change, a long-term change, etc.) in the electrical property of the transistor can be caused (i.e., created, generated) by the signal conducted by the spark-gap circuit 210 during the electrical event. In a subsequent electrical test of the transistor, the test equipment can be coupled to the first terminal 201a and the second terminal 201b to measure the electrical property. For example, in one possible implementation a gate-oxide leakage current of the transistor may be measured. In another possible implementation, a threshold voltage of the transistor may be measured. The measured values may be compared to a baseline value (e.g., determined prior to use) to determine a change. The determined change can indicate that an electrical event has occurred and, in some cases, can correspond to the severity of an electrical event and/or a cumulative history of events.
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Based on the change in resistance, it may be concluded that an electrical event (e.g., an EOS/ESD event) has occurred, which may be used for diagnosing damage to the internal circuit. Further, an amount of the change in resistance may correlate with a severity of an electrical event and/or a cumulative history of multiple electrical events.
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As mentioned previously, the spark gap may be fabricated as an encapsulated air-gap structure (i.e., air-gap). Encapsulating the air-gap using an inorganic dielectric, such as SiO2, SiON, or SiN, can hermetically seal the air-gap from an outside environment (e.g., humidity, pressure, etc.). The inorganic dielectric encapsulation may have advantage over other encapsulation approaches (e.g., encapsulation using an organic material) because its ability to seal the air-gap from pressure or moisture changes, either of which can affect the trigger voltage for the air-gap. A trigger voltage for the air-gap that is stable in various environments can facilitate accurate measurements of electrical events.
The fabrication of the air-gap structure can use a semiconductor processes, including (but not limited to) deposition, photolithography, chemical etching, and the like. A variety of process flows may be used to form an encapsulated air-gap structure. It may be desirable to select a process flow for fabricating the encapsulating air-gap structure that matches the process flow used for fabricating the internal circuit 110 and/or event recording circuit 200 so that all these elements may be included in the same semiconductor device 100. In other words, forming a spark gap with no additional processing (other than already employed) or minimal additional processing may be desirable. In what follows, details regarding possible fabrication process flows for fabricating encapsulated air-gaps are presented. For the possible fabrication process flows presented, there may be a tradeoff between simplicity and size. For example, a process flow requiring fewer processing may require more area for the air-gap structure.
One possible process flow that can be used for fabricating an encapsulated air-gap structure includes forming metal traces (i.e., conductors, wires) in a dielectric, masking and etching the dielectric to form air-gaps and depositing a non-conformal dielectric over the air-gaps to encapsulate (i.e. seal, pinch-off) the air-gaps. For the non-conformal dielectric to seal the air-gap the gap width is be small (e.g., ≤0.2 microns). In some cases, after the air-gaps are etched and before the non-conformal dielectric is deposited, the surfaces of the structure are stripped and cleaned, and a conformal passivation layer is deposited on the surfaces. The dimensions of the air-gap may be controlled by the process. In some implementations, the air-gap has a lateral width that is smaller than the lateral width of the electrodes, while in other implementations the lateral width of the air-gap can be the same or larger than the lateral width of the electrodes.
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It may be desirable to use or adapt a wafer-bonding process to create an air-gap structure. For example, some applications, such as images sensors (e.g., a back-side illumination image sensor) may use this process.
While various process flows have been presented variations may exist that do not depart from the scope of the disclosure, which presents spark gaps that can be fabricated with little or no additional processing in a process flow for a semiconductor device. For example, the novel approach of adapting tungsten vias (i.e., via bars) as spark gap electrodes can be used to create an air-gap structure that can be encapsulated with an organic material. For example, a mold compound (e.g., from the package housing) of a semiconductor device may be adapted to encapsulate the air-gap structure. The organic sealing material may be more permeable to an environment than the inorganic sealing materials described thus far but can be used in certain situations (e.g., for cost efficiency). In another example, the process flows may result in air-gaps having virtually any shape, including (but not limited to) rectangular, circular, triangular, and the like.
The disclosure provides an event-recording circuit that can monitor and record ESD/EOS events. The event-recording circuit can simplify and aid failure analysis (FA) of an internal circuit. For example, the FA of a customer return of the internal circuit can be simplified and FA information may be provided that helps determine if the internal circuit (i.e., the part) was operated outside of its specification limits. This determination may further help determine a business decision, such as whether to replace the part free of charge. The spark gap minimizes parasitic effects (e.g., current leakage, parasitic capacitance) on an I/O port because a recording device is not coupled to the circuit until an electrical event (e.g., ESD/EOS event) occurs. Further, the spark gap may not require any power consumption to perform this trigger voltage operation. The use of the spark gap provides versatility in the recording device design. For example, very simple recording device components and topologies may be used (e.g., see
In the specification and/or figures, typical embodiments have been disclosed. The present disclosure is not limited to such exemplary embodiments. The use of the term “and/or” includes any and all combinations of one or more of the associated listed items. The figures are schematic representations and so are not necessarily drawn to scale. Unless otherwise noted, specific terms have been used in a generic and descriptive sense and not for purposes of limitation.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. Methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present disclosure. As used in the specification, and in the appended claims, the singular forms “a,” “an,” “the” include plural referents unless the context clearly dictates otherwise. The term “comprising” and variations thereof as used herein is used synonymously with the term “including” and variations thereof and are open, non-limiting terms. The terms “optional” or “optionally” used herein mean that the subsequently described feature, event or circumstance may or may not occur, and that the description includes instances where said feature, event or circumstance occurs and instances where it does not. Ranges may be expressed herein as from “about” one particular value, and/or to “about” another particular value. When such a range is expressed, an aspect includes from the one particular value and/or to the other particular value. Similarly, when values are expressed as approximations, by use of the antecedent “about,” it will be understood that the particular value forms another aspect. It will be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint.
Some implementations may be implemented using various semiconductor processing and/or packaging techniques. Some implementations may be implemented using various types of semiconductor processing techniques associated with semiconductor substrates including, but not limited to, for example, Silicon (Si), Gallium Arsenide (GaAs), Gallium Nitride (GaN), Silicon Carbide (SiC) and/or so forth.
While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the implementations. It should be understood that they have been presented by way of example only, not limitation, and various changes in form and details may be made. Any portion of the apparatus and/or methods described herein may be combined in any combination, except mutually exclusive combinations. The implementations described herein can include various combinations and/or sub-combinations of the functions, components and/or features of the different implementations described.
