Claims
- 1. A programmable logic device comprising an array of logic blocks, each logic block having at least one circuit comprising:
- an input terminal for providing a first input signal (A.sub.i);
- a ripple-in terminal (C.sub.i) and a ripple-out terminal (C.sub.i+1);
- a ripple-chain multiplexer (923) for connecting one of said input terminal and said ripple-in terminal to said ripple-out terminal;
- a lookup table (903) for generating a function of said first input signal and at least one other input signal; and
- a control multiplexer (804) for controlling said ripple-chain multiplexer, said control multiplexer being controlled to select from at least two input signals, one of said signals being provided by said lookup table.
- 2. A programmable logic device comprising an array of logic blocks, each logic block having at least one circuit comprising:
- an input terminal for providing a first input signal (A.sub.i);
- an input select multiplexer (801) for providing one of said first input signal and another signal (802) as an output of said input select multiplexer;
- a ripple-in terminal (C.sub.i) and a ripple-out terminal (C.sub.i+1);
- a ripple-chain multiplexer (923) for connecting one of said output of said input select multiplexer and said ripple-in terminal to said ripple-out terminal;
- a lookup table (903) for generating a signal which can control said ripple-chain multiplexer.
CONTINUATION INFORMATION
This is a continuation-in-part of U.S. patent application Ser. No. 08/116,659 filed Sep. 2, 1993, issued as U.S. Pat. No. 5,349,250 on Sep. 20, 1994.
US Referenced Citations (12)
Non-Patent Literature Citations (1)
Entry |
Xilinx Programmable Gate Array Data Book, 1989, pp. 6-30 through 6-44, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124. |
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
116659 |
Sep 1993 |
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