Claims
- 1. A clock generation circuit for an analog delay circuit which includes an analog memory circuit including a plurality of memory cells each including a switch element having a first terminal connected to a corresponding row line and a memory capacitor connected to a second terminal of said switch element, said memory cells being arranged in a matrix of u columns and v rows, u and v being natural numbers, a first scanning circuit for successively outputting u column selection signals to drive the switch elements of said memory cells for the individual columns, and a second scanning circuit for successively outputting v row selection signals to drive the switch elements of said memory cells for the individual rows, said clock generation circuit supplying a same clock signal to said first and second scanning circuits, said clock generation circuit comprising:
- a logic operation circuit for logically operating one of the column selection signals of said first scanning circuit and one of the row selection signals of said second scanning circuit;
- a phase comparator for comparing a phase of an output signal of said logical operation circuit and a phase of a reference signal provided from the output with each other; and
- a voltage controlled oscillator for receiving a comparison output of said phase comparator as a control input for an oscillation frequency and supplying a clock signal of the oscillation frequency commonly to said first and second scanning circuits.
- 2. The clock generation circuit according to claim 1, wherein said first scanning circuit includes u stages of shift registers, and said second scanning circuit includes v stages of shift registers.
- 3. The clock generation circuit according to claim 1, wherein said phase comparator compares a phase of an output signal of said logical operation circuit and a phase of a horizontal synchronizing signal of a video signal with each other.
Priority Claims (2)
Number |
Date |
Country |
Kind |
P08-057299 |
Mar 1996 |
JPX |
|
P08-062255 |
Mar 1996 |
JPX |
|
Parent Case Info
This application is a divisional of application Ser. No. 08,808,866 filed Feb. 28, 1997.
US Referenced Citations (3)
Divisions (1)
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Number |
Date |
Country |
Parent |
808866 |
Feb 1997 |
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