CLOCK SIGNAL GENERATING CIRCUIT

Abstract

Each of identically configured logic inverter circuits 10a, 10b, 10c, and 10d comprises a PMOS transistor MP1 (abbreviated as MP1 hereinafter), and NMOS transistors MN1 and MN2 (abbreviated as MN1 and MN2 hereinafter). Gates of MP1 and MN1 are connected to input terminal IN1, gate of MN2 is connected to input terminal IN2, drains of MP1 and MN1 are connected to an output terminal OUT, source of MN1 is connected to the drain of MN2, source of MP1 is connected to a controllable power supply VC, and source of MN2 is grounded. Input terminals IN1 and IN2 of logic inverter circuits 10a, 10b, 10c, and 10d are connected to output terminals OUT of the logic inverter circuits 10b and 10c, 10c and 10d, 10d and 10a, and 10a and 10b respectively. High-speed four-phase clock signals are generated.

Description

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1 is a circuit diagram of a clock signal generating circuit relating to a first example of the present invention.

FIG. 2 is a timing chart illustrating the operation of the clock signal generating circuit relating to the first example of the present invention.

FIG. 3 is a circuit diagram of a clock signal generating circuit relating to a second example of the present invention.

FIG. 4 is a circuit diagram of a clock signal generating circuit relating to a third example of the present invention.

FIG. 5 is a circuit diagram of a voltage-controlled oscillator circuit in which a conventional three-stage ring oscillator and a frequency divider circuit are combined.

FIG. 6 is a timing chart of signals generated by a conventional voltage-controlled oscillator circuit, as analyzed by the present invention.

Claims

1. A clock signal generating circuit comprising: first to fourth logic inverter circuits; whereinsaid first to fourth logic inverter circuits are respectively connected between first and second power supplies, and respectively comprise first and second input terminals and an output terminal;said output terminal is at a second level when said first input terminal is at a first level, with said output terminal being at the first level when said first and second input terminals are at the second level, in each of said logic inverter circuits; andfirst input terminals of said first to fourth logic inverter circuits are connected to output terminals of said second, third, fourth, and first logic inverter circuits respectively, and second input terminals of said first to fourth logic inverter circuits are connected to output terminals of said third, fourth, first, and second logic inverter circuits respectively.

2. The clock signal generating circuit as defined in claim 1, wherein each of said first to fourth logic inverter circuits comprises a first MOS transistor of a first conductivity type and first and second MOS transistors of a second conductivity type;a gate of said first MOS transistor of the first conductivity type and a gate of said first or second MOS transistor of the second conductivity type being connected to said first input terminal; a gate of the other MOS transistor of the second conductivity type being connected to said second input terminal; a drain of said first MOS transistor of the first conductivity type and a drain of said first MOS transistor of the second conductivity type being connected to said output terminal; a source of said first MOS transistor of the second conductivity type being connected to a drain of said second MOS transistor of the second conductivity type; a source of said first MOS transistor of the first conductivity type being connected to said first power supply; and a source of said second MOS transistor of the second conductivity type being connected to said second power supply.

3. The clock signal generating circuit as defined in claim 2 wherein each of said first to fourth logic inverter circuits further comprises: a second MOS transistor of the first conductivity type having its source connected to the source of said first MOS transistor of the first conductivity type, its drain connected to the drain of said first MOS transistor of the first conductivity type, and its gate connected to said second input terminal.

4. A clock signal generating circuit comprising: first to fourth two-input NAND circuits connected between first and second power supplies; whereinone of input terminals of each of said first to fourth two-input NAND circuits is connected to an output terminal of said second, third, fourth, and first two-input NAND circuits respectively, and the other input terminal of each of said first to fourth two-input NAND circuits is connected to an output terminal of said third, fourth, first, and second two-input NAND circuits respectively.

5. The clock signal generating circuit as defined in claim 4 wherein said two-input NAND circuits are replaced by two-input NOR circuits.

6. A voltage-controlled oscillator circuit comprising the clock signal generating circuit as defined in claim 1 wherein the oscillation frequency of clock signals generated is varied by controlling a voltage between said first and second power supplies.

7. A voltage-controlled oscillator circuit comprising the clock signal generating circuit as defined in claim 2 wherein the oscillation frequency of clock signals generated is varied by controlling a voltage between said first and second power supplies.

8. A voltage-controlled oscillator circuit comprising the clock signal generating circuit as defined in claim 3 wherein the oscillation frequency of clock signals generated is varied by controlling a voltage between said first and second power supplies.

9. A voltage-controlled oscillator circuit comprising the clock signal generating circuit as defined in claim 4 wherein the oscillation frequency of clock signals generated is varied by controlling a voltage between said first and second power supplies.

10. A voltage-controlled oscillator circuit comprising the clock signal generating circuit as defined in claim 5 wherein the oscillation frequency of clock signals generated is varied by controlling a voltage between said first and second power supplies.