This invention relates to an advanced lithography system to gain high throughput and high resolution in semiconductor lithography practice. More specifically, embodiments of the present invention provide a hybrid system that combines optical and e-beam lithography (EBL) system to achieve the object. Merely by way of example, the present invention has been used onto smallest feature lithograph such as gate, AA and contact, but it would be recognized that the invention has a much broader range of applicability.
Fabrication of semiconductor device such as logic and memory device may include processing wafer through various semiconductor processing tools. As feature size continuous shrink from 45 nm to 32 nm, conventional high throughput optical lithography system does not have high enough resolution for sub 32 nm nodes. The conventional e-beam lithography system has high resolution but has very low throughput during lithography practice.
Therefore, an improved system to achieve both high resolution and high throughput is desired.
This invention relates to an advanced lithography system to gain high throughput and high resolution in semiconductor lithography practice. More specifically, embodiments of the present invention provide a hybrid system that combines optical and e-beam lithography system to achieve the object. Merely by way of example, the present invention has been used onto smallest feature lithograph such as gate, AA and contact, but it would be recognized that the invention has a much broader range of applicability.
An object of the present invention is to provide a hybrid lithography system that combines one optical lithographer to expose larger pattern area and a cluster e-beam lithography system to expose pattern area where request higher resolution.
This invention relates to an advanced lithography system to gain high throughput and high resolution in semiconductor lithography practice. More specifically, embodiments of the present invention provide a hybrid system that combines optical and e-beam lithography system to achieve the object. Merely by way of example, the present invention has been used onto smallest feature lithograph such as gate, AA and contact, but it would be recognized that the invention has a much broader range of applicability.
As explained above, the e-beam lithographer is characterized with high resolution and low throughput; the optical lithographer has high throughput but not high enough resolution for sub 32 nm nodes in a semiconductor device. Moreover, a hybrid system with a cluster e-beam lithography system and an optical lithography system can take advantages of both. More specifically, the cluster e-beam lithography system exposes for small features and the optical lithography system exposes for larger patterns.
Under 35 USC §120, this application is a Non-Provisional application and is related to co-pending U.S. Patent Application Ser. No. 60/983130, filed on Oct. 26, 2007, entitled “CLUSTER E-BEAM LITHOGRAPHY SYSTEM”; to U.S. Patent Application Ser. No. 61/044633, filed on Apr. 14, 2008, entitled “CLUSTER E-BEAM LITHOGRAPHY SYSTEM”, all of which are incorporated herein by reference.
Number | Date | Country | |
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60983130 | Oct 2007 | US | |
61044633 | Apr 2008 | US |