Mechanical stress control in the channel regions of metal-oxide semiconductor field-effect transistors (MOSFETs) enables overcoming the limitations incurred in the scaling down of devices.
U.S. Pat. No. 6,284,610 B1 to Cha et al. describes a poly layer to reduce stress.
U.S. Pat. No. 6,281,532 B1 to Doyle et al. describes processes to change the localized stress.
U.S. Pat. No. 5,562,770 to Chen et al. describes a process for global stress modification by forming layers or removing layers from over a substrate.
U.S. Pat. No. 5,834,363 to Masanori describes a method for global stress modification by forming layers from over a substrate.
The J. Welser et al. Strain Dependence of the Performance Enhancement in Strained-Si n-MOSFETs, IEDM Tech. Dig., pp. 373–376, 1994 article discloses measurements of the strain dependence of the electron mobility enhancements in n-MOSFETs employing tensilely-strained Si channels.
The K. Rim et al. Strained Si NMOSFET's for High Performance CMOS Technology, VLSI Tech., pp. 59 and 60, 2001 article describes performance enhancements in strained Si NMOSFET's at Leff<70 nm.
The F. Ootsuka et al. A Highly Dense, High-Performance 130 nm node CMOS Technology for Large Scale System-on-a-Chip Applications, IEDM Tech. Dig., pp. 575–578, 2000 article describes a 130 nm node CMOS technology with a self-aligned contact system.
The Shinya Ito et al. Mechanical Stress Effect of Etch-Stop Nitride and its Impact on Deep Submicron Transistor Design, IEDM Tech, Dig.; pp. 247–250, 2000 article describes process-induced mechanical stress affecting the performance of short-channel CMOSFET's.
The A. Shimizu et al. Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement, IEDM Tech. Dig., pp. 433–436, 2001 article describes a “local mechanical-stress control” (LMC) technique used to enhance the CMOS current drivability.
Accordingly, it is an object of one or more embodiments of the present invention to provide a MOS/CMOS device having different stresses on at least two different areas, and methods of fabricating the same.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a structure having at least an adjacent NMOS device and PMOS device is provided. A first stress layer is formed over the PMOS device and a second stress layer is formed over the NMOS device whereby the mobility of holes and electrons within the structure is improved. A semiconductor device comprising: at least one NMOS device; at least one PMOS device adjacent the at least one NMOS device; a first stress layer overlying the at least one PMOS device with the first stress layer having a first stress characteristic; and a second stress layer overlying the at least one NMOS device with the second stress layer having a second stress characteristic.
The present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements, regions and portions and in which:
Information Known to the Inventors—Not to be Considered Prior Art
The following information is known to the inventors and is not to be necessarily considered prior art for the purposes of this invention.
Changing the Si lattice spacing to a value other than the equilibrium value by using mechanical stress can increase the mobility of holes and electrons. This has been demonstrated in a strained-silicon (Si) MOSFET which applied high biaxial tensile stress to the channel of MOSFETs. However, the fabrication of strained-Si MOSFETs involves complicated processes such as forming a relaxed SiGe buffer layer. A recent study has shown that mechanical stress from a contact etch stop silicon nitride (SiN) layer affects the drive current.
Initial Structure—
An isolation device 11 may be formed within structure 10 between adjacent NMOS/PMOS devices 16, 18. Structure 10 may be a silicon substrate or a silicon-germanium substrate, for example, and isolation device 11 may be, for example, a shallow trench isolation (STI) device.
The NMOS devices(s) 16 comprise a respective electrode 20 and sidewall spacers 22, source/drain (S/D) implants (not shown) and a gate oxide layer 21. The PMOS devices(s) 18 comprise a respective electrode 30 and sidewall spacers 32, source/drain (S/D) implants (not shown) and a gate oxide layer 31. The respective gate oxide layers 21, 31 each have a thickness of preferably from about 6 to 100 Å and more preferably less than about 17 Å.
An NMOS device channel and a PMOS device channel may be formed (not shown). The respective device channels each have a design width of preferably from about 0.05 to 10.0 μm, more preferably less than about 10.0 μm and most preferably less than about 0.5 μm.
The operation voltage design is preferably from about 0.6 to 3.3 volts (V) and is more preferably less than about 1.2 V.
Structure 10 is preferably a silicon substrate or a germanium substrate, is more preferably a silicon substrate and is understood to possibly include a semiconductor wafer or substrate.
A first stress layer 40 is formed over structure 10, NMOS devices(s) 16 and PMOS device(s) 18 to a thickness of preferably from about 200 to 700 Å. First stress layer 40 may be either a tensile-stress layer or a compression-stress layer as described below.
An etch stop layer 42 is formed over the first stress layer 40 to a thickness of preferably from about 200 to 700 Å and more preferably from about 250 to 500 Å. Etch stop layer 42 is preferably comprised of oxide, silicon oxide (SiO2) or SiON and is more preferably comprised of oxide or silicon oxide.
A first patterning layer 46 is formed at least over either the NMOS device 16 and adjacent thereto or, as shown in
Patterning of the Etch Stop Layer 42 and the First Stress Layer 40—
As shown in
As one skilled in the art would understand now or hereafter, the first patterning layer 46 may not necessarily be needed to pattern the etch stop layer 42 and the first stress layer 40 as long as the etch stop layer 42 and the first stress layer 40 are patterned/etched as shown in
Formation of Second Stress Layer 50—
As shown in
A second stress layer 50 is formed over structure 10, NMOS device 16 and over patterned etch stop layer 42′ that overlies at least PMOS device 18 and adjacent thereto to a thickness of preferably from about 200 to 700 Å. Second stress layer 50 is (1) a tensile-stress layer if the patterned first stress layer 40′ is comprised of a tensile-stress layer and is a (2) a tensile-stress layer is the patterned first stress layer 40′ is comprised of a compression-stress layer.
As shown in
Patterning of the Second Stress Layer 50—
As shown in
As one skilled in the art would understand now or hereafter, the second patterning layer 48 may not necessarily be needed to pattern the second stress layer 50 et al. as long as the second stress layer 50 et al. are patterned/etched as shown in
Removal of the Second Patterning Layer 48—
As shown in
Formation of Tensile-stress Layers and Compression-stress Layers
As noted above, the first stress layer 40 may be either a tensile-stress layer or a compression-stress layer while the second stress layer 50 is a tensile-stress layer. That is, if the first stress layer 40 is a tensile-stress layer then the second stress layer 50 is a tensile-stress layer, and if the first stress layer 40 is a compression-stress layer then the second stress layer 50 is a tensile-stress layer as illustrated by the following table:
The tensile-stress layer, be it first stress layer 40 or second stress layer 50, is preferably comprised of silicon nitride (Si3N4 or just SiN), silicon oxynitride (SiON), oxide or Si-rich nitride, is more preferably SiN or SiON and is most preferably SiON and has a thickness of preferably from about 200 to 1000 Å and more preferably from about 250 to 500 Å. The tensile-stress layer is preferably deposited by rapid thermal chemical vapor deposition (RTCVD) under the following conditions:
The compression-stress layer, which may be first stress layer 40, is preferably comprised of silicon nitride (Si3N4 or just SiN), silicon oxynitride (SiON), oxide or Si-rich nitride, is more preferably SiN or SiON and is most preferably SiON and has a thickness of preferably from about 200 to 1000 Å and more preferably from about 250 to 500 Å. The compression-stress layer is preferably deposited by plasma enhanced chemical vapor deposition (PECVD) under the following conditions:
The different stresses achieved by using either a first tensile-stress layer 40′/second compression-stress layer 50′ combination or a first compression-stress layer 40′/second tensile-stress layer 50′teachings of the present invention increases the mobility of holes and electrons.
Advantages of the Present Invention
The advantages of one or more embodiments of the present invention include:
While particular embodiments of the present invention have been illustrated and described, it is not intended to limit the invention, except as defined by the following claims.
Number | Name | Date | Kind |
---|---|---|---|
5562770 | Chen et al. | Oct 1996 | A |
5834363 | Masanori | Nov 1998 | A |
6271054 | Ballantine et al. | Aug 2001 | B1 |
6281532 | Doyle et al. | Aug 2001 | B1 |
6284610 | Cha et al. | Sep 2001 | B1 |
6403482 | Rovedo et al. | Jun 2002 | B1 |
6444566 | Tsai et al. | Sep 2002 | B1 |
6573172 | En et al. | Jun 2003 | B1 |
6599792 | Jung | Jul 2003 | B1 |
6678307 | Ezaki et al. | Jan 2004 | B1 |
6737308 | Kim | May 2004 | B1 |
20020058186 | Nozawa et al. | May 2002 | A1 |
20020175146 | Dokumaci et al. | Nov 2002 | A1 |
20040099910 | Choe et al. | May 2004 | A1 |
20040110377 | Cho et al. | Jun 2004 | A1 |
Number | Date | Country | |
---|---|---|---|
20040104405 A1 | Jun 2004 | US |