Claims
- 1. A system for scanning an image, the system comprising:
a CMOS imaging system with at least one CMOS imager having at least one series of pixels; an image focusing device for directing the image on to at least a portion of the at least one series of pixels; and an image control processing system coupled to the CMOS imaging system.
- 2. The system as set forth in claim 1 wherein the CMOS imager has two or more series of pixels, wherein at least one of the series of pixels is offset from another one of the series of pixels.
- 3. The system as set forth in claim 2 wherein the offset of each of the two or more series of pixels from each other is by a reciprocal of a total number of the two or more series of pixels.
- 4. The system as set forth in claim 1 wherein the image control processing system further comprises a shutter controller for the at least one series of pixels to control integration for all of the pixels in the at least one series of pixels.
- 5. The system as set forth in claim 1 wherein the image control processing system further comprises a resolution adjustment system that skips one or more of the pixels in the at least one series to reduce resolution and increase frame rate.
- 6. The system as set forth in claim 1 further comprising at least three CMOS imagers, each of the CMOS imagers having at least one series of pixels.
- 7. The system as set forth in claim 6 further comprising a different color filter for each of the CMOS imagers to capture a different color band.
- 8. The system as set forth in claim 6 wherein the image control processing system further comprises a binning system that combines a signal on the pixel in the at least one series of pixels in one of the CMOS imagers with a signal on at least the pixel in the at least one series of pixels in another one of the CMOS imagers.
- 9. A method for scanning an image, the method comprising:
directing the image on to at least a portion of at least one series of pixels in a CMOS imaging system; capturing the image with the at least one series of pixels in a CMOS imager in the CMOS imaging system; and controlling at least one aspect of the CMOS imaging system during the capturing and processing of the image.
- 10. The method as set forth in claim 9 wherein the CMOS imager in the CMOS imaging system has two or more series of pixels and further comprising offsetting at least one of the series of pixels from another one of the series of pixels.
- 11. The method as set forth in claim 9 wherein the offset of each of the two or more series of pixels from each other in the CMOS imager is by a reciprocal of a total number of the two or more series of pixels.
- 12. The method as set forth in claim 10 further comprising controlling integration in the at least one series of pixels in the CMOS imaging system with a shutter controller for all of the pixels in the at least one series of pixels.
- 13. The method as set forth in claim 9 further comprising skipping one or more of the pixels in the at least one series in the CMOS imager.
- 14. The method as set forth in claim 9 wherein the capturing of the image further comprises capturing the image with at least three CMOS imagers, each of the CMOS imagers having at least one series of pixels.
- 15. The method as set forth in claim 14 further comprising filtering a different color for each of the CMOS imagers to capture a different color band.
- 16. The method as set forth in claim 14 further comprising binning a signal on the pixel in the at least one series of pixels in one of the CMOS imagers with a signal on at least the pixel in the at least one series of pixels in another one of the CMOS imagers.
- 17. A system for capturing an image, the system comprising:
a first series of pixels in at least one CMOS imager; and at least one more series of pixels that are at least adjacent to the first series of pixels in the at least one CMOS imager, wherein the at least one more series of pixels is offset from the first series of pixels.
- 18. The system as set forth in claim 17 wherein the offset of the at least one more series of pixels from the first series of pixels is by a reciprocal of a total number of the first series of pixels and the at least one more series of pixels.
- 19. The system as set forth in claim 17 further comprising an image control processing system coupled to the at least one CMOS imager.
- 20. The system as set forth in claim 19 wherein the image control processing system further comprises a shutter controller for each of the first series of pixels and the at least one more series of pixels, each of the shutter controllers controlling integration for all of the pixels in the first series of pixels or the at least one more series of pixels.
- 21. The system as set forth in claim 19 wherein the image control processing system further comprises a resolution adjustment system that skips one or more of the pixels in one or more of the first series of pixels and the at least one more series of pixels.
- 22. The system as set forth in claim 19 further comprising at least three of the CMOS imagers, each of the CMOS imagers is coupled to the image control processing system and has at least the first series of pixels and the at least one more series of pixels at least adjacent to the first series of pixels, wherein the at least one more series of pixels is offset from the first series of pixels in each of the CMOS imagers.
- 23. The system as set forth in claim 22 further comprising a different color filter for each of the CMOS imagers to capture a different color band.
- 24. The system as set forth in claim 22 wherein the image control processing system further comprises a binning system that combines a signal on the pixel in the first series of pixels or the at least one more series of pixels in one of the CMOS imagers with a signal on at least the pixel in the first series of pixels or the at least one more series of pixels in another one of the CMOS imagers.
- 25. A method for capturing an image, the method comprising:
offsetting a first series of pixels in at least one CMOS imager from at least one more series of pixels that are at least adjacent to the first series of pixels in the at least one CMOS imager; and capturing the image with at least a portion of the offset first series of pixels and the at least one more series of pixels.
- 26. The method as set forth in claim 25 wherein the offsetting of the at least one more series of pixels from the first series of pixels is by a reciprocal of a total number of the first series of pixels and the at least one more series of pixels.
- 27. The method as set forth in claim 25 further comprising controlling integration for all of the pixels in the first series of pixels or the at least one more series of pixels with a shutter controller.
- 28. The method as set forth in claim 25 further comprising skipping one or more of the pixels in at least one of the first series of pixels and the at least one more series of pixels.
- 29. The method as set forth in claim 25 wherein the capturing further comprises capturing the image with at least three of the CMOS imagers, each of the CMOS imagers having at least the first series of pixels and the at least one more series of pixels at least adjacent to the first series of pixels, wherein the at least one more series of pixels is offset from the first series of pixels in each of the CMOS imagers.
- 30. The method as set forth in claim 29 further comprising filtering for a different color filter for each of the CMOS imagers.
- 31. The method as set forth in claim 29 further comprising binning a signal on the pixel in one of the first series of pixels or the at least one more series of pixels in one of the CMOS imagers with a signal on at least one of the pixels in another of the first series of pixels or the at least one more series of pixels in another one of the CMOS imagers.
- 32. A system for capturing an image, the system comprising:
a CMOS system with at least one CMOS imager having at least one series of pixels on a CMOS chip, the CMOS system having one or more functions; an image focusing device for directing the image on to at least a portion of the at least one series of pixels; and an image control processing system coupled to the CMOS imaging system and on the CMOS chip, the image control processing system having at least one function.
- 33. The system as set forth in claim 32 wherein the one or more functions for the CMOS system comprises imaging.
- 34. The system as set forth in claim 32 wherein the one or more functions for the CMOS system comprise imaging and printing.
- 35. The system as set forth in claim 32 wherein the one or more functions for the image control processing system comprises image control.
- 36. The system as set forth in claim 32 wherein the one or more functions for the image control processing system comprise image control and print processing.
- 37. The system as set forth in claim 32 wherein the one or more functions for the image control processing system comprise image control and facsimile processing.
- 38. The system as set forth in claim 32 wherein the CMOS imager has two or more series of pixels, wherein at least one of the series of pixels is offset from another one of the series of pixels.
- 39. The system as set forth in claim 38 wherein the offset of each of the two or more series of pixels from each other is by a reciprocal of a total number of the two or more series of pixels.
- 40. The system as set forth in claim 32 wherein the image control processing system further comprises a shutter controller for the at least one series of pixels to control integration for all of the pixels in the at least one series of pixels.
- 41. The system as set forth in claim 32 wherein the image control processing system further comprises a resolution adjustment system that skips one or more of the pixels in the at least one series to reduce resolution and increase frame rate.
- 42. The system as set forth in claim 32 further comprising at least three CMOS imagers, each of the CMOS imagers having at least one series of pixels.
- 43. The system as set forth in claim 42 further comprising a different color filter for each of the CMOS imagers to capture a different color band.
- 44. The system as set forth in claim 42 wherein the image control processing system further comprises a binning system that combines a signal on the pixel in the at least one series of pixels in one of the CMOS imagers with a signal on at least the pixel in the at least one series of pixels in another one of the CMOS imagers.
- 45. A system for capturing an image, the system comprising:
a CMOS imaging system with at least one CMOS imager having at least one series of pixels on a CMOS chip;and an image processing system coupled to the CMOS imaging system and on the CMOS chip; and a power monitoring system coupled to the CMOS imaging system and on the CMOS chip, the power monitoring system shutting down power consumption during non use periods.
- 46. The system as set forth in claim 45 further comprising an image focusing device for directing the image on to at least a portion of the at least one series of pixels.
- 47. The system as set forth in claim 45 wherein the CMOS imager has two or more series of pixels, wherein at least one of the series of pixels is offset from another one of the series of pixels.
- 48. The system as set forth in claim 47 wherein the offset of each of the two or more series of pixels from each other is by a reciprocal of a total number of the two or more series of pixels.
- 49. The system as set forth in claim 45 wherein the image processing system further comprises a shutter controller for the at least one series of pixels to control integration for all of the pixels in the at least one series of pixels.
- 50. The system as set forth in claim 45 wherein the image processing system further comprises a resolution adjustment system that skips one or more of the pixels in the at least one series to reduce resolution and increase frame rate.
- 51. The system as set forth in claim 45 further comprising at least three CMOS imagers, each of the CMOS imagers having at least one series of pixels.
- 52. The system as set forth in claim 51 further comprising a different color filter for each of the CMOS imagers to capture a different color band.
- 53. The system as set forth in claim 51 wherein the image control processing system further comprises a binning system that combines a signal on the pixel in the at least one series of pixels in one of the CMOS imagers with a signal on at least the pixel in the at least one series of pixels in another one of the CMOS imagers.
- 54. A method for capturing an image, the method comprising:
capturing the image with a CMOS imaging system with at least one CMOS imager having at least one series of pixels; and controlling at least one aspect of the CMOS imaging system during processing of the image; and monitoring use of the CMOS imaging system; shutting down power during the monitored periods of non use periods.
- 55. The method as set forth in claim 54 further comprising directing the image on to at least a portion of the at least one series of pixels.
- 56. The method as set forth in claim 54 wherein the CMOS imager has two or more series of pixels, wherein at least one of the series of pixels is offset from another one of the series of pixels.
- 57. The method as set forth in claim 56 wherein the offset of each of the two or more series of pixels from each other is by a reciprocal of a total number of the two or more series of pixels.
- 58. The method as set forth in claim 54 further comprising controlling integration in the at least one series of pixels with a shutter controller for all of the pixels in the at least one series of pixels.
- 59. The method as set forth in claim 54 further comprising skipping one or more of the pixels in the at least one series in the CMOS imager.
- 60. The method as set forth in claim 54 wherein capturing the image further comprises further comprises capturing the image with at least three CMOS imagers, each of the CMOS imagers having at least one series of pixels.
- 61. The method as set forth in claim 54 further comprising filtering a different color for each of the CMOS imagers to capture a different color band.
- 62. The system as set forth in claim 54 further comprising binning a signal on the pixel in the at least one series of pixels in one of the CMOS imagers with a signal on at least the pixel in the at least one series of pixels in another one of the CMOS imagers.
- 63. A CMOS compatible imaging device, comprising a CMOS imager having two or more series of pixels, wherein at least one of the series of pixels is offset from another one of the series of pixels.
- 64. The system as set forth in claim 63 wherein at least two of the two or more series of pixels are adjacent to each with out spacing.
Parent Case Info
[0001] The present invention claims the benefit of U.S. Provisional Patent Application Serial No. 60/289,076, filed May 7, 2001, which is hereby incorporated by reference in its entirety.
Provisional Applications (1)
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Number |
Date |
Country |
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60289076 |
May 2001 |
US |