DESCRIPTION OF THE DRAWINGS
Embodiments of the invention are described hereafter with reference to the accompanying drawings. It should be noted, however, that the various drawing features are not necessarily drawn to scale. In fact, the relative dimensions of the various features may be arbitrarily increased or decreased to add clarity to the description. Wherever applicable and practical, like reference numerals refer to like or similar elements.
FIGS. 1A through 1D depict portions of a semiconductor substrate undergoing a conventional Chemical/Mechanical Polishing (CMP) process;
FIG. 2 illustrates an exemplary polishing device which may be adapted for use with embodiments of the invention;
FIGS. 3-7 depict various portions of exemplary semiconductor substrates undergoing a planarization process according to embodiments of the invention;
FIG. 8 is a graph further illustrating a relationship between pressure applied to a semiconductor substrate during an exemplary CMP process and the resultant rate of removal of a material layer from a working surface of the substrate; and
FIG. 9 is a flowchart outlining an exemplary CMP process consistent with embodiments of the invention.