CMP method providing reduced thickness variations

Information

  • Patent Application
  • 20070167014
  • Publication Number
    20070167014
  • Date Filed
    October 05, 2006
    18 years ago
  • Date Published
    July 19, 2007
    17 years ago
Abstract
A chemical mechanical polishing (CMP) method is disclosed for use in the fabrication of a semiconductor device having dense and sparse regions. The method uses an abrasive stop layer formed on the dense and sparse regions to control polishing of a material layer formed on the abrasive stop layer by a rigid, fixed abrasive polishing pad.
Description

DESCRIPTION OF THE DRAWINGS

Embodiments of the invention are described hereafter with reference to the accompanying drawings. It should be noted, however, that the various drawing features are not necessarily drawn to scale. In fact, the relative dimensions of the various features may be arbitrarily increased or decreased to add clarity to the description. Wherever applicable and practical, like reference numerals refer to like or similar elements.



FIGS. 1A through 1D depict portions of a semiconductor substrate undergoing a conventional Chemical/Mechanical Polishing (CMP) process;



FIG. 2 illustrates an exemplary polishing device which may be adapted for use with embodiments of the invention;



FIGS. 3-7 depict various portions of exemplary semiconductor substrates undergoing a planarization process according to embodiments of the invention;



FIG. 8 is a graph further illustrating a relationship between pressure applied to a semiconductor substrate during an exemplary CMP process and the resultant rate of removal of a material layer from a working surface of the substrate; and



FIG. 9 is a flowchart outlining an exemplary CMP process consistent with embodiments of the invention.


Claims
  • 1. A chemical mechanical polishing (CMP) method adapted for use in the fabrication of a semiconductor device, the method comprising: contacting a material layer disposed on a working surface of a substrate with a rigid, fixed abrasive polishing pad to planarize the material layer by removing a portion of the material layer until a portion of an abrasive stop layer disposed under the material layer is exposed.
  • 2. The CMP method of claim 1, further comprising introducing a polishing slurry to the polishing pad.
  • 3. The CMP method of claim 2, wherein the polishing slurry is an abrasive-less slurry.
  • 4. The CMP method of claim 2, wherein the polishing slurry comprises a passivation agent adapted to define a polishing selectivity between the material layer and the CMP stop layer.
  • 5. The CMP method of claim 4, wherein the passivation agent selectively passivates the CMP stop layer to inhibit removal of the CMP stop layer by the polishing pad surface.
  • 6. The CMP method of claim 1, wherein the material layer comprises an interlayer dielectric layer.
  • 7. The CMP method of claim 6, wherein the interlayer dielectric layer comprises an oxide, and the abrasive stop layer comprises a nitride.
  • 8. The CMP method of claim 6, further comprising: forming a second interlayer dielectric layer on the planarized interlayer dielectric layer.
  • 9. The CMP method of claim 1, wherein the material layer comprises at least one of a metal and a metal alloy.
  • 10. The CMP method of claim 1, wherein contacting the material layer with the rigid polishing pad surface comprises: applying pressure to the substrate against the polishing pad.
  • 11. The CMP method of claim 10, wherein contacting the material layer with the rigid polishing pad surface further comprises: the pressure applied to the substrate is less than a threshold pressure defined in relation to the material layer.
  • 12. A method of fabricating a semiconductor device on a substrate, the substrate including dense and sparse regions, and the method comprising: forming an abrasive stop layer on the dense and sparse regions;forming a material layer on the abrasive stop layer; and,planarizing the material layer with a rigid, fixed abrasive polishing pad until a portion of the abrasive stop layer on the dense region is exposed.
  • 13. The fabrication method of claim 12, wherein the material layer comprises a first interlayer dielectric layer, and the method further comprises: forming a second interlayer dielectric layer on the planarized first dielectric layer.
  • 14. The fabrication method of claim 12, further comprising defining a polishing selectivity between the material layer and the abrasive stop layer by introducing a slurry during the planarization of the material layer.
  • 15. The fabrication method of claim 14, wherein the slurry comprises a passivation agent selected in relation to the abrasive stop layer.
  • 16. The fabrication method of claim 12, further comprising: defining a threshold pressure in relation to the material layer; andwherein planarizing the material layer comprises:applying a first pressure on the substrate against the polishing pad which is less than the threshold pressure.
  • 17. The fabrication method of claim 12, wherein the material layer comprises a metal or a metal alloy.
  • 18. A method of fabricating a semiconductor device disposed in a dense region and a sparse region of a substrate, the method comprising: forming an abrasive stop layer on at least the dense region of the substrate;forming a first interlayer dielectric layer on the substrate to cover the abrasive stop layer in the dense region and the sparse region;while introducing a slurry comprising a passivation agent selected in relation to the abrasive stop layer, planarizing the first interlayer dielectric layer using a rigid, fixed abrasive polishing pad until the abrasive stop layer is exposed; and,after planarizing the first interlayer dielectric layer, forming a uniformly thick second interlayer dielectric layer on the substrate.
  • 19. The fabrication method of claim 18, wherein the CMP abrasive stop layer comprises a nitride and is formed on both the dense and sparse regions of the substrate.
  • 20. The fabrication method of claim 18, wherein planarizing the first interlayer dielectric layer comprises applying a pressure to the substrate against the polishing pad less than a threshold pressure defined in relation to the first interlayer dielectric.
  • 21. The fabrication method of claim 20, wherein the slurry comprises at least one abrasive material selected from a group of abrasive materials consisting of ceria, silica, alumina, titania, zirconia, and germania.
  • 22. The fabrication method of claim 20, wherein the passivation agent comprises at least one material selected from a group of materials consisting of carbolic acid, phosphoric acid, sulfonic acid, amine, sulfuric ester and L-proline.
  • 23. The fabrication method of claim 22, where the passivation agent changes the selectivity between the interlayer dielectric layer and the abrasive stop layer by at least a factor of ten times.
  • 24. The fabrication method of claim 18, wherein the planarizing of the first interlayer dielectric layer comprises: initially removing material from the first interlayer dielectric material at a first removal rate; and thereafter,removing material from the first interlayer dielectric layer at a second removal rate less than the first removal rate as the rigid, fixed abrasive polishing pad approaches the abrasive stop layer.
  • 25. The fabrication method of claim-24, wherein the planarizing of the first interlayer dielectric layer further comprises: removing material from the first interlayer dielectric layer at a third removal rate less than the second removal rate after the rigid, fixed abrasive polishing pad makes contact with abrasive stop layer.
  • 26. The fabrication method of claim 25, wherein at least one of the second and third removal rates is defined in relation to the slurry.
Priority Claims (1)
Number Date Country Kind
10-2006-0004876 Jan 2006 KR national