The present invention relates to the field of electronics, and especially to a COB die bonding and wire bonding system and method.
COB (Chips on Board), i.e., a technology that a bare chip is adhered to an interconnected substrate with a conductive or non-conductive adhesive, and then its electrical connection is achieved by wire bonding.
Since one die bonder is used during the traditional die bonding operation, only die bonding in the same direction can be achieved, and the wire can only be bonded according to the positive and negative poles in sequence. As most COB substrates are circular, a folded wire bonding mode is formed, as shown in
In order to solve the above-mentioned technical problem, an object of the invention is to provide a COB die bonding and wire bonding device that can save the amount of gold wire used and the time for wire bonding.
In order to solve the above-mentioned technical problem, another object of the invention is to provide a COB die bonding and wire bonding method that can save the amount of gold wire used and the time for wire bonding.
The technical solution adopted in the invention is: a COB die bonding and wire bonding system, comprising a controller, a forward die bonder, a reverse die bonder and a conveyor belt, the controller being connected with the forward die bonder and the reverse die bonder respectively, and the forward die bonder is associated with the reverse die bonder by the conveyor belt.
Further, the controller includes a shortest wire bonding path calculation module which is used to calculate a die bonding layout of chips to achieve the shortest wire bonding path on a substrate.
Further, the shortest wire bonding path calculation module is used to calculate a die bonding layout of chips which can achieve the shortest wire bonding path on a substrate according to the forward die bonding and the reverse die bonding for chips.
Further, the COB die bonding and wire bonding system further comprises a wire bonding device which is connected with the controller.
Another technical solution adopted by the invention is: a COB die bonding and wire bonding method, comprising the following steps:
A. Calculating a die bonding layout of chips which can achieve the shortest wire bonding path on a substrate according to the forward die bonding and the reverse die bonding for the chips;
B. Sending the forward die bonding layout in the above die bonding layout of chips to the forward die bonder, while sending the reverse die bonding layout in the above die bonding layout of chips to the reverse die bonder, and sending the shortest wire bonding path to the wire bonding device;
C. Performing die bonding on the substrate by the forward die bonder, transporting the forward die bonded substrate to the reverse die bonder by the conveyor belt, then performing die bonding on the substrate by the reverse die bonder; and
D. Performing wire bonding to the chips on the substrate by the wire bonding device.
Further, in the die bonding layout of chips which can achieve the shortest wire bonding path in step A, the chips are arranged in rows, wherein the chips in each row are arranged forwardly or reversely, and two adjacent rows of chips are arranged in opposite directions.
Further, in step A of calculating the die bonding layout of chips which can achieve the shortest wire bonding path on the substrate, a Dijkstra algorithm, a SPFA algorithm, a Bellman-Ford algorithm or a Floyd-Warshall algorithm is used.
Further, the die bonding by the reverse die bonder precedes that by the forward die bonder in step C, and the specific description is as follows: performing die bonding on the substrate by the reverse die bonder, transporting the reverse die bonded substrate to the forward die bonder by the conveyor belt, and then performing die bonding on the substrate by the forward die bonder.
One beneficial effect of the invention is that the device of the invention realizes the combination of the forward and reverse bonding when using the forward die bonder and the reverse die bonder to fix the chips, thus the amount of gold wire used for connecting the chips on the substrate is minimized, which in turn saves the cost of electric circuit, working time and labor force.
Another beneficial effect of the invention is that the method of the invention realizes the combination of the forward and reverse bonding when using the forward die bonder and the reverse die bonder to fix the chips, thus the amount of gold wire used for connecting chips on the substrate is minimized, which in turn saves the cost of electric circuit, working time and labor force.
The specific embodiments of the invention will be further illustrated below with reference to the accompanying drawings.
With reference to
In a further preferred embodiment, the controller includes a shortest wire bonding path calculation module which is used to calculate a die bonding layout of chips to achieve the shortest wire bonding path on a substrate.
In a further preferred embodiment, the shortest wire bonding path calculation module is used to calculate a die bonding layout of chips, which can achieve the shortest wire bonding path on a substrate, according to the forward die bonding and the reverse die bonding for chips.
In a further preferred embodiment, the COB die bonding and wire bonding system further comprises a wire bonding device which is connected with the controller.
With reference to
A. Calculating a die bonding layout of chips which can achieve the shortest wire bonding path on a substrate according to the forward die bonding and the reverse die bonding for chips;
B. Sending the forward die bonding layout in the above die bonding layout of chips to the forward die bonder, while sending the reverse die bonding layout in the above die bonding layout of chips to the reverse die bonder, and sending the shortest wire bonding path to the wire bonding device;
C. Performing die bonding on a substrate by the forward die bonder, transporting the forward die bonded substrate to the reverse die bonder by the conveyor belt, and then performing die bonding on the substrate by the reverse die bonder; and
D. Performing wire bonding to the chips on the substrate by the wire bonding device.
In a further preferred embodiment, in the die bonding layout of chips which can achieve the shortest wire bonding path in step A, the chips are arranged in rows, wherein the chips in each row are arranged forwardly or reversely, and two adjacent rows of chips are arranged in opposite directions.
In a further preferred embodiment, in step A of calculating the die bonding layout of chips which achieves the shortest wire bonding path on the substrate, a Dijkstra algorithm, a SPFA algorithm, a Bellman-Ford algorithm or a Floyd-Warshall algorithm is adopted.
When the above algorithm is adopted, the forward die bonding and the reverse die bonding for chips in step A are constraint conditions for guaranteeing that there are only the above two die bonding ways for chips, which can be accomplished by the forward/reverse die bonders.
In a further preferred embodiment, in step C, the die bonding operation by a reverse die bonder precedes that by the forward die bonder, and the specific description is as follows: performing die bonding on the substrate by the reverse die bonder, transporting the reverse die bonded substrate to the forward die bonder by the conveyor belt, and then performing die bonding operation on the substrate by the forward die bonder.
With reference to
Compared with
In the embodiment of the method as shown in
Meanwhile, as the die bonder performs die bonding after identifying the chips according to their characteristics, the chips can only be bonded in one direction. A repeated setting of parameters will undoubtedly increase labor costs. The new implementation method can be achieved with a system composed of two die bonders, with the first die bonder fixing the chips in the forward direction, the second die bonder fixing the chips in the reverse direction, and the middle section being connected through the automatic conveyor belt, thereby saving the implementation time and cost.
With reference to
While the preferred embodiments of the invention have been specifically described above, the invention is not limited thereto. Various equivalent variations and substitutions may be made by those skilled in the art without departing from the spirit of the invention and should be included within the scope defined by the claims of this application.
Number | Date | Country | Kind |
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201510908357.4 | Dec 2015 | CN | national |
Filing Document | Filing Date | Country | Kind |
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PCT/CN2015/097990 | 12/21/2015 | WO | 00 |