Claims
- 1. A complementary metal oxide semiconductor integrated circuit having a power supply comprising:
- a semiconductor substrate of a first conductivity type forming the collector of a first transistor and the base of a second transistor.
- a well of a second conductivity type formed in said semiconductor substrate and defining the base of the first transistor and the collector of the second transistor, said second conductivity type being opposite to said first conductivity type,
- a first diffusion region of said second conductivity type formed in said well, a first reference voltage being applied to said first diffusion region,
- a second diffusion region of said first conductivity type and defining the emitter of said first transistor formed in said well,
- a third diffusion region of said second conductivity type defining a power supply terminal formed in said well and separated from said first diffusion region, and
- a fourth diffusion region of said second conductivity type formed in said semiconductor substrate, spaced laterally apart from said well and forming the emitter of said second transistor, a second reference voltage different from said first reference voltage being applied to said fourth diffusion region,
- said second diffusion region and said third diffusion region being in contact with each other within said well, a metallic layer of said substrate above said well electrically connecting said second and third diffusion regions to each other.
- 2. A complementary metal oxide semiconductor integrated circuit in accordance with claim 1, wherein
- said first conductivity type is a P type,
- said second conductivity type is an n type, and
- said first reference voltage is selected to be higher than said second reference voltage.
- 3. A complementary metal oxide semiconductor integrated circuit in accordance with claim 1, wherein
- said first conductivity type is an N type,
- said second conductivity type is a P type, and
- said first reference voltage is selected to be lower than said second reference voltage.
- 4. A complementary metal oxide semiconductor integrated circuit in accordance with claim 1, wherein
- said first diffusion region is formed in the vicinity of one end of said well, and
- said third diffusion region is formed in the vicinity of the other end of said well.
Priority Claims (1)
Number |
Date |
Country |
Kind |
59-86875 |
Apr 1984 |
JPX |
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Parent Case Info
This application is a continuation of application Ser. No. 719,055 filed Apr. 2, 1985 now abandoned.
US Referenced Citations (9)
Foreign Referenced Citations (6)
Number |
Date |
Country |
0084000 |
Jul 1983 |
EPX |
58-127348 |
Jul 1983 |
JPX |
1542481 |
Mar 1979 |
GBX |
1559581 |
Jan 1980 |
GBX |
1558502 |
Jan 1980 |
GBX |
2158640 |
Nov 1985 |
GBX |
Non-Patent Literature Citations (1)
Entry |
Chen, "Latch-Up Elimination in High Density DMOS", 1983 VLSI Symposium Digest, pp. 54-55. |
Continuations (1)
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Number |
Date |
Country |
Parent |
719055 |
Apr 1985 |
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