Patent Grant
11989143
As machine learning and other processes become common, datasets continue to grow in size. As the size of datasets increase, the datasets become impractical to store and, thus, processing on the datasets must be efficiently performed to extract useful insight from such datasets.
Described are methods and systems utilizing cache coherent switch on chip. In a certain embodiment, a system may be disclosed. The system may include a first server device and a second server device. The first server device may include a first memory device and a first cache coherent switch on chip, communicatively coupled to the first memory device via a Compute Express Link (CXL) protocol. The second server device may be communicatively coupled to the first server device via a data connection and may include a second memory device and a second cache coherent switch on chip, communicatively coupled to the second memory device via the CXL protocol and communicatively coupled to the first cache coherent switch on chip by the data connection via the CXL protocol. The first cache coherent switch on chip and the second cache coherent switch on chip may be configured to pool the first memory device and the second memory device.
Illustrative, non-exclusive examples of inventive features according to the present disclosure are described herein. These and other examples are described further below with reference to figures.
The disclosure may best be understood by reference to the following description taken in conjunction with the accompanying drawings, which illustrate various embodiments.
In the following description, specific details are set forth to provide illustrative examples of the systems and techniques described herein. The presented concepts may be practiced without some, or all, of these specific details. In other instances, well known process operations have not been described in detail to avoid unnecessarily obscuring the described concepts. While some concepts will be described with the specific examples, it will be understood that these examples are not intended to be limiting.
For the purposes of this disclosure, certain Figures may include a plurality of similar components. The plurality of such components may be indicated with A, B, C, D, E, F, G, H, . . . N, and/or such indicators to distinguish the individual such components within the Figures. In certain instances, references may be provided to such components without reference to the letter indicators. It is appreciated that, in such instances, disclosure may apply to all such similar components.
Components described herein are referred to with a three digit ordinal indicator number. In certain instances of this disclosure, certain components may be described herein within a plurality of Figures. In such instances, similar components appearing in a plurality of Figures may include the same final two digits of the three digit ordinal indicator number (e.g., X02).
Some embodiments of the disclosed systems, apparatus, methods and computer program products are configured for implementing cache coherent switch on chip. As described in further detail below, such a system may be implemented utilizing the Compute Express Link (CXL) interconnect open standard. Such a CXL based cache on chip allows for low latency paths for memory access and coherent caching between devices.
Utilizing CXL, the currently disclosed cache coherent switch on chip allows for connection of a variety of components connected through a high speed low latency interface. The currently disclosed cache coherent switch on chip allows for multi-host access and the sharing of resources. The cache coherent switch on chip allows for greater utilization of resources, creation of composable virtual servers aligned with workloads, higher efficiency and performance of systems, and flexibility for architecture modifications of systems. The features of the cache coherent switch on chip allows for more efficient utilization of resources and power consumption while providing increased system level performance.
The disclosed cache coherent switch on chip allows for component disaggregation and server composability through system resource sharing without requiring a processor to control such resource sharing and, thus, becoming a bottleneck. As such, system resources may be more fully utilized and resource sharing may optimize component usage within a system, enabling more workloads to be executed. The cache coherent switch on chip also decreases the burden on the system processor, as the system processor is no longer required to handle data and memory transfers and other such tasks.
Furthermore, the disclosed cache coherent switch on chip allows for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclosed systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.
As the size of datasets and the speeds required to process them grow, the value of effective caching and access to such caches becomes ever more valuable. In various embodiments, the systems and techniques may provide for a switch on chip for the caching layer of memory. Thus, cached data, as well as other transient data, may be shared between various devices of a system without requiring CPU involvement. The sharing of cached data or another such transient data may provide for much faster access to such cached data and significantly increase the amount of cached data that may be effectively stored within a system. Accordingly, the systems and techniques provide for switching and sharing of cached data, allowing for data to be accessed at a much faster speed without CPU involvement and for greater optimization of storage of such cached data. Due to CPU involvement no longer being required, a much greater amount of cached data may be shared between various memories, accelerators, graphics cards, and/or other devices.
In various embodiments, a cache hierarchy may be determined and/or utilized by one or more cache coherent switch on chip caches, indicating which caches are prioritized for refreshing and/or reading/writing. In certain embodiments, such caches may be configured to fetch, read, and/or write data according to such hierarchy. Packet flow of data between various components, as well as for caching, may thus be optimized.
Processor 104 may be any type of processor, such as a central processing unit (CPU) and/or another type of processing circuitry such as a single core or multi-core processor. Processor 104 may be a main processor of an electronic device. For the purposes of this disclosure, “processor,” “CPU,” “microprocessor,” and other such reference to processing circuitry may be interchangeable. Thus, reference to one such component may include reference to other such processing circuitry. In various embodiments, an electronic device or system may include one or a plurality of processors 104. Each processor may include associated components, such as memory 114B. Memory 114B may, for example, be a memory module, such as a dual in-line memory module, and may provide memory for processor 104.
Cache coherent switch on chip 102 may be configured to allow for sharing of resources between various components of system 100, as described herein. Such components may include, for example, accelerators 106A and 106B, storage 108 (e.g., smart storage such as harddrives or memories such as solid state drives), ASIC 110, PM 112, and memory 114A. Accelerators 106A and 106B may be hardware or software configured to accelerate certain types of workloads and are configured to more efficiently perform such specific workloads. Storage 108 may be harddrives and/or other storage devices. ASIC 110 may be, for example, artificial intelligence ASICs and/or other such ASICs configured to perform specific tasks. PM 112 may be non-volatile low latency memory with densities that are greater than or equal to DRAM, but may have latencies that are greater than DRAM. Memory 114A may be, similar to memory 114B, a memory module including random access memory (RAM) and/or another such memory.
In various embodiments, cache coherent switch on chip 102 may be communicatively coupled to one or more such components of system 100 via CXL interface 116. Cache coherent switch on chip 102 may be configured to allow for sharing of resources between the various such components. In certain embodiments, cache coherent switch on chip 102 may include its own resources, such as its own RAM module, as well as other such resources that are described herein. Such resources may also be shared between the various components. Cache coherent switch on chip 102 may utilize CXL interface 116 to provide low latency paths for memory access and coherent caching (e.g., between processors and/or devices to share memory, memory resources, such as accelerators, and memory expanders). CXL interface 116 may include a plurality of protocols, including protocols for input/output devices (IO), for cache interactions between a host and an associated device, and for memory access to an associated device with a host. For the purposes of this disclosure, reference to a CXL interface or protocol described herein may include any one or more of such protocols. Cache coherent switch on chip 102 may utilize such protocols to provide for resource sharing between a plurality of devices by acting as a switch between the devices.
Typically, all components of a system is controlled via a processor. Thus, component-to-component traffic is controlled by the processor. In such a configuration, the processor, due to limited resources, becomes a bottleneck in component-to-component traffic, limiting the speed of component-to-component traffic. The techniques and systems described, such component-to-component traffic is controlled via cache coherent switch on chip 102, with CXL interface 116, generally bypassing processor 104. As CXL interface 116 allows for an extremely low latency interface between components, processor 104 is no longer a bottleneck and sharing of resources may be performed more quickly and efficiently.
In certain embodiments, one or more upstream ports 220 may be configured to support CXL protocols while one or more downstream ports 222 may be configured to support PCI and CXL protocols. In another embodiment, one or more upstream ports 220 may be configured to support PCI protocols while one or more downstream ports 222 may be configured to support CXL protocols. In a further embodiment, one or more upstream ports 220 may be configured to support PCI protocols while one or more downstream ports 222 may be configured to support PCI protocols. In yet another embodiment, one or more upstream ports 220 may be configured to support CXL protocols while one or more downstream ports 222 may be configured to support CXL protocols.
Cache coherent switch on chip 202 may include switched fabric circuitry 276 that includes a plurality of nodes and may interconnect a plurality of ports. Switched fabric circuitry 276 may be configured to receive input and/or provide output to the various ports. Accordingly, switched fabric circuitry 276 may be coupled to downstream ports 220, upstream ports 222, and/or other ports and/or portions of cache coherent switch on chip 202. Switched fabric circuitry 276 may be circuitry configured in a switched fabric manner, to allow for inputs and outputs to be interconnected and signals accordingly communicated.
Cache coherent switch on chip 202 may include processing core 274. Processing core 274 receives electrical signals from ports of cache coherent switch on chip 202 and transforms and/or outputs associated electrical signals to other ports of cache coherent switch on chip 202. Processing core 274 may be configured to transform signals from a first protocol to a second protocol, and/or may be configured to determine the appropriate port to output signals toward.
In various embodiments, a cache hierarchy may be determined and/or utilized by cache coherent switch on chip 302. The cache hierarchy may be, for example, a version of virtual hierarchy 324 and may indicate the priority for the caches of components coupled to cache coherent switch on chip 302. The cache hierarchy may indicate a priority for refreshing and/or reading/writing the caches of the various components. Such a cache hierarchy may be determined by cache coherent switch on chip 302 based on machine learning according to the techniques described herein and/or may be a preset hierarchy (e.g., a preset hierarchy of which caches of certain components are given priority and/or which components are given priority in utilization of the caches). In certain embodiments, such caches may be configured to fetch, read, and/or write data according to such hierarchy (e.g., higher priority components may be given priority for fetching, reading, and/or writing data to caches, according to the cache hierarchy).
In certain embodiments, one or more of upstream ports 304 and/or downstream ports 306 may include a bridge (e.g., a PCI-to-PCI bridge (PPB)) for coupling the ports to devices. Furthermore, cache coherent switch on chip 302 may include one or more virtual bridges (e.g., vPPB) for binding to one or more components coupled to cache coherent switch on chip 302. In various embodiments, such bridges may additionally include bridges such as SR2MR (Single Root to Multiple Root), SLD2MLD (Single Logical Device to Multi Logical Device), and/or other such legacy bridges to provide for communications with legacy devices.
In certain embodiments, SR2MR bridges may be configured to allow a single root PCIe device to be exposed to multiple host ports. For SR2MR bridges, downstream ports may implement one or a plurality of virtual point-to-point (P2P) bridges. In certain embodiments, one virtual P2P bridge may be utilized for each virtual hierarchy. The SR2MR bridges may be a part of a switch on chip or may be a separate chip communicatively coupled to the switch on chip.
In certain embodiments, SLD2MLD bridges may be configured to allow a CXL standard single logical device to be seen as a multi logical device by the switch domain. Downstream ports implement address translation and enforces the isolation normally performed by multi logical devices. The SLD2MLD bridges may be a part of the switch on chip or may be a part of a separate chip communicatively coupled to the switch on chip.
Cache coherent switch on chips 402A and 402B may be communicatively coupled via expansion port 472. In certain embodiments, cache coherent switch on chips 402 may include processing cores 474. Expansion port 472 may be a port on cache coherent switch on chips 402 to allow for expansion of processing power of cache coherent switch on chips 402 by, for example, allowing for interconnection of processing cores 474 (e.g., processing cores 474A and 474B). Expansion port 472 thus allows for increase in processing power and, in certain embodiments, expansion in the amount of component resources that may be shared. Accordingly, for example, memories 414B, 414C, 414E, and 414F as well as devices 428A to 428D may all be pooled resources for system 400. Memories 414 may be any type of appropriate memory described herein. One or more memories 414 may form a memory bank for portions of system 400, such as for one or more cache coherent switch on chips 402. Devices 428 may be any sort of device of a computing system, such as harddrives, graphics cards, ASICs, I/O devices, and/or other such devices. Furthermore, communicatively and/or electrically coupling together cache coherent switch on chips 402A and 402B may provide for greater system redundancy, increasing reliability.
Though the embodiment of
In certain embodiments, each of cache coherent switch on chip 402A and 402B may include their own virtual hierarchies. When coupled as in
Fabric manager 540 may be configured to allocate and/or deallocate resources attached to the ports of cache coherent switch on chips 502 to applications running on such ports (e.g., to applications running on ASICs coupled to ports of cache coherent switch on chips 502). Fabric manager 540 may be configured to receive signals (e.g., data) from an upstream port and direct the signal to the appropriate downstream port. Various techniques for receiving and directing such signals (e.g., packet flows) are described herein. Fabric manager 540, as well as other firmware and/or software may further manage hot plug coupling by devices 528 to downstream CXL ports. Fabric manager 540 may also manage the inventory of various devices coupled to the ports of the respective cache coherent switch on chip 502.
Fabric manager 540 may be communicatively coupled to management 530 for top level management of system 500, including management of the various cache coherent switch on chips 502 described herein. Thus, in various embodiments, management 530 may be, for example, a baseboard management controller and/or another management device or server configured to provide management/orchestration. In various embodiments, management 530 may interface with fabric management 540 to provide for management of the various cache coherent switch on chips (e.g., via a specific fabric management API).
Fabric manager 540 may be implemented within firmware of cache coherent switch on chip 502 (e.g., within the firmware of a microprocessor of cache coherent switch on chip 502). Such firmware may include a system fabric manager that implements the logic for operations to be performed by switch hardware and other helper functions for implementing the API and a CXL fabric manager for implementing the front-end fabric manager APIs according to the CXL specifications.
In certain embodiments, a CXL single logical device (SLD), such as device 528A, may be hot-inserted into or hot-removed from cache coherent switch on chip 502B (e.g., via port 516E, which may be a PCI and/or CXL protocol port). When such an SLD is first hot-inserted, it is assigned to fabric manager 540B. Diagnostics may be performed on the newly inserted SLD (e.g., either run as self-diagnostics by device 528A or run via diagnostics software on the processing core of cache coherent switch on chips 502). After the SLD has been determined to be ready, it can be assigned to one of the ports (e.g., port 516E) of cache coherent switch on chip 502B based on policy (e.g., due to a virtual hierarchy) or via a command (e.g., from software within system 100).
The assignment may include binding the corresponding downstream PPBs of a cache coherent switch on chip 502 to one of the vPPBs, virtual hierarchies, and host port of cache coherent switch on chip 502. The managed hot-inserted device 528A is then presented to the host port (e.g., port 516E) after its assignment to the respective virtual hierarchy to allocate device 528A. The host CPU (e.g., the CPU within the respective cache coherent switch on chip 502) may then discover device 528A (e.g., via software), load software for device 528A and begin communicating with device 528A.
Cache coherent switch on chip 602 may include a plurality of root ports 632. Such root ports 632 may include, for example, ports associated with a processing core of cache coherent switch on chip 602 as well as external devices. Root ports 632 may be assigned to downstream CXL resources, including embedded accelerators within system 600. Fabric manager 640 may include a processor (e.g., an ARM processor or another type of processor) and such a processor may be a part of one or more virtual hierarchies 624. Various downstream PPB ports 638 may be communicatively coupled to MLDs 640. The assignment of MLDs 640, as well as other components such as SLDs, memories, accelerators, and other such components, to certain PPBs 638 and vPPBs 636 may be controlled by fabric manager 640. Thus, fabric manager 640 may detect that a component has been coupled to a port of cache coherent switch on chip 602 and accordingly assign the component to the appropriate virtual hierarchy 624 (e.g., based on the detected type of the component). Furthermore, the appropriate PPB 638 and/or the vPPB 636 may be assigned to the component. In certain embodiments, such assignment may be based on the detected type of the component and on virtual hierarchy 624.
In various embodiments, the amount of memory attached to a socket is limited by the number of channels that the socket supports. In certain situations, in a data-centric environment, an entire operating data set may not fit in a server's available memory, resulting in poor performance and increased latency when processing the data. Cache coherent switch on chip 702 addresses this problem by allowing for low-latency memory expansion due to memories 714A and 714B via the ports of cache coherent switch on chip 702, increasing the amount of memory available to a host CPU (beyond what could be connected directly to the CPU). Memories 714 may be DDR4, DDR5, future DDR, DRAM, PM, NVMe, Low-Power Double Data Rate (LPDDR), and/or other such appropriate memory drives which may be expanded via CXL protocol through cache coherent switch on chip 702.
Such an ability of cache coherent switch on chip 702 is particularly beneficial in providing cost and performance advantages for memory intensive applications that would otherwise require a computing device with a large memory footprint or result in poor performance in a less expensive computing device with limited memory.
As illustrated in
In various embodiments, cache coherent switch on chips 802 may provide compression and/or decompression ability to conserve persistent memory as well as crypto ability to provide added security between transactions into and out of persistent memory.
In certain embodiments, a prefetched buffer scheme may be utilized at the memory source. Accordingly, in various embodiments, cache coherent switch on chips 802 may include memory prefetchers 878. Memory prefetchers 878 may be an intelligent algorithm run by the processing core of the cache coherent switch on chips 802. Memory prefetchers 878 may be an artificial intelligence (AI) or machine learning (ML) prefetcher configured to predict the addresses of future accesses to memories based on past access patterns by the hosts, and prefetch data from such memories for those addresses to store in DRAM buffers to reduce the latency of future accesses by the host applications. In certain embodiments, accelerators communicatively coupled to cache coherent switch on chip 802 may also be configured to provide prefetching when pooling resources via cache coherent switch on chips 802 between servers 842A and 842B.
In certain embodiments, disaggregated servers 842 may pool memory and/or other resources across a midplane (e.g., bus 844). Thus, for example, in a chassis or blade server, a large shared pool of memory on memory cards/blades is available to be used by server cards/blades (that could be lightweight servers, aka thin servers, with a minimal amount of their own memory connected to the CPU socket). Such memory pooling may provide cost and/or power consumption advantages by reducing the amount of unused memory and/or other resources in data center servers, as memory/resource pooling allows for greater flexibility and, thus, a lower requirement for fixed resources. Servers may also be more flexibly configured due to the advantages of resource sharing.
In a certain use case, current typical server systems may include 512 gigabyte (GB) or so of volatile memory in cloud service provider infrastructure. A portion of this memory is typically stranded due to lower memory utilization for all the applications. Additionally, certain cloud environments include highly memory intensive applications that require more than 512 GB of memory. Currently, for example, platforms allocate all the servers with 512 GB memory due to simplicity, stranding the memory resources in the majority of the servers in order to have enough capacity for edge use cases. The currently disclosed cache coherent switch on chips addresses this memory stranding problem by allowing for the sharing of CXL protocol persistent memory both inside the server system and to outside servers connected via a network.
In various embodiments, there may be both write and read flows for memory 914A. In a write flow, microprocessor 904 may indicate that writes on memory 914A are steered to a DRAM buffer port of cache coherent switch on chip 902A. For such writes, cache coherent switch on chip 902A may check to ensure that memory 914C is configured to provide buffer write/read commands to memory 914A, allowing for memory 914A to be used as a buffer for memory 914C. Thus, memory 914C is updated so that the buffer write/read address of memory 914C refers to that of memory 914A. Memory 914A may then be accordingly utilized as a buffer for memory 914C, avoiding the increase in access time of utilizing memory appliance 946.
In certain embodiments, for a read flow, microprocessor 904 may first query the buffer port of memory 914A for the wanted data. If such data is present within the buffer of memory 914A, the data may be provided to microprocessor 904. If memory 914A does not include such data, memory 914C may be queried and the requested data may be provided from memory 914C over switch fabric/bus 944.
In certain embodiments, the cache buffers of memory 914A include AI/ML prefetch algorithms. The algorithm is configured to predict the next set of addresses (expected to be fetched by the applications) and configures a direct memory access (DMA) engine to prefetch those addresses and store the data in read/write buffers, to be ready to be read by the applications. In certain embodiments, cache coherent switch on chip 902A is configured to keep statistics of hit ratios for each line that was prefetched to provide feedback to the algorithm for continuous improvement (e.g., to determine which prefetched data has been utilized).
In certain embodiments, cache coherent switch on chip 902A may provide instructions for operation of the memory prefetcher. Thus, cache coherent switch on chip 902A may be configured to determine data to be prefetched (e.g., based on the AI/ML prefetch algorithm) and provide instructions (via switch fabric/bus 944) to memory 914C to provide such prefetched data to memory 914A (via switch fabric/bus 944) for caching. Memory 914C may accordingly provide such data for buffering by memory 914A.
In certain embodiments, each upstream port of cache coherent switch on chip 902A is configured to determine whether a cache buffer port is assigned for the respective upstream port. If a cache buffer port is assigned, a further determination may be made as to which downstream port is assigned as the cache buffer port. Incoming traffic may then be accordingly provided to the assigned downstream port for cache buffer purposes.
In various embodiments, caching may be performed by memory of the switch on chip and/or memory attached to the ports of the switch on chip. Variously, cache coherent switch on chip 914A may determine whether requested data is within the cache and retrieve such data if it is present within the cache. If the data is not within the cache, a request may be provided to the coupled persistent memory for the data and the data may be accordingly provided. In certain embodiments, write requests may be provided to both the cache and the persistent memory.
In various embodiments, cache coherent switch on chips 1002A and 1002B may be communicatively coupled via an Ethernet connection (e.g., via network 1044). As such, cache coherent switch on chips 1002 may communicate via CXL protocol through Ethernet to allow for resource pooling and/or sharing (e.g., of memory, accelerators, and/or other devices) between different devices, server racks, and/or data centers.
In various embodiments, commands received from a host via a CXL protocol port of cache coherent switch on chips 1002 are received and terminated inside the respective cache coherent switch on chips 1002 at the CXL protocol port. Cache coherent switch on chip 1002 may then provide a corresponding command tunneled within the payload of Ethernet frames that are communicated over network 1044. Thus, cache coherent switch on chip 1002 includes a bridging function that is configured to terminate all the read and write commands (e.g., persistent memory flush commands) inside cache coherent switch on chip 1002 and provide corresponding commands over Ethernet.
NICs 1080 may be configured to allow for cache coherent switch on chips 1002s to communicate via network/bus 1044. In certain embodiments, cache coherent switch on chips 1002 may be provided for data flow between accelerators 1006 and NICs 1080 (which may be a Smart NIC) so that NICs 1080 may write directly into accelerator 1006's cache coherent memory. Such data flow allows for sending and/or receiving of cache coherent traffic over network 1044 by accelerators 1006.
The configuration of system 1000 allows for data to be communicated between components within servers 1000A and 1000B as well as between servers 1000A and 1000B without needing to be controlled by CPUs 1004. Furthermore, the components of system 1000 are decoupled from each other, with traffic controlled by respective cache coherent switch on chips 1002.
In a certain embodiments, system 1000 may be configured so that cache coherent traffic stays within respective servers 1000A and 1000B. Cache coherency within each server 1000A/B is resolved by respective CPU 1004. Cache coherent switch on chips 1002 may provide accelerator traffic over network 1044, but in certain such embodiments, such accelerator traffic may be non-cache coherent traffic. The cache coherent traffic is thus never exposed to network 1044.
In certain embodiments, (e.g., with processing core 474 within a cache coherent switch on chip, as described in
In a further embodiment of providing/receiving cache coherent traffic to accelerator 1006 over network 1044, NIC 1080 may indicate that it is providing cache coherent traffic to accelerator 1006. Upon receipt of such traffic, accelerator 1006 may provide the bias change of the coherent memory line to CPU 1004 (via cache coherent switch on chip 1002). Upon receipt, CPU 1004 may then provide snoop requests to all components within its respective server 1000A/B, and once the cache line is resolved, CPU 1004 provides a line resolved message to the requesting accelerator 1006. Upon receipt of this message, accelerator 1006 may write the received traffic from NIC 1080 into the cache coherent portion of the respective memory 1046 of accelerator 1006.
Typically, accelerator to accelerator traffic within a system is provided via a proprietary switch. Cache coherent switch on chip 1002 allows for the elimination of such a proprietary switch while providing for accelerator to accelerator traffic. Accordingly, CXL protocol data may be provided from a first accelerator 1006 to a cache coherent switch on chip 1002 and communicated to a second accelerator 1006.
In various embodiments, CPU 1004 may include a home agent configured to resolve coherent traffic. Cache coherent traffic may be resolved by the home agent of CPU 1004. However, cache coherency may also be resolved within a processing core (e.g., a processing core such as processing core 474 of cache coherent switch on chip) of the cache coherent switch on chip, removing CPU 1004 as a bottleneck.
In a typical system, when data arrives from a network, typical data flows include network to processor, processor to storage, storage to processor, and processor to accelerator. As the volume of data grows, the processor becomes a bottleneck in this type of circular cycle of data transfer.
Cache coherent switch on chip 1002 allows for data to flow through to its ultimate destination while bypassing any CPU bottleneck. Thus, cache coherent switch on chip 1002 allows for data transfer between various ports, such as between two downstream ports. Components that are coupled to cache coherent switch on chip 1002 may, accordingly, more easily transfer data between each other and bypass CPU bottlenecks. Such transfers may be of the CXL protocol format.
For data transfers between accelerators and storage devices allocated to a root port of a microprocessor of cache coherent switch on chip 1002, the transfers may be cache coherent (e.g., controlled by the microprocessor), removing the need for cache coherency to be resolved by CPU 1004. Such a configuration provides for bandwidth and latency advantages as CPU 1004 may be bypassed and may be especially beneficial for neural networks, cryptocurrency, and/or other such systems where accelerators, ASICs, and/or other devices are primarily used (e.g., during training or mining).
Each cache coherent switch on chip 1002 may be communicatively/electrically coupled with one or more of a plurality of accelerators 1006. As each cache coherent switch on chip 1002 may be communicatively/electrically coupled to one or more other cache coherent switch on chip 1002, the number of accelerators available to each of the communicatively/electrically coupled cache coherent switch on chips 1002 may be accordingly expanded across a network to encompass accelerators that are coupled to the plurality of cache coherent switch on chips 1002. Variously, cache coherent switch on chip 1002 may provide for such pooling regardless of whether the respective accelerator is assigned to CPU 1004 or a microprocessor of the cache coherent switch on chip 1002 (allowing for operation of the accelerator via cache coherent switch on chip 1002).
Thus, cache coherent switch on chip 1002 allows for creating and managing a pool of CXL protocol attached accelerators or other resources distributed across one or more cache coherent switch on chips 1002. In various embodiments, each cluster of communicatively coupled cache coherent switch on chips 1002 may include their own respective virtual hierarchies and cluster of resources. Resources within each cluster may communicate between each other accordingly as if all are connected to the same switch.
Resources within the pool (such as accelerators) may be allocated/deallocated to any application server inside a rack, aisle, data center, and/or any portion of networked data centers communicatively coupled via CXL protocol (including via CXL protocol over Ethernet or other networks). Applications servers may thus be provided with direct access to all accelerators within a cluster, removing all data transformations that are required in typical architecture (e.g., from CUDA code to RDMA protocol packets and back).
In certain embodiments, traffic passing through a first cache coherent switch on chip may be mirrored on a second cache coherent switch on chip. The mirrored traffic may then be utilized for, for example, analysis of traffic that is provided through the first cache coherent switch on chip.
For read packet 2000A, command 2010 may include a command indicating “PM read” with length data of the packet and the intended address. For read response packet 2000B, command 2010 may indicate “PM response” with the intended address and the read data. CRC 2016 may indicate the full Ethernet frame. Address 2012 may correspond to the persistent memory's address.
For write packet 2000C, command 2010 may indicate a “PM write” with length data of the packet, the intended address, and the write data. For write acknowledgement packet 2000D, command 2010 may indicate a “PM write acknowledgement” and the intended address.
In various embodiments, compression and/or decompression may be utilized and, based on the packets, the same compression and/or decompression algorithm may be utilized for both the read initiator and the target. Compressed data may be inflated at the source and written within cache.
In certain embodiments, after data arrives within cache coherent switch on chip 1102 from the network (e.g., via NIC 1180), the data is provided to CSM 1150 to be decrypted and/or decompressed. Once the data is decrypted and/or decompressed, such data is then provided to other components through one or more ports of cache coherent switch on chip 1102. Additionally, when data is provided to cache coherent switch on chip 1102 to be provided to the network via NIC 1180, CSM 1150 may first encrypt and/or compress such data before memory buffering and/or providing such data to NIC 1180 (and, thus, the network).
In a certain instance, server 1242B may wish to share one or more of memories 1214F-J with server 1242A. A driver running within server 1242B may pin such memory through a registration routine and may provide an access key to server 1242A for access to the respective memory. Server 1242A may then access the shared memory via CXL protocol memory commands.
In another instance, server 1242B may share read/write caches with server 1242A. When recalling cached data, server 1242A may first check if the data is available locally. If the data is not available locally, a request for cached data is provided to server 1242B. Server 1242B may then provide the requested cached data either from a cache within memories 1214F-I of server 1242B or from memory 1214J communicatively coupled to microprocessor 1204B.
In other embodiments, two or more servers may be a part of the system. A local server may determine that requested data is not within its own buffer and may then communicate requests for the buffer data to each of the various servers. The various servers may provide erasure code, accordingly to the techniques described herein (e.g., within
In the embodiment of
Bridge 1354A may include a plurality of virtual function assignments 1396A-C. Port 1316 may be coupled to device 1328 via bridge 1354A. Port 1316 may include a plurality of P2P bridges 1386A-D. Each virtual function 1396 may be associated with a corresponding P2P bridge 1386. Each virtual function 1396 may include address remap logic. In certain embodiments, port 1316 may implement physical function assignment logic to control processor 1398. Due to the matched virtual functions 1396 of bridge 1354A to P2P bridges 1386 of port 1316, device 1328 may be associated with a plurality of roots (e.g., multi-roots). The configuration of system 1300A may be utilized for single root devices and may provide for the implementation of multi-root devices while providing the security and isolation of separate virtual hierarchies.
In the embodiment of
As described herein, cache coherent switch on chip 1502 may be configured to assign one or more resources from the resource pool to applications on demand. When the application no longer requires the assigned resources, the resources may be reallocated available for other applications.
Each of server racks 1666A-D may include their respective cache coherent switch on chips. Resource clusters may be created from devices communicatively coupled to the respective cache coherent switch on chips within a server rack (e.g., within one of server racks 1666A to D), from devices communicatively coupled via Ethernet 1668, from devices communicatively coupled via Internet 1670, and/or communicatively coupled via another technique. Accordingly, the cache coherent switch on chip disclosed herein allows for the creation of any resource cluster within a system, within a server rack, and across the server racks, creating completely fungible resources connected via a high speed CXL network or CXL protocol over fabric.
Erasure code accelerator 1782 may provide redundancy for data stored in persistent memory, non-volatile memory, random access memory, and/or other such memory communicatively coupled to cache coherent switch on chip 1702 or across a network that cache coherent switch on chip 1702 is communicatively coupled to with other cache coherent switch on chips.
Thus, erasure code accelerator 1782 may be communicatively coupled to processor 1726 and/or to memory or storage communicatively coupled to ports 1720/1722. In situations where erasure code accelerator 1782 is communicatively coupled to processor 1726, erasure code accelerator 1782 may perform read/write requests addressed to processor 1726. Erasure code accelerator 1782 thus stripes data across one or more non-volatile memory on writes and reconstructs data from such memory during reads. In the event of a non-volatile memory failure, erasure code accelerator 1782 may support reconstruction of any lost data.
In certain embodiments, cache coherent switch on chip 1702 may receive a write data flow. For a write data flow received by cache coherent switch on chip 1702, a check may be performed to determine whether the write data is assigned a virtual end point (e.g., a memory or I/O device) in a virtual hierarchy. If the write is for the virtual end point, fabric 1776 may provide the data to processor 1726. Processor 1726 may then provide the write request to erasure code accelerator 1782, identifying the port associated with the request and the erasure code technique for use. Data may then read from various CXL protocol ports of cache coherent switch on chip 1702, allowing for erasure coding to be accordingly performed by erasure code accelerator 1782 by modifying the data and recalculating the erasure coded data. The modified erasure coded data is then written to the respective CXL port (e.g., the ports where the data is read from the various CXL protocol ports). Such a technique may conserve processing resources by offloading erasure coding to erasure code accelerator 1782.
Erasure code accelerator 1782 may also provide a read data flow. In a certain embodiment, ingress logic (e.g., for a read request from a port of cache coherent switch on chip 1702) determines whether the read data flow has erasure code implemented. If erasure code has been implemented, the read request may be provided to processor 1726. Processor 1726 may then provide the read request to erasure code accelerator 1782. The read request may identify the port (and, thus, the device communicatively coupled to the port) where the read request was received. The requested read data may then read from various CXL protocol ports of cache coherent switch on chip 1702, allowing for erasure coding to be accordingly performed by erasure code accelerator 1782 to prepare new erasure coded data. The erasure coded data is then provided back to the respective requesting CXL port.
The various accelerators of cache coherent switch on chip 1702 (e.g., compression, security, erasure coding, and/or other such accelerators) and processor 1726 of cache coherent switch on chip 1702 may be utilized for provisioning of computational storage services (CSSes) to applications running on host CPUs (e.g., CPUs of the greater system containing cache coherent switch on chip 1702). For example, processor 1726 and CSM modules may serve as computational storage processors (CSPs) to provide CSSes to attached hosts. Processor 1726 may also be utilized as the host in computational storage use cases, orchestrating data movement and running of CSSes. In certain embodiments, processor 1726 may offload batch processing of CSS commands from the host CPUs.
In various embodiments,
System 1800, including ports 1802A-P and cross points 1804A-I, form a switch mesh network. System 1800's topology includes ports 1802 disposed on the perimeter of the die of the switch mesh network of system 1800. Cross points 1804 may form the nodes of a switch mesh network and be communicatively coupled to certain portions of communication interfaces 1812 (e.g., referred to as “cross links”). Communication interfaces 1812 may be, for example, 512@1 gigahertz interfaces. As communication interfaces 1812 may be bidirectional, such interfaces may actually be 2×512@1 gigahertz interfaces. The configuration of system 1800 allows for a plurality of links between points (e.g., ports and/or cross points 1804) of system 1800.
In various embodiments, the instantaneous bandwidth of system 1800 may be determined by summing the bandwidth of all the links between cross points 1804. System 1800 includes cross-wise communication interfaces 1812C and 1812D as well as 1812A and 1812B between cross points 1804G and 1804C and between 1804E and 1804A (the cross points on the edge corners of the grid array), respectively. Such cross-wise communication interfaces 1812 reduces the average hop count (the average number of cross points 1804 that a signal communicated within system 1800 would encounter from an input port to an output port) from a normal grid array for signals in communication within system 1800.
Cross-wise communication interfaces 1812 allows for effective overspeed for certain signals communicated within system 1800. In certain embodiments, such overspeed may be close to 2× overspeed. Furthermore, cross-wise communication interfaces 1812 reduces potential for path conflicts. In certain such embodiments, the longest path between cross points is that of two hops, as long as all cross-links are able to receive and send signals. In certain embodiments, the following rules may be applied in order so that the longest path between cross points (e.g., for signals communicated within the mesh network) is that of two hops: 1) If the destination is on the same cross point, the path has zero hops, 2) If the destination is on an adjacent cross point, the path is a single hop directly to that cross point, 3) A two hop path between array corner cross points in the same row, follows the row, 4) A two hop path between array corner cross points in the same column, follows the column, 5) A two hop path from a corner cross point to a node adjacent to the opposite corner cross point takes its first hop to the opposite corner cross point, 6) A two hop path from a node at the center of its row or column to a destination homed at the center of its row or column goes to the array center for its first hop, and 7) A two hop path from a cross point at the center of its row or column to a destination homed at an array corner cross point goes to the array diagonally opposite its destination's cross point for its first hop.
Other configurations of input and output ports (e.g., location and/or quantity) may be utilized for various cross points, including cross points that are not corner cross points. Thus, for example, row center and column center cross points (e.g., cross points 1804B, 1804D, 1804F, and 1804H of
Output ports may include one or more first in, first out (FIFO) queues to provide control of data outputted by the output ports (e.g., for traffic control of signals communicated). Such FIFO queues may be any appropriate size for stage flow control, such as a depth of 2 to 64, inclusive (e.g., may contain 2 to 64 signals and/or flits). In various embodiments, certain output ports may include different sized FIFO queues, depending on expected traffic. For example, FIFO queues at the station outputs (e.g., output ports that are communicatively coupled to one or more ports 1802) may be increased in size to absorb transient output port connections.
In various embodiments, input and output ports may be implemented in pairs, with an odd lane and an even lane. Signals may be allocated to either the odd lane or the even lane throughout communications within the system (e.g., within the fabric). Thus, paired inputs may communicate corresponding odd and even signals. Paired outputs may communicate corresponding odd and even signals as well. An even input may only feed an even output, and vice versa. In various embodiments, loopback connections (not shown) may be present from input to output to support communications between two bifurcated ports in the same station.
In various embodiments, a multiplexer and arbiter may be present at each cross point output. The arbiter round robins among the FIFO queues based on several criteria. The head of the FIFO queue (e.g., the oldest data entry within a queue) that wins an arbitration event is selected and clocked into an output register. The head of a FIFO queue is eligible to compete in an arbitration round if there is sufficient room in the output FIFO queues of the link partner cross point (e.g., if the associated credit register is greater than 0). If any of the FIFO queues are more than half full (e.g., more than half of their capacity is used), the arbiter rounds among those FIFO queues that are more than half full and pass the credit test (e.g., that the destination buffer has free data space). Otherwise, it rounds among those FIFO queues that are not empty and whose heads pass the credit test. If a FIFO queue's head fails a credit test, the FIFO queue is blocked until a credit grant is received.
In certain embodiments, a credit system may be utilized for communication of signals and/or flits. Each cross point output port may include a set of credit registers—one credit register for each output of the corresponding linked cross point (e.g., for output port 2008B, one each for output ports 2014A-C) and the FIFO queue for the input-output port pair of the cross point (e.g., the input-output pair of input port 2006B and output port 2008B, per the prior example). The initial credit in each register is equal to the queue depth of the FIFO queue. When a flit or a signal is provided to a cross point, the input port may receive the flit and accordingly forward the flit to the appropriate output port for storage within the FIFO queue of the output port before the flit and/or signal is provided to the next cross point (e.g., output ports 2008 and 2014 may each include their own corresponding FIFO queues).
The register of the output port is decremented when a flit or a signal that will be stored in the associated FIFO queue of a destination output port (e.g., for output port 2008B, a flit that will be stored within output port 2014B) is forwarded and incremented when a credit grant is provided to the FIFO queue of the forwarding output port (e.g., output port 2008B) from the linked partner cross point (e.g., cross point 2004).
In certain embodiments, a flit is forwarded if there is a positive credit balance in the credit register for the corresponding cross point's output FIFO queue in which it will be stored when forwarded. After forwarding, the flit is entered into the FIFO queue at the corresponding output port of the recipient cross point (e.g., output port 2008B may forward a flit that may be stored within the FIFO queue of, depending on the destination, output port 2014A, B, or C of cross point 2004). The flit will then exit the corresponding FIFO queue and is clocked into the output register, to be communicated onward. In response, a credit grant for the FIFO queue where the flit has been communicated onward is provided back to the previous stage's cross point (e.g., if output port 2014B received a flit from output port 2008B and has communicated a flit onward, a credit grant for the FIFO queue of output port 2014B may then be provided to output port 2008B). A plurality of cross point output ports may forward flits from the same cross point input port in the same cycle. Therefore, within a cross point, separate circuitry may be utilized for each output port's credit grant, which may be communicatively coupled to the corresponding output port of the associated cross point (e.g., as illustrated in communicative circuitry 2028, which may provide credit grants from output ports 2014A-C to corresponding FIFO queues 2010A-C of output port 2008B). Such a configuration may decrease signal congestion within the cross link.
In certain situations, congestion into a cross point output port occurs when the cross point (e.g., the input ports of the cross point) receives traffic faster than can be drained into the cross point output ports. In certain embodiments, the cross point output queues may be sized to absorb these bursts without filling for at least most circumstances.
If a cross point's output queue is filled up, a switch on chip may be configured to block traffic of certain characteristics (e.g., 2 hop traffic, where signals pass through system 1800 may enter via one cross point, pass through an intermediate cross point, and exit through a third cross point). Alternatively, in certain embodiments, XON/XOFF (“transmit on” and “transmit off”) feedback, based on the depth of the output queues, may be utilized. Thus, for example, when the depth of an individual FIFO queue exceeds 50% of its capacity, an XOFF is multicast to the cross links which provide traffic to the associated input port of the output port with FIFO queue exceeding 50% (e.g., the input port on the cross link of the output port with FIFO queue exceeding 50%). When the total queue depth at the output port falls below the level that can be drained according to a target latency, an XON is broadcast. In certain embodiments, a minimum time requirement between XON and XOFF may be implemented, to provide hysteresis.
In certain embodiments, when the ports of cross links are bifurcated, 4 ports may be targeted by 16 ports, increasing the likelihood of congestion. Indeed with 16 ports targeting 4 ports instead of a single port, the peak transfer rate is quadruple that of capacity. Thus, in such an embodiment, the following rules may be implemented imposed on the schedulers in the source stations (where source stations are defined as 1×4, 2×4, 3×4, 4×4, 1×8, 2×8, and/or 1×16 bifurcated CXL/PCIe ports): 1) An 8 port cross link (in the example above) may be sent a flit only once every other cycle and 2) A 4 port cross link (in the example above) may be sent a flit only once every 4th cycle.
In such an embodiment, for cross links/ports on the edges of switch on chips that provide traffic to other switches, traffic to other stations may be blocked unless there is a technique for bypassing the traffic blocked by XOFF to such stations. Such a technique may include: 1) Flow control or valid/accepted handshaking is performed at fabric ingress between station and fabric ingress cross points and at every stage between the ingress's scheduler and the fabric ingress. 2) When XOFF is asserted at a fabric ingress cross point, the pipeline between the station's scheduler and the cross point is halted if a flit targeting a port provided with an XOFF command is seen by the cross point. 3) The station implements pipeline shadow registers so that traffic blocked by an XOFF port can be bypassed by traffic to other destinations. When an XOFF is received, flits that target the XOFF port are shunted into shadow registers at every pipeline stage. Flow to other stations may then be resumed, in some embodiments, after a lag to refill the pipeline. 4) The shadow pipelines are cleared by forwarding from them at a fraction of line rate during XOFF. The fractional amount (e.g., ¼ or ⅛) may minimize congestion spreading. 5) A plurality of shadow pipeline registers may be implemented to allow handling of several concurrent XOFFs.
Accordingly, output queues may be structured to support bypassing and end to end flow control may be implemented to avoid fully filling the egress queues of a station (e.g., a cross link). In certain embodiments, the input ports of a station may include Virtual Input Queues, which may be in common memory pools per message class. XON/XOFF flow control (e.g., implemented as a control module within the full system and/or within each switch on chip and/or provided within control logic within, for example, a fabric manager) may then both manage the congestion and at the same time manage egress queues to prevent overflowing. In certain embodiments, XON/XOFF flow control may not require a credit system and the required egress queue space may be minimized.
The basic principle of XON/XOFF is to signal XOFF when there is just enough room in the queue to hold all the traffic that can arrive during the flow control loop latency (e.g., the time for the XOFF to reach the source ports to shut down traffic and for that traffic already in flight to arrive). XON is signaled in time for flows to resume before the queues drain completely, starving the outputs.
XON/XOFF thresholds may be independently set per station, switch on chip, port, and/or other components. XON/XOFFs may also be provided to FIFOs queues, as described herein. Additionally or alternatively, a separate data path (e.g., a data path 16 bits wide) may be implemented to broadcast and multicast XON/XOFF messages. The XON/XOFF message structure for a station XON/XOFF includes data directed to: 1) Validity, 2) Hop Count, 3) Source Station, 4) Source Port, 5) CXL memory data, 6) CXL cache data, and 7) PCIe data.
In certain systems, an XON/XOFF broadcast follows configured signal routes in reverse along the configured source cross point to destination cross point paths. When a broadcast XON/XOFF flit arrives in a cross point from an attached station, the flit is forwarded through every port of the cross point. When an XON/XOFF flit arrives in a cross point from a cross point to cross point link, its HopCount bit is set and the message is forwarded only to ports that fabric routing tables use to reach the station issuing the XON/XOFF. In general, the flit will be forwarded out all ports except those leading back towards the cross point from which it came. When a flit arrives in a cross point with its HopCount bit set, it is forwarded only to attached stations.
When a single station output port FIFO queue crosses the threshold for XON or XOFF, the cross point sends an XON/XOFF, respectively, flit in which all classes are turned on or off to the output port that feeds the output port whose FIFO queue depth has just crossed the threshold. At each hop, the message is copied into output queues for the attached stations.
In certain embodiments, specific ingress architecture may be provided from queue reader and scheduler stages forward to the fabric interface. For example, flits may be packed so that the entire flit has a single destination (e.g., a specific memory bank) and may be exchanged at 2 Gigahertz. When read for packing, queues may be read up to 4 messages deep per cycle, one per memory bank, to get sufficient message content to fill a flit. When a data header message is found when packing, the data may be packed at the next opportunity or can be held back to be sent as an all data flit. Pipeline stages from the queue reader or packer forward to the fabric interface may include shadow registers to allow bypassing of flits blocked by XOFF flow control.
In certain embodiments, the systems described herein may be utilized for point-to-multipoint communications. Thus, for example, a specific NOC may be utilized to broadcast data to various other components of the systems described herein. Additionally or alternatively, single NOCs (e.g., that of system 1800) may broadcast data from a singular port or cross point to a plurality of other ports and/or cross points.
Any of the disclosed embodiments may be embodied in various types of hardware, software, firmware, computer readable media, and combinations thereof. For example, some techniques disclosed herein may be implemented, at least in part, by non-transitory computer-readable media that include program instructions, state information, etc., for configuring a computing system to perform various services and operations described herein. Examples of program instructions include both machine code, such as produced by a compiler, and higher-level code that may be executed via an interpreter. Instructions may be embodied in any suitable language such as, for example, Java, Python, C++, C, HTML, any other markup language, JavaScript, ActiveX, VBScript, or Perl. Examples of non-transitory computer-readable media include, but are not limited to: magnetic media such as hard disks and magnetic tape; optical media such as flash memory, compact disk (CD) or digital versatile disk (DVD); magneto-optical media; and other hardware devices such as read-only memory (“ROM”) devices and random-access memory (“RAM”) devices. A non-transitory computer-readable medium may be any combination of such storage devices.
In the foregoing specification, various techniques and mechanisms may have been described in singular form for clarity. However, it should be noted that some embodiments include multiple iterations of a technique or multiple instantiations of a mechanism unless otherwise noted. For example, a system uses a processor in a variety of contexts but can use multiple processors while remaining within the scope of the present disclosure unless otherwise noted. Similarly, various techniques and mechanisms may have been described as including a connection between two entities. However, a connection does not necessarily mean a direct, unimpeded connection, as a variety of other entities (e.g., bridges, controllers, gateways, etc.) may reside between the two entities.
In the foregoing specification, reference was made in detail to specific embodiments including one or more of the best modes contemplated by the inventors. While various embodiments have been described herein, it should be understood that they have been presented by way of example only, and not limitation. For example, some techniques and mechanisms are described herein in the context of fulfillment. However, the disclosed techniques apply to a wide variety of circumstances. Particular embodiments may be implemented without some or all of the specific details described herein. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the techniques disclosed herein. Accordingly, the breadth and scope of the present application should not be limited by any of the embodiments described herein, but should be defined only in accordance with the claims and their equivalents.
This patent document claims the benefit and priority of U.S. Provisional Patent Application No. 63/223,045 to Shah et al., filed on Jul. 18, 2021, and entitled “Disaggregated servers and virtual resource appliance to compose an application server by allocating and deallocating the components from the pool of volatile memory, persistent memory, solid state drives, input/output devices, artificial intelligence accelerators, graphics processing units, FPGAs and domain specific accelerator components via CXL connected to cache coherent switch SoC and composable management software,” which is hereby incorporated by reference in its entirety for all purposes.
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