Patent Application
20150162321
As used herein, the phrase “group III-V” refers to a compound semiconductor including at least one group III element and at least one group V element. By way of example, a group III-V semiconductor may take the form of a III-Nitride semiconductor. “III-Nitride” or “III-N” refers to a compound semiconductor that includes nitrogen and at least one group III element such as aluminum (Al), gallium (Ga), indium (In), and boron (B), and including but not limited to any of its alloys, such as aluminum gallium nitride (AlxGa(1-x)N), indium gallium nitride (InyGa(1-y)N), aluminum indium gallium nitride (AlxInyGa(1-x-y)N), gallium arsenide phosphide nitride (GaAsaPbN(1-a-b)), aluminum indium gallium arsenide phosphide nitride (AlxInyGa(1-x-y)AsaPbN(1-a-b)), for example. III-N also refers generally to any polarity including but not limited to Ga-polar, N-polar, semi-polar, or non-polar crystal orientations. A III-N material may also include either the Wurtzitic, Zincblende, or mixed polytypes, and may include single-crystal, monocrystalline, polycrystalline, or amorphous structures. Gallium nitride or GaN, as used herein, refers to a III-N compound semiconductor wherein the group III element or elements include some or a substantial amount of gallium, but may also include other group III elements in addition to gallium.
In addition, as used herein, the phrase “group IV” refers to a semiconductor that includes at least one group IV element such as silicon (Si), germanium (Ge), and carbon (C), and may also include compound semiconductors such as silicon germanium (SiGe) and silicon carbide (SiC), for example. Group IV also refers to semiconductor materials which include more than one layer of group IV elements, or doping of group IV elements to produce strained group IV materials, and may also include group IV based composite substrates such as single-crystal or polycrystalline SiC on silicon, silicon on insulator (SOI), separation by implantation of oxygen (SIMOX) process substrates, and silicon on sapphire (SOS), for example.
It is noted that, as used herein, the terms “low voltage” or “LV” in reference to a transistor or switch describes a transistor or switch with a voltage range of up to approximately fifty volts (50V). It is further noted that use of the term “midvoltage” or “MV” refers to a voltage range from approximately fifty volts to approximately two hundred volts (approximately 50V to 200V). Moreover, the term “high voltage” or “HV,” as used herein, refers to a voltage range from approximately two hundred volts to approximately twelve hundred volts (approximately 200V to 1200V), or higher.
In power management applications where normally off characteristics of power devices are advantageous, a depletion mode (normally on) power transistor having desirable on-state characteristics, such as a low on-resistance, can be implemented in combination with a low voltage (LV) enhancement mode (normally off) transistor to produce an enhancement mode composite power switch. For example, a III-Nitride or other group III-V power field-effect transistor (FET) or high electron mobility transistor (HEMT) may be implemented in combination with an LV silicon FET to provide a high performance composite switch.
Careful selection of the power transistor and LV transistor used to form the composite switch can result in a rugged switch capable in principle of tolerating high noise and high voltage spike environments. However, in conventional implementations, the gate of the LV enhancement mode transistor typically remains susceptible to damage as a result of an electrostatic discharge (ESD) event. Consequently, conventional composite power switches can be vulnerable to premature failure due to ESD caused damage, which may be incurred during device fabrication and assembly, for example.
The present disclosure is directed to a composite power device with ESD protection clamp, substantially as shown in and/or described in connection with at least one of the figures, and as set forth more completely in the claims.
The following description contains specific information pertaining to implementations in the present disclosure. One skilled in the art will recognize that the present disclosure may be implemented in a manner different from that specifically discussed herein. The drawings in the present application and their accompanying detailed description are directed to merely exemplary implementations. Unless noted otherwise, like or corresponding elements among the figures may be indicated by like or corresponding reference numerals. Moreover, the drawings and illustrations in the present application are generally not to scale, and are not intended to correspond to actual relative dimensions.
As noted above, in power management applications where normally off characteristics of power devices are advantageous, a depletion mode (normally on) power transistor having desirable on-state characteristics, such as a low on-resistance, can be implemented in combination with a low voltage (LV) enhancement mode (normally off) transistor to produce an enhancement mode composite power switch. For example, a III-Nitride or other group III-V power field-effect transistor (FET) or high electron mobility transistor (HEMT) may be implemented in combination with an LV silicon FET to provide a high performance composite switch.
As further shown in
Several examples of such cascoded III-Nitride switches are disclosed in U.S. Pat. No. 8,017,978, entitled “Hybrid Semiconductor Device”, filed on Mar. 10, 2006, and issued on Sep. 13, 2011; U.S. Pat. No. 8,084,783, entitled “GaN-Based Device Cascoded with an Integrated FET/Schottky Diode Device”, filed on Nov. 9, 2009, and issued on Dec. 27, 2011; U.S. patent application Ser. No. 13/433,864, entitled “Stacked Composite Device Including a Group III-V Transistor and a Group IV Lateral Transistor”, filed on Mar. 29, 2012, and published as U.S. Patent Application Publication Number 2012/0256188 on Oct. 11, 2012; U.S. patent application Ser. No. 13/434,412, entitled “Stacked Composite Device Including a Group III-V Transistor and a Group IV Vertical Transistor”, filed on Mar. 29, 2012, and published as U.S. Patent Application Publication Number 2012/0256189 also on Oct. 11, 2012; and U.S. patent application Ser. No. 13/780,436, entitled “Group III-V and Group IV Composite Switch”, filed on Feb. 28, 2013, and published as U.S. Patent Application Publication Number 2013/0240898 on Sep. 19, 2013. The above identified patents and patent applications are hereby incorporated fully by reference into the present application.
In order to make conventional composite power switch 100 capable of operating reliably in power management systems, where there are typically high noise and high voltage spikes present, the cascode configuration shown in
Examples of a cascoded device incorporating such optimization are disclosed in U.S. Pat. No. 8,766,375, entitled “Composite Semiconductor Device with Active Oscillation Prevention” filed on Mar. 9, 2012, and issued on Jul. 1, 2014; U.S. patent application Ser. No. 13/419,820, entitled “III-Nitride Transistor with Passive Oscillation Prevention”, filed on Mar. 14, 2012, and published as U.S. Patent Application Publication Number 2012/0241820 on Sep. 27, 2012; U.S. patent application Ser. No. 13/415,779, entitled “Composite Semiconductor Device with Turn-On Prevention Control”, filed on Mar. 8, 2012 and published as U.S. Patent Application Publication Number 2012/0241819 also on Sep. 27, 2012; and U.S. patent application Ser. No. 13/416,252, entitled “High Voltage Composite Semiconductor Device with Protection for a Low Voltage Device”, filed on Mar. 9, 2012, and published as U.S. Patent Application Publication Number 2012/0241756 also on Sep. 27, 2102. The above identified patent and patent applications are hereby incorporated fully by reference into the present application.
Despite the advantages provided by conventional composite power switch 100, gate 126 of LV silicon transistor 120 typically remains susceptible to damage as a result of an electrostatic discharge (ESD) event. As a result, composite gate 106 provided by gate 126 of LV silicon transistor is susceptible to such damage, rendering conventional composite power switch 100 vulnerable to premature failure due to ESD induced damage, which may be experienced during device fabrication and/or assembly and/or packaged product handling, for example.
The present application is directed to implementations of normally off (enhancement mode) composite power devices configured so as to reduce or substantially prevent ESD induced damage. In various implementations, an ESD protection clamp may be utilized to protect a gate of an LV transistor, and thus the composite gate of the composite power device that is provided by the gate of the LV transistor, from ESD related damage or failure.
Referring to
As shown in
It is noted that, in high power and high performance circuit applications, group III-V transistors, such as transistors fabricated from III-Nitride materials, are often desirable for their high efficiency and high voltage handling capability. As noted above in the Definition section, III-Nitride materials include, for example, gallium nitride (GaN) and its alloys such as aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN). These III-Nitride materials are semiconductor compounds having a relatively wide, direct bandgap and can enable high breakdown fields, and the creation of a two-dimensional electron gas (2DEG) that exhibits high conduction electron mobility. As a result, III-Nitride materials such as GaN are used in many microelectronic applications as depletion mode power FETs and HEMTs.
Normally on power transistor 210 may be such a III-Nitride or other group III-V based power transistor, and may be implemented as a depletion mode insulated-gate FET (IGFET), a junction FET (JFET), an accumulation mode FET (AccuFet), or as a heterostructure FET (HFET) or HEMT, for example. In one implementation, normally on power transistor 210 may take the form of a depletion mode metal-insulator-semiconductor HFET (MISHFET), such as a metal-oxide-semiconductor HFET (MOSHFET). According to one implementation, for example, normally on power transistor 210 may be a high voltage (HV) transistor, as defined above in the Definition section of the present application. Thus, normally on power transistor 210 can take the form of an HV group III-V transistor such as an HV group III-V FET or HEMT.
Normally off LV transistor 220 may be implemented as an enhancement mode LV group IV transistor, such as an enhancement mode silicon transistor, for example. According to one implementation, normally off LV transistor 220 may be a silicon MISFET or MOSFET. However, in other implementations, normally off LV transistor 220 may include any suitable group IV material, such as silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), or a strained group IV element or compound, for example. In some implementations, as shown in
The combination of normally on power transistor 210 and normally off LV transistor 220 provides composite power device 200, which according to the implementation shown in
In some implementations, ESD protection clamp 230 may be a group IV diode, such as a silicon PN junction diode, for example. According to the exemplary implementations shown in
As shown in
In various implementations of the present disclosure, ESD protection clamp 230 is configured such that the sum of the breakdown voltage of ESD protection clamp 230 and the current-resistance (IR) drop across ESD protection clamp 230 during an ESD event is less than the breakdown voltage of gate 226 of normally off LV transistor 220. At the same time, the breakdown voltage of the ESD protection clamp 230 is designed to be greater than the maximum rated operating voltage of gate 226. In various implementations of the present disclosure, ESD protection clamp 230 is configured such that normally off composite power device 200 is capable of surviving ESD test standards as characterized by the Human-Body Model (HBM) and Machine Model (MM), as known in the art. For example, ESD protection clamp may be configured to enable normally off composite power device 200 to survive HBM of greater than or approximately equal to 2kV and to survive MM of greater than or approximately equal to 500V. The present disclosure is in marked contrast to previously used gate protection schemes for III-V devices, where a protection diode or a protection clamp may have been utilized to protect against voltage spikes which exceed the safe operation of the group III-V device gate generated by a gate driver coupled to the composite gate of the composite power device. For example, the gate driver protection scheme is generally limited to protection against voltages up to about 10 volts. However, the ESD protection clamp of the present disclosure protects against much higher voltages from 500 volts to about 2000 volts, as stated above, though the clamping voltage is designed to be less than the safe dielectric capability of the LV enhancement mode device gate, typically less than 20 volts. It is noted that ESD protection clamp 230 may not be implemented as a single component, but rather may include several components, as discussed above, in order to meet the design requirements described above.
Continuing to
As shown in
Composite power device 300 including normally on power transistor 310, normally off LV transistor 320, and ESD protection clamp 330 corresponds in general to composite power device 200 including normally on power transistor 210, normally off LV transistor 220, and ESD protection clamp 230, in
However, in contrast to the implementation shown in
As noted above, in various implementations of the present disclosure, ESD protection clamp 330 is configured such that the sum of the breakdown voltage of ESD protection clamp 330 and the IR drop across ESD protection clamp 330 during an ESD event is less than the breakdown voltage of gate 326 of normally off LV transistor 320. At the same time, the breakdown voltage of ESD protection clamp 330 is designed to be greater than the maximum rated operating voltage of gate 326. In various implementations of the present disclosure, ESD protection clamp 330 is configured such that normally off composite power device 300 is capable of surviving ESD test standards as characterized by HBM of greater than or approximately equal to 2kV and to MM of greater than or approximately equal to 500V. It is noted that ESD protection clamp 330 may not be implemented as a single component, but rather may include several components, as discussed above, in order to meet the design requirements described above.
Moving to
As shown in
Composite power device 400 including normally on power transistor 410, normally off LV transistor 420, and ESD protection clamp 430 corresponds in general to composite power device 200 including normally on power transistor 210, normally off LV transistor 220, and ESD protection clamp 230, in
However, in contrast to the implementation shown in
Exemplary techniques for integrating cascoded III-Nitride and silicon based switches are described in U.S. Pat. No. 7,915,645, entitled “Monolithic Vertically Integrated Composite Group III-V and Group IV Semiconductor Device and Method For Fabricating Same”, filed on May 28, 2009, and issued on Mar. 29, 2011; U.S. patent application Ser. No. 14/472,974, filed on Aug. 29, 2014, entitled “Monolithic Integrated Composite Group III-V and Group IV Semiconductor Device and IC”; U.S. patent application Ser. No. 12/653,236, filed on Dec. 10, 2009, entitled “Monolithic Integrated Composite Group III-V and Group IV Semiconductor Device and Method for Fabricating Same”; U.S. patent application Ser. No. 12/174,329, filed on Jul. 16, 2008, entitled “III-Nitride Device”; U.S. patent application Ser. No. 11/999,552, filed on Dec. 4, 2007, entitled “Monolithically Integrated III-Nitride Power Converter,” and issued as U.S. Pat. No. 7,863,877 on Jan. 4, 2011; U.S. patent application Ser. No. 12/928,103, filed on Dec. 3, 2010, entitled “Monolithic Integration of Silicon and Group III-V Devices”; and U.S. patent application Ser. No. 14/327,495, filed on Jul. 9, 2014, entitled “Monolithic Composite III-Nitride Transistor with High Voltage Group IV Enable Switch.” The disclosures in all of the above-identified patent and patent application documents are hereby incorporated fully by reference into the present application.
As noted above, in various implementations of the present disclosure, ESD protection clamp 430 is configured such that the sum of the breakdown voltage of ESD protection clamp 430 and the IR drop across ESD protection clamp 430 during an ESD event is less than the breakdown voltage of gate 426 of normally off LV transistor 420. At the same time, the breakdown voltage of ESD protection clamp 430 is designed to be greater than the maximum rated operating voltage of gate 426. In various implementations of the present disclosure, ESD protection clamp 430 is configured such that normally off composite power device 400 is capable of surviving ESD test standards as characterized by HBM of greater than or approximately equal to 2kV and to MM of greater than or approximately equal to 500V. It is noted that ESD protection clamp 430 may not be implemented as a single component, but rather may include several components, as discussed above, in order to meet the design requirements described above.
From the above description it is manifest that various other implementations of the present inventive concepts are also possible without departing from the scope of those concepts. For example, in some implementations, the normally on power transistor and the normally off LV transistor may be monolithically integrated on a common die, while the ESD protection clamp may be implemented as a discrete diode not monolithically integrated with either transistor.
Thus, the present application discloses normally off (enhancement mode) composite power devices configured so as to reduce or substantially prevent ESD related damage. In various implementations of the present disclosure, an ESD protection clamp may be utilized to protect a gate of a normally off LV transistor, and thus protect the composite gate of the composite power device from ESD related damage or failure Monolithic integration of the ESD protection clamp 330 with LV transistor 320 provides protection from damage due to ESD events during wafer level and die level handling and packaging operations. Moreover, by monolithically integrating the ESD protection clamp with the normally off LV transistor on a common die, the size of the ESD protection clamp can be substantially minimized, thereby advantageously reducing gate capacitance and leakage. Similarly, by monolithically integrating the ESD protection clamp with the normally off LV transistor as well as the normally on power transistor on a common die, the parasitic inductances between the LV and HV devices can be minimized and the matching of the device capacitances can be better controlled.
From the above description it is manifest that various techniques can be used for implementing the concepts described in the present application without departing from the scope of those concepts. Moreover, while the concepts have been described with specific reference to certain implementations, a person of ordinary skill in the art would recognize that changes can be made in form and detail without departing from the scope of those concepts. As such, the described implementations are to be considered in all respects as illustrative and not restrictive. It should also be understood that the present application is not limited to the particular implementations described herein, but many rearrangements, modifications, and substitutions are possible without departing from the scope of the present disclosure.
The present application claims the benefit of and priority to a provisional application entitled “III-Nitride Transistor Cascoded with Diode Protected Silicon MOSFET,” Ser. No. 61/913,533 filed on Dec. 9, 2013. The disclosure in this provisional application is hereby incorporated fully by reference into the present application.
| Number | Date | Country | |
|---|---|---|---|
| 61913533 | Dec 2013 | US |
