Claims
- 1. An integrated semiconductor device, comprising:a first semiconductor device having conductors a second semiconductor device having a substrate and conductors; said conductors on said first semiconductor device being bonded to said conductors on said second semiconductor device to form a unit of said first and second semiconductor devices; said unit having only one substrate; a layer of cement extending from said substrate on said second semiconductor device and surrounding a portion of said first semiconductor device; and a layer of etch-resist on said cement.
- 2. A device as in claim 1, wherein said cement extends between said substrate and said etch-resist and around said conductors and around said semiconductor devices.
- 3. A device as in claim 1, wherein said conductors on said first semiconductor device are coplanar, and said conductors on said second semiconductor device are coplanar.
- 4. A device as in claim 2, wherein said cement forms a structural support from said first semiconductor device to said second semiconductor device.
- 5. A device as in claim 4, wherein said first semiconductor device is a photonic device and said second semiconductor device is a Si device.
- 6. A device as in claim 1, wherein said second semiconductor device includes a GaAs/AlGaAs multiple quantum well modulator and said first semiconductor device includes a Si integrated circuit chip.
- 7. A device as in claim 1, wherein said cement is an epoxy.
- 8. A device as in claim 1, wherein said first semiconductor device includes a plurality of GaAs structures on said substrate of said first semiconductor device, said conductors on said first device including a plurality of terminals on each of said GaAs structures, said second semiconductor device includes a plurality of GaAs structures on said substrate of said second semiconductor device, said conductors on said second device including a plurality of terminals on each of said GaAs structures;said etch-resist being located on the substrate of said first structures and about each of said structures on said first semiconductor device; said terminals of said first structures being bonded to said terminals of said second structures.
REFERENCE TO RELATED APPLICATIONS
This application is a divisional application of pending prior application Ser. No. 08/572,275, filed Dec. 13, 1995 now U.S. Pat. No. 6,048,751, which in turn is a continuation-in-part of U.S. application Ser. No. 08/366,864 filed Dec. 30, 1994 now U.S. Pat. No. 5,578,162, which is a continuation-in-part of divisional U.S. application Ser. No. 08/236,307, file May 2, 1994 now abandoned, and of U.S. application Ser. No. 08/083,742 filed Jun. 25, 1993, now U.S. Pat. No. 5,385,632, all assigned to the same assignee as this application.
US Referenced Citations (2)
Number |
Name |
Date |
Kind |
4783594 |
Schulte et al. |
Nov 1988 |
A |
5488504 |
Worchesky et al. |
Jan 1996 |
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Continuation in Parts (3)
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Number |
Date |
Country |
Parent |
08/366864 |
Dec 1994 |
US |
Child |
08/572275 |
|
US |
Parent |
08/236307 |
May 1994 |
US |
Child |
08/366864 |
|
US |
Parent |
08/083742 |
Jun 1993 |
US |
Child |
08/236307 |
|
US |