Patent Grant
10297745
A magnetic memory cell or device stores information by changing electrical resistance of a magnetic tunnel junction (MTJ) element. The MTJ element typically includes a thin insulating tunnel barrier layer sandwiched between a fixed ferromagnetic layer and a free ferromagnetic layer, forming a magnetic tunnel junction. The resistance state of the MTJ element changes corresponding to that of the magnetic orientation of the free layer relating to the fixed layer, which may be in either a parallel (P) state or an anti-parallel (AP) state. The corresponding electrical resistance between the free layer and the fixed layer in P state is denoted as RP while the corresponding electrical resistance between the free layer and the fixed layer in AP state is denoted as RAP. The performance of an MTJ element is usually characterized by its tunneling magnetoresistance (TMR), which may be calculated using the formula given by (RAP−RP)/RP. For example, a larger TMR ratio facilitates read operations in a magnetic memory cell. Thus, an enhanced TMR is necessary for realizing next-generation magnetic memory cells.
It is desirable to provide a reliable memory device with an enhanced TMR ratio and a method for forming a reliable memory device which eliminates the high temperature concern for the MTJ element. Furthermore, it is also desirable that the process is cost effective and is compatible with logic processing.
Embodiments of the present disclosure generally relate to semiconductor devices and methods for forming a semiconductor device. One embodiment relates to a method of forming a device. The method includes providing a substrate having circuit component formed on its surface. Back-end-of-line (BEOL) processing is performed to form an inter level dielectric (ILD) layer over the substrate. The ILD layer includes a plurality of ILD levels. A magnetic tunneling junction (MTJ) stack is formed in between adjacent ILD levels of the ILD layer. The MTJ stack includes a magnetic fixed layer which includes a synthetic antiferromagnetic (SAF) layer, a composite spacer layer disposed on the SAF layer and a reference layer on the composite spacer layer. The composite spacer layer includes a first non-magnetic (NM) spacer layer, a magnetic (M) spacer layer disposed over the first NM spacer layer and a second NM spacer layer disposed over the M layer. A tunneling barrier layer disposed over the magnetic fixed layer. A magnetic free layer is disposed over the tunneling barrier layer.
Another embodiment relates to a method of forming a device. The method includes providing a substrate having circuit component formed on its surface. Back-end-of-line (BEOL) processing is performed to form an inter level dielectric (ILD) layer over the substrate. The upper ILD layer includes a plurality of ILD levels. A magnetic tunneling junction (MTJ) stack is formed in between adjacent ILD levels of the ILD layer. The MTJ stack includes a bottom electrode with a seed layer thereon. A magnetic fixed layer is disposed on the seed layer. The magnetic fixed layer includes a synthetic antiferromagnetic (SAF) layer, a composite spacer layer disposed on the SAF layer and a reference layer on the composite spacer layer. The composite spacer layer includes a first non-magnetic (NM) spacer layer, a magnetic (M) spacer layer disposed over the first NM spacer layer and a second NM spacer layer disposed over the M layer. A tunneling barrier layer disposed over the magnetic fixed layer. A magnetic free layer is disposed over the tunneling barrier layer. A cap layer is disposed on the magnetic free layer. A top electrode is over the cap layer.
Another embodiment relates to a device. The device includes a substrate having circuit component formed on its surface. An inter level dielectric (ILD) layer is disposed over the substrate. The ILD layer includes a plurality of ILD levels. A magnetic tunneling junction (MTJ) stack is disposed in between adjacent ILD levels of the ILD layer. The MTJ stack includes a magnetic fixed layer which includes a synthetic antiferromagnetic (SAF) layer, a composite spacer layer disposed on the SAF layer and a reference layer on the composite spacer layer. The composite spacer layer includes a first non-magnetic (NM) spacer layer, a magnetic (M) spacer layer disposed over the first NM spacer layer and a second NM spacer layer disposed over the M layer. A tunneling barrier layer disposed over the magnetic fixed layer. A magnetic free layer is disposed over the tunneling barrier layer.
These and other advantages and features of the embodiments herein disclosed, will become apparent through reference to the following description and the accompanying drawings. Furthermore, it is to be understood that the features of the various embodiments described herein are not mutually exclusive and can exist in various combinations and permutations.
The accompanying drawings, which are incorporated in and form part of the specification in which like numerals designate like parts, illustrate preferred embodiments of the present disclosure and, together with the description, serve to explain the principles of various embodiments of the present disclosure.
Embodiments of the present disclosure generally relate to memory cells or devices. In one embodiment, the memory cells are magnetoresistive memory cells. For example, the memory devices may be spin transfer torque magnetoresistive random access memory (STT-MRAM) devices. Other types of memory devices may also be useful. A magnetoresistive memory cell includes a magnetic tunneling junction (MTJ) storage unit. The MTJ storage unit of the present disclosure includes a composite spacer layer that provides sustainable or enhanced TMR at high annealing temperature, for example, 400° C. during back-end-of-line (BEOL) processing. Other suitable types of memory cells may also be useful. Such memory devices, for example, may be incorporated into standalone memory devices including, but not limited to, USB or other types of portable storage units, or ICs, such as microcontrollers or system on chips (SoCs). The devices or integrated circuits (ICs) may be incorporated into or used with, for example, consumer electronic products, or relate to other types of devices.
The MTJ element includes a magnetically fixed layer 113, a tunneling barrier layer 116 and a magnetically free layer 117. In one embodiment, the magnetically fixed layer 113 is disposed below the magnetically free layer 117, forming a bottom pinned pMTJ stack. The magnetic orientation or magnetization of the fixed layer 113 is fixed or pinned in a first perpendicular direction. The term perpendicular direction, for example, refers to the direction of the magnetic field which is perpendicular to the surface of a substrate or perpendicular to the plane of the layers of the MTJ module.
The magnetic fixed layer includes a synthetic antiferromagnetic (SAF) layer. The SAF layer includes first and second magnetic layers 124a and 124b separated by an exchange coupler layer 123. The first and second magnetic layers of the SAF layer have opposite directions of magnetization. A reference layer 115 is disposed over the SAF layer. The reference layer and the SAF layer are separated by a spacer layer 128. As shown, the reference layer has a magnetization which is fixed in the first magnetic direction. The reference layer, for example, defines the magnetic direction of the fixed layer. The SAF layer, for example, pins the magnetization of the reference layer in the first magnetic direction.
As shown, the first perpendicular direction is in an upward direction away from the electrode. Providing the first perpendicular direction which is in a downward direction towards the electrode may also be useful. As for the magnetic orientation or magnetization of the free layer 117, it may be programmed to be in a first or same direction as the fixed layer 113 or in a second or opposite direction as the fixed layer 113.
For example, as shown by structure 111, the magnetic orientation or magnetization of the free layer 117 is programmed to be in the second or anti-parallel direction to the fixed layer 113. The corresponding MTJ electrical resistance between the free layer 117 and the fixed layer 113 is denoted as RAP. Structure 112 illustrates that the magnetic orientation of the free layer 117 is programmed to be in the first or parallel direction to the fixed layer 113. The corresponding MTJ electrical resistance between the free layer 117 and the fixed layer 113 is denoted as RP. The resistance RAP is higher than the resistance RP.
As shown, the SAF layer 213 is disposed on the seed layer. The SAF layer may include a first magnetic layer 213a, a second magnetic layer 213b and an exchange coupling layer 213c. The first and second magnetic layers have opposite directions of magnetization and are separated by the coupling layer 213c. The first magnetic layer may be referred to as a first antiparallel layer (AP1) or first hard layer (HL1) and the second magnetic layer may be referred to as a second antiparallel layer (AP2) or second hard layer (HL2). The first magnetic layer 213a, for example, is disposed on the seed layer 211. The coupling layer 213c is disposed on the first magnetic layer 213a and the second magnetic layer 213b is disposed on the coupling layer 213c. The purpose of the SAF layers is to minimize the stray field arising from AP1 and AP2 through the free layer 217. This maintains higher data retention. As a result, stray magnetic field influences on the free layer 217 are minimized.
The magnetizations of the first and second magnetic layers are “pinned” via the exchange coupling layer 213c. The magnetization or magnetic orientation in the second magnetic layer 213b which is proximate to the free layer 217 acts as a fixed reference to the free layer 217.
The first magnetic layer 213a and the second magnetic layers 213b of the SAF layer 213 may be an alloy magnetic layer or a multilayer. For example, a magnetic layer may be a cobalt-iron-boron (CoFeB) alloy, a cobalt-iron (CoFe) alloy, or a platinum (Pt) alloy. The magnetic layer, for example, may be Co(Fe,Ni)Pt/Pd or CoPt or FePt. In other cases, the magnetic layer may be a multilayer of cobalt/platinum (Co/Pt)n, cobalt/palladium (Co/Pd)m or cobalt/nickel (Co/Ni)x. The first magnetic layer 213a may be thicker than the second magnetic layer 213b. For example, the first magnetic layer 213a may include n layer(s) of Co/Pt, Co/Pd or Co/Ni, and the second magnetic layer 213b may include m layer(s) of Co/Pt, Co/Pd or Co/Ni, wherein n is larger than m. In one embodiment, n and m may be less than 20 layers. The first magnetic layer may be referred to as a first anti-parallel (AP1) layer and the second magnetic layer may be referred to as a second anti-parallel (AP2) layer.
In one embodiment, the first and second magnetic layers of the SAF layer 213 may be arranged in the (111) orientation of a face centered cubic (fcc) lattice structure. Other fcc orientations of the first and second magnetic layers of the SAF layer 213 may also be useful. As for the coupling layer 213c, it may be a non-magnetic conductor layer. For example, the coupling layer 213c may be a ruthenium (Ru) layer. The Ru layer may be sufficiently thin. For example, the coupling layer may be about 4-9 Å thick. Preferably, the coupling layer is about 4 Å thick. Other thicknesses may also be useful. A thin coupling layer facilitates maximizing the exchange coupling field through the first peak of the coupling layer, such as Ru.
As for the spacer layer 214, it is disposed on the SAF layer 213. The spacer layer 214 may be a composite spacer. In one embodiment, the composite spacer layer includes multiple layers. The composite spacer layer includes non-magnetic (NM) and magnetic (M) layers. In one embodiment, the composite spacer layer includes a M layer 214b sandwiched between two NM layers 214a and 214b. The first NM layer 214a may be referred to as a base layer (BL). For example, the composite spacer layer may be a BL/M/NM composite layer. In other embodiments, the composite spacer layer may include a BL 214a and a plurality of M/NM bilayers 214b and 214c. For example, the composite spacer layer may be a (BL)(M/NM)n composite layer, where n is ≥1 and is the number of M/MN bilayers.
In one embodiment, the B layer is proximate to the SAF layer 213, whereas the M spacer layer 214b is distal from the SAF layer 213. The M layer is magnetically coupled to the AP2 layer through the layer 214a. In one embodiment, the NM layer 214c serves as a template enhancer for the polarizer layer. Enhancing the template of the polarizer layer facilitates strong tunneling effect through the tunnel barrier layer 216 and hence, improves the TMR. In addition, the M spacer layer serves as a diffusion barrier. For example, the M spacer layer prevents or reduces diffusion of atoms from the NM spacer layer below to the polarizer layer and the tunneling barrier layer. Furthermore, the use of multiple NM spacer layers separated by at least one M layer reduces the thickness of the NM layers. This also results in reduced diffusion of atoms from the NM spacer to the polarizer layer and the tunneling barrier layer.
The NM layers, including the B layer, may be NM metal layers. In one embodiment, a metal NM layer may be, for example, tantalum (Ta), molybdenum (Mo), tungsten (W), niobium (Nb), ruthenium (Ru), titanium (Ti) or a combination thereof. In a preferred embodiment, a NM spacer layer is a Ta layer. In one embodiment, a NM spacer layer may be an amorphous layer. The thickness of the NM spacer layer should be sufficiently thin to maintain coupling between RL and AP2. The thickness of the NM spacer layer may be, for example, about 0.5-5 Å and preferably about 0.5-4 Å. Other thicknesses may also be useful. The thickness, for example, may depend on the desired coupling strength.
As for a M spacer layer 214b, it may be a Co-based magnetic layer. The Co-based M layer may be a composite M layer with different compositions. In one embodiment, a Co-based M spacer layer is a Co(Fe, Ni)Bx. In a preferred embodiment, the M layer is a CoFeB layer. The M spacer layer is a magnetically continuous amorphous layer. For example, the Co-based layer is a magnetically continuous amorphous layer. To facilitate an amorphous layer, the boron (B) concentration of the Co(Fe, Ni)Bx layer may be and preferably from about 0-40%. As for the concentration of Co of the Co(Fe, Ni)Bx layer, it may vary from about 20-60% The M spacer layer may, in one embodiment, be a monolayer. The M spacer monolayer may be a discontinuous layer, which is loosely packed on the surface of the first spacer layer 214a. The discontinuous second layer 214b allows diffusion of B towards the first spacer layer 214a so that B can be absorbed by the NM spacer layer or layers. The thickness of the M layer should maintain the perpendicular magnetic anisotropy (PMA) of the RL and AP2 layer. For example, the thickness of the M layer may be about 1.0-13 Å and preferably be about 1.0-13 Å. Other thicknesses may also be useful.
In the case where n is greater than one, thinner NM and M layers may be employed. This improves over surface smoothness of the spacer layer and improves coupling to RL as well as enhancing the polarization of RL. This also increases or maximizes the TMR of the MTJ element.
In some embodiments, the different M and NM layers of the spacer layer may be of the same type. For example, the M layers are the same type of M layers and NM layers are of the same type of NM layers. In other embodiments, different M and NM layers may be different types of N and MN layers or a combination of same and different types of layers.
As described, the composite spacer layer 214 is as follows:
Spacer layer=(BL)/(M/NM)n,
where
BL is the base layer and is a non-magnetic (NM) metal layer,
M/NM is the bilayer in which
M is a magnetic layer of the bilayer, and
NM is a non-magnetic metal layer of the bilayer, and
n is the number of bilayers and is ≥1.
In one embodiment, n is from 1 to 5. Providing other numbers of bilayers may also be useful.
In one embodiment, the NM layers of the composite spacer include Ta and the M layers include CoFeB. For example, the composite spacer layer may be Ta/(CoFeB/Ta)n, wherein n is from 1 to 5. The thickness of the NM layers may be about 1 Å while the thickness of the M layers is about 2 Å. Other types and thicknesses of composite spacer layers may also be useful.
In one embodiment, the NM and M spacer layers may be formed by sputtering using separate sputtering processes. In other embodiments, the NM and M spacer layers may be formed by an alloy target including both materials of the NM and M spacer layers. For example, the spacer layers may be formed by co-sputtering. In the case of a Ta/CoFeB/Ta spacer layer, a TaCoFeB alloy target may be used. In one embodiment, the first Ta spacer layer is formed having a thickness of about 0.5-5 Å using Krypton (Kr) gas at 75 W. Alternatively, the first Ta spacer layer may be formed using Xenon (Xe) gas at 75 W. As for the CoFeB second spacer layer, it is formed with a thickness of about 1.0-13 Å using Argon (Ar) gas at 600 W.
The spacer layer 214 governs the growth of the subsequently formed layer. For example, the amorphized first spacer layer 214a, such as Ta, breaks the texture from underneath, for example, the crystallinity of the polarizer layer.
The spacer layer 214 enables the growth of an amorphous layer. Therefore, the subsequently formed layer, e.g., the polarizer layer, is highly disordered, resulting in an enhanced TMR.
The polarizer layer 215 is disposed on the spacer layer 214. The polarizer layer 215 is an amorphous layer. In one embodiment, the polarizer layer 215 may be an amorphized CoFeB layer. The amorphous layer enhances the tunnel magnetoresistance (TMR) effect of the MTJ stack.
The tunneling barrier layer 216 is disposed on the polarizer layer 215. The tunneling barrier layer 216 is a non-magnetic and electrically insulating layer. The tunneling barrier layer 216 may be a metal oxide layer, for example, a crystalline magnesium oxide (MgO) or an amorphous aluminum oxide (Al2O3). Other metal oxides suitable for used as the tunneling barrier layer in the MTJ element may also be useful.
The magnetic free layer 217 is disposed on the tunneling barrier layer 216. The magnetic free layer 217 may be a CoFeB layer. The cap layer 218 is disposed on the free layer 217. The cap layer 218 may be made of Pt, Ru, Ta or other suitable metals. The cap layer 218 protects the underlying free layer 217 and promotes the perpendicular magnetic anisotropy (PMA) in the free layer 217.
As described, the MTJ stack includes a single tunneling barrier layer 216 disposed between the reference layer 215 and magnetic free layer 217. In other embodiments, the MTJ stack may include dual tunneling barrier layers. For example, a first barrier layer 216 may be disposed between the reference layer 215 and magnetic free layer 217 and a second barrier layer (not shown) between the free layer 217 and cap layer 218. Other configurations of tunneling barrier layers may also be useful.
In another embodiment, as shown in
In one embodiment, a tunneling barrier layer 331, similar to the tunneling barrier 216, is disposed on the dual coupling stack while the cap layer 218 is disposed on the tunneling barrier layer. For example, the MTJ stack is a dual tunneling barrier MTJ stack. Providing a single tunneling barrier MTJ stack may also be useful.
In yet another embodiment, as shown in
The composite free layer serves as a magnetic dilution layer for enhancing the perpendicular magnetic anisotropy (PMA) as well as reducing the switching current. Furthermore, the composite free layer also improves the 400° C. thermal budget performance and enables pMTJ process to be compatible with complementary metal oxide semiconductor (CMOS) BEOL process.
For the dual coupling stack, a tunneling barrier layer 331, similar to the tunneling barrier 216, is disposed on the dual coupling stack while the cap layer 218 is disposed on the tunneling barrier layer. For example, the MTJ stack is a dual tunneling barrier MTJ stack. Providing a single tunneling barrier MTJ stack may also be useful.
The pMTJ element includes first and second electrodes 931 and 932. The first electrode 931, for example, may be a bottom electrode while the second electrode 932 may be a top electrode. Other configurations of electrodes may also be useful. In one embodiment, the top electrode 932 of the storage unit 910 is electrically connected to a bit line (BL). The bottom electrode 931 of the storage element is connected to the first cell node 939.
The cell selector unit 940 includes a selector for selecting the memory cell. The selector, for example, may be a select transistor. In one embodiment, the select transistor is a metal oxide semiconductor (MOS) transistor. In one embodiment, the selector is a n-type MOS transistor. The select transistor includes first and second source/drain (S/D) terminals 945 and 946 and a gate or control terminal 944. The S/D terminals, for example, are heavily doped regions with first polarity type dopants, defining the first type transistor. For example, in the case of a n-type transistor, the S/D terminals are n-type heavily doped regions. Other types of transistors or selectors may also be useful.
In one embodiment, the first terminal of the cell selector and the first electrode 931 of the storage unit 910 are commonly coupled at the first cell node 939. For example, the first S/D terminal 945 of the cell selector is coupled to the bottom electrode 931 of the storage unit 910. The second terminal 946 of the cell selector is coupled to a source line (SL). As for the gate terminal 944, it is coupled to a wordline (WL).
As shown, the array includes four memory cells arranged in a 2×2 array. For example, the array is arranged to form two rows and two columns of memory cells. Memory cells of a row are interconnected by a wordline (WL1 or WL2) while memory cells of a column are interconnected by a bitline (BL1 or BL2). A S/D terminal is coupled to a source line (SL1 or SL2). Other suitable cell configurations may also be useful. Although the array is illustrated as a 2×2 array, it is understood that arrays of other sizes may also be useful.
The memory cell is disposed on a substrate 1105. For example, the memory cell is disposed in a cell region of the substrate 1105. The cell region may be part of an array region. For example, the array region may include a plurality of cell regions. The substrate 1105 may include other types of device regions (not shown), such as high voltage (HV) as well as logic regions, including low voltage (LV) and intermediate voltage (IV) device regions. Other types of regions may also be provided.
The substrate 1105, for example, is a semiconductor substrate, such as a silicon substrate. For example, the substrate 1105 may be a lightly doped p-type substrate. Providing an intrinsic or other types of doped substrates, such as silicon-germanium (SiGe), germanium (Ge), gallium-arsenic (GaAs) or any other suitable semiconductor materials, may also be useful. In some embodiments, the substrate 1105 may be a crystalline-on-insulator (COI) substrate. A COI substrate includes a surface crystalline layer separated from a crystalline bulk by an insulator layer. The insulator layer, for example, may be formed of a dielectric insulating material. The insulator layer, for example, is formed from silicon oxide, which provides a buried oxide (BOX) layer. Other types of dielectric insulating materials may also be useful. The COI substrate, for example, is a silicon-on-insulator (SOI) substrate. For example, the surface and bulk crystalline layers are single crystalline silicon. Other types of COI substrates may also be useful. It is understood that the surface and bulk layers need not be formed of the same material.
Front-end-of-line (FEOL) processing is performed on the substrate 1105. The FEOL process, for example, forms n-type and p-type devices or transistors on the substrate 1105. The p-type and n-type device form a complementary MOS (CMOS) device. The FEOL processing, for example, includes forming isolation regions, various device and isolation wells, transistor gates and transistor source/drain (S/D) regions and contact or diffusion regions serving as substrate or well taps. Forming other components with the FEOL process may also be useful.
Isolation regions 1180, for example, serve to isolate different device regions. The isolation regions may be shallow trench isolation (STI) region. To form STI regions, trenches are formed and filled with isolation material. A planarization process, such as chemical mechanical polishing (CMP) is performed to remove excess dielectric material, forming isolation regions. Other types of isolation regions may also be useful. The isolation regions are provided to isolate device regions from other regions.
Device wells (not shown), for example, serve as bodies of p-type and n-type transistors. Device wells are doped wells. Second type doped device wells serve as bodies of first type transistors. For example, p-type device wells serve as bodies of n-type transistors and n-type device wells serve as bodies of p-type transistors. Isolation wells may be used to isolate device wells from the substrate. The isolation wells are deeper than the device wells. For example, isolation wells encompass the device wells. The isolation wells are first type doped wells. For example, n-type isolation wells are used to isolate p-type device wells. Separate implants may be employed to form different doped device wells and isolation wells using, for example, implant masks, such as photoresist masks. The wells, for example, are formed after forming isolation regions.
Gates of transistors are formed on the substrate. For example, layers of the gate, such as gate dielectric and gate electrode, are formed on the substrate and patterned to form the gates 1144. The gate dielectric may be a silicon oxide layer while the gate electrode layer may be polysilicon. The gate electrode may be doped, for example, to reduce sheet resistance. Other types of gate dielectric and gate electrode layers may also be useful. The gate dielectric layer may be formed by thermal oxidation and the gate electrode layer may be formed by chemical vapor deposition (CVD). Separate processes may be performed for forming gate dielectrics of the different voltage transistors. This is due to, for example, different gate dielectric thicknesses associated with the different voltage transistors. For example, high voltage (HV) transistor will have a thicker gate dielectric than a low voltage (LV) transistor.
The gate layers are patterned by, for example, mask and etch techniques. For example, a patterned photoresist mask may be provided over the gate layers. For example, a photoresist layer is formed over the gate layers and lithographically exposed by using a reticle. The photoresist mask layer is developed, forming a patterned photoresist mask with the desired pattern of the reticle. To improve lithographic resolution, an anti-reflective coating (ARC) layer may be provided between the gate electrode layer and the photoresist mask layer. An anisotropic etch, such as a reactive ion etch (RIE) is used to pattern the gate layers to form the gates using the patterned photoresist mask.
Doped contact regions, such as source/drain (S/D) regions and well or substrate taps are formed in exposed active regions of the substrate 1105 after forming the gates. The contact regions are heavily doped regions. Depending on the type of transistor and well tap, the contact regions may be heavily doped n-type or p-type regions. For n-type transistors, S/D regions are heavily doped n-type regions and for p-type transistors, S/D regions are heavily doped p-type regions. For well taps, they are the same dopant type as the well.
A S/D region may include lightly doped diffusion (LDD) and halo regions. A LDD region is a lightly doped region with first polarity type dopants while the halo region is a lightly doped region with second polarity type dopants. For example, the halo region includes p-type dopants for a n-type transistor while the LDD region includes n-type dopants for n-type transistors. The halo and LDD regions extend under the gate. A halo region extends farther below the gate than a LDD region. Other configurations of LDD, halo and S/D regions may also be useful.
Dielectric spacers (not shown) may be provided on the gate sidewalls of the transistors. The spacers may be used to facilitate the formation of halo, LDD and S/D regions. For example, spacers are formed after halo and LDD regions are formed. Spacers may be formed by, for example, forming a spacer layer on the substrate and anisotropically etching it to remove horizontal portions, leaving the spacers on the sidewalls of the gates. After forming the spacers, an implant is performed to form the S/D regions. Separate implants may be employed to form different doped regions using, for example, implant masks, such as photoresist mask. Well taps of the same dopant type as S/D regions are formed at the same time.
As shown, the FEOL processing forms a cell region isolated by an isolation region 1180, such as a STI region. The cell region is for a memory cell. Isolation regions may be provided to isolate columns of memory cells. Other configurations of isolation regions may also be useful. The cell region may include a cell device well (not shown). The cell device well, for example, serves as a body well for a transistor of the memory cell. The device well may be doped with second polarity type dopants for first polarity type transistors. The device well may be lightly or intermediately doped with second polarity type dopants. In some cases, a cell device isolation well (not shown) may be provided, encompassing the cell device well. The isolation well may have a dopant type which has an opposite polarity to that of the cell device well. For example, the isolation well may include first polarity type dopants. The isolation well serves to isolate the cell device well from the substrate. Well biases may be provided to bias the wells.
The cell device well may be a common well for the cell regions in the array region. For example, the cell device well may be an array well. The cell device isolation well may serve as the array isolation well. Other configurations of device and isolation wells may also be useful. Other device regions of the device may also include device and/or device isolation wells.
The memory cell includes a cell selector unit 1140 and a storage unit 1110. The FEOL forms the cell selector unit 1140 in the cell region. The cell selector unit 1140 includes a selector for selecting the memory cell. The selector, for example, may be a select transistor. In one embodiment, the select transistor is a metal oxide semiconductor (MOS) transistor. The transistor, as shown, includes first and second source/drain (S/D) regions 1145 and 1146 formed in the substrate 1105 and a gate 1144 disposed on the substrate between the S/D regions. The first S/D region 1145 may be referred to as a drain region and the second S/D region 1146 may be referred to as a source region. The S/D regions, for example, are heavily doped regions with first polarity type dopants, defining the type of transistor. For example, in the case of a n-type transistor, the S/D regions are n-type heavily doped regions. Other types of transistors or selectors may also be useful.
As for the gate 1144, it includes a gate electrode over a gate dielectric. The gate electrode may be polysilicon while the gate dielectric may be silicon oxide. Other types of gate electrode and gate dielectric materials may also be useful. A gate, for example, may be a gate conductor along a first or wordline direction. The gate conductor forms a common gate for a row of memory cells.
As discussed, a S/D region may include LDD and halo regions (not shown). Dielectric spacers (not shown) may be provided on the gate sidewalls of the transistors to facilitate forming transistor halo, LDD and transistor S/D regions. It is understood that not all transistors include LDD and/or halo regions.
After forming the cell selector unit 1140 and other transistors, back-end-of-line (BEOL) processing is performed. The BEOL process includes forming interconnects in interlevel dielectric (ILD) layers 1190. The interconnects connect the various components of the integrated circuit (IC) to perform the desired functions. An ILD layer includes a metal level 1194 and a contact level 1192. Generally, the metal level 1194 includes conductors or metal lines 1195 while the contact level 1192 includes contacts 1193. The conductors and contacts may be formed of a metal, such as copper, copper alloy, aluminum, tungsten or a combination thereof. Other suitable types of metal, alloys or conductive materials may also be useful. In some cases, the conductors and contacts may be formed of the same material. For example, in upper metal levels, the conductors and contacts may be formed by dual damascene processes. This results in the conductors and contacts having the same material. In some cases, the conductors and contacts may have different materials. For example, in the case where the contacts and conductors are formed by single damascene processes, the materials of the conductors and contacts may be different. Other techniques, such as reactive ion etch (RIE) may also be employed to form metal lines.
A device may include a plurality of ILD layers or levels. For example, x number of ILD levels may be provided. As illustrated, the device includes 5 ILD levels (x=5). Other numbers of ILD levels may also be useful. The numbers of ILD levels may depend on, for example, design requirements or the logic process involved. A metal level of an ILD level may be referred to as Mi, where i is from 1 to x and is the ith ILD level of x ILD levels. A contact level of an ILD level may be referred to as Vi-1, where i is the ith ILD level of x ILD levels.
The BEOL process, for example, commences by forming a dielectric layer over the transistors and other components are formed in the FEOL process. The dielectric layer may be silicon oxide. For example, the dielectric layer may be silicon oxide formed by chemical vapor deposition (CVD). The dielectric layer serves as a pre-metal dielectric layer or first contact layer of the BEOL process. The dielectric layer may be referred to as CA level of the BEOL process. Contacts are formed in the CA level dielectric layer. The contacts may be formed by single damascene processes. Via openings are formed in the dielectric layer using mask and etch techniques. For example, a patterned resist mask with openings corresponding to the vias is formed over the dielectric layer. An anisotropic etch, such as RIE, is performed to form the vias, exposing contact regions below, such as S/D regions and gates. A conductive layer, such as tungsten is deposited on the substrate, filling the openings. The conductive layer may be formed by sputtering. Other techniques may also be useful. A planarization process, such as CMP, is performed to remove excess conductive materials, leaving contact plugs in the CA level.
After forming contacts 1193 in the CA level, the BEOL process continues to form dielectric layer over the substrate 1105, covering the CA level dielectric layer. The dielectric layer, for example, serves as a first metal level M1 of the first ILD layer. The upper dielectric layer, for example, is a silicon oxide layer. Other types of dielectric layers may also be useful. The dielectric layer may be formed by CVD. Other techniques for forming the dielectric layer may also be useful.
Conductive lines are formed in the M1 level dielectric layer. The conductive lines may be formed by a damascene technique. For example, the dielectric layer may be etched to form trenches or openings using, for example, mask and etch techniques. A conductive layer is formed on the substrate, filling the openings. For example, a copper or copper alloy layer may be formed to fill the openings. The conductive material may be formed by, for example, plating, such as electro or electroless plating. Other types of conductive layers or forming techniques may also be useful. Excess conductive materials are removed by, for example, CMP, leaving planar surface with M1 dielectric. The first metal level M1 and CA may be referred as a lower ILD level.
The process continues to form additional ILD layers (not shown). For example, the process continues to form upper ILD layers or levels. The upper ILD levels may include ILD level 2 to ILD level x. For example, in the case where x=5 (5 levels), the upper levels include ILD levels from 2 to 5, which include via levels V1 to V4 and metal levels M2 to M5. The number of ILD layers may depend on, for example, design requirements or the logic process involved. The upper ILD layers may be formed of silicon oxide. Other types of dielectric materials, such as low k, high k or a combination of dielectric materials may also be useful. The ILD layers may be formed by, for example, CVD. Other techniques for forming the ILD layers may also be useful.
The conductors and contacts of the upper ILD layers may be formed by dual damascene techniques. For example, vias and trenches are formed, creating dual damascene structures. The dual damascene structure may be formed by, for example, via first or via last dual damascene techniques. Mask and etch techniques may be employed to form the dual damascene structures. The dual damascene structures are filled with a conductive layer, such as copper or copper alloy. The conductive layer may be formed by, for example, plating techniques. Excess conductive materials are removed by, for example, CMP, forming conductors and contacts in an upper ILD layer.
A dielectric liner (not shown) may be disposed between ILD levels and on the substrate 1105. The dielectric liner, for example, serves as an etch stop layer. The dielectric liner may be formed of a low k dielectric material. For example, the dielectric liner may be nBLOK. Other types of dielectric materials for the dielectric liner may also be useful.
The uppermost ILD level (e.g., M5) may have different design rules, such as critical dimension (CD), than the lower ILD levels. For example, Mx may have a larger CD than metal levels M1 to Mx−1 below. For example, the uppermost metal level may have a CD which is 2× or 6× the CD of the metal levels below. Other configurations of the ILD levels may also be useful.
As shown, S/D contacts 1193 are disposed in the CA level. The S/D contacts are coupled to the first and second S/D regions of the select transistor. Other S/D contacts coupled to other S/D regions of transistors may also be provided. The CA level may include a gate contact (not shown) coupled to the gate of the select transistor. The gate contact may be disposed in another cross-section of the device. The contacts may be tungsten contacts while contact pads may be copper pads. Other types of contacts and contact pads may also be useful. Other S/D and gate contacts for other transistors may also be provided.
As described, metal lines are provided in M1. The metal lines are coupled to the S/D contacts 1193. In one embodiment, a SL is coupled to the second S/D region 1146 of the select transistor. As for the first S/D contact 1145, it may be coupled to contact pads or island in M1. The contact pads provide connections to upper ILD levels. The metal lines or pads may be formed of copper or copper alloy. Other types of conductive materials may also be useful.
As for the upper ILD, for example, from 2 to 5, they include contacts in the via level and contact pads/metal lines in the metal level. The contacts and contact pads provide connections from M5 to the first S/D region 1145 of the select transistor.
A pad level (not shown) is disposed over the uppermost ILD level. For example, a pad dielectric level is disposed over Mx. In the case where the device includes 5 metal levels, the pad level is disposed over M5. The pad dielectric layer, for example, may be silicon oxide. Other types of dielectric materials may also be useful. The pad dielectric layer includes pads, such as bond pads or pad interconnects for providing external interconnections to the components. Bond pads may be used for wire bonding while pad interconnects may be provided for contact bumps. The external interconnections may be input/output (I/O), power and ground connections to the device. The pads, for example, may be aluminum pads. Other types of conductive pads may also be useful. A passivation layer, such as silicon oxide, silicon nitride or a combination thereof, may be provided over the pad level. The passivation layer includes openings to expose the pads.
A dielectric liner may be disposed between the uppermost metal level and pad level. The dielectric liner, for example, serves as an etch stop layer during via etch process and it may also serve as a diffusion barrier layer for, for example, copper (Cu) layer. The dielectric liner may be a low k dielectric liner. For example, the dielectric liner may be nBLOK. Other suitable types of dielectric materials for the dielectric liner may also be useful.
The storage unit 1110 of the memory cell is disposed in a storage dielectric layer 1150. The storage dielectric layer 1150 may be a via level of an ILD level. As shown, the storage dielectric layer 1150 is V1. Providing the storage dielectric layer at other via levels may also be useful. In other embodiments, the storage dielectric layer 1150 may be a dedicated storage dielectric layer and is not part of an interconnect level. Other configurations of storage dielectric layer may also be useful. The storage unit 1110 includes a storage element disposed between bottom and top electrodes, forming a pMTJ element. The storage element, in one embodiment, is a bottom pinned pMTJ storage element, such as that described in
In one embodiment, the bottom electrode of the storage unit is coupled to a drain of the select transistor. For example, the bottom electrode is coupled to a contact pad in the M1 level and a via contact in the CA level. Other configurations of coupling the bottom electrode may also be useful. The top electrode is coupled to a BL. For example, the top electrode is coupled to the BL disposed in M2. The BL is along a bitline direction. As for the source of the select transistor, it is coupled to a SL. For example, a via contact in CA is provided to couple the source region of the select transistor to SL in M1. Providing SL in other levels may also be useful.
As for the gate of cell selector, it is coupled to a WL. The WL, for example, is along a wordline direction. The bitline and wordline directions are perpendicular to each other. As shown, the WL is disposed in M3. The WL may be coupled to the gate by contact pads in M2 and M1 and via contacts in V2 and V1 (not shown). Other configurations of coupling the WL to the gate may also be useful. For example, the WL may be disposed in other metal levels.
Although as described, the various lines and storage element are disposed in specified dielectric levels of the backend dielectric levels, other configurations may also be useful. For example, they may be disposed in other or additional metal levels. For example, the storage element may be provided in an upper via level, such as between M5 and M6 (not shown). Furthermore, the device may include other device regions and components.
The simplified cross-sectional views illustrate an upper ILD level 1290. For example, a substrate (not shown) has been processed with FEOL and BEOL processing, as already described, to include the upper ILD level. FEOL processing, for example, forms transistors, including a select transistor of the memory cell. Other types of devices may also be formed on the same substrate. BEOL processing forms interconnects in ILD levels. The upper ILD level includes a via level 1292 and a metal level 1294. For example, the upper ILD level includes V4 and M5. The via level, as shown, includes via contacts 1293 while the metal level includes interconnects. For example, interconnect 1295b is a cell contact pad for coupling to a storage unit and interconnect 1295a is coupled to a pad interconnect. The interconnects, for example, are copper interconnects. Other suitable types of interconnects may also be useful.
Referring to
The process continues to form a dielectric layer. As shown in
In
Referring to
The MTJ stack, for example, includes a storage stack disposed between top and bottom electrodes. The bottom electrode is coupled to a contact pad in the metal level below. For example, the bottom electrode is coupled to a contact pad 1295b in M5. This provides connections of the MTJ stack to the first S/D region 1145 of the cell select transistor as described in
The various layers of the MTJ stack are formed on the substrate. For example, the various layers of the MTJ stack are sequentially formed over the lower passivation layer and fill the opening. After the opening 1264 is formed, a bottom electrode layer 1231, such as Ta or TaN is deposited over the lower passivation layer and fills the opening as shown in
Referring to
In one embodiment, the substrate is subjected to an alloying process. The alloying process includes annealing the substrate to around 400° C. with duration of about 1-2 hours and with hydrogen ambient. Other annealing parameters may also be useful.
An intermediate dielectric layer 1270 which serves as a storage dielectric layer is formed on the substrate, as shown in
A planarizing process is performed on the substrate, planarizing the intermediate dielectric layer. The planarizing process, for example, is a CMP process. The CMP process produces a planar top surface between the top of the MTJ stack and the intermediate dielectric layer. The intermediate dielectric layer is patterned to form a via opening 1276. The via opening is patterned by mask and etch techniques. The via opening penetrates through the various dielectric layers and the dielectric liner. This exposes the interconnect 1295a in the lower metal level. After forming the via opening, the mask layer is removed. For example, the mask and ARC layers are removed.
Referring to
The conductive layer is patterned to form a metal line 1269 and an interconnect 1266. Patterning the conductive layer to form the metal line and interconnect may be achieved by mask and etch techniques. For example, a patterned photoresist mask (not shown) may be formed over the conductive layer. An etch, such as RIE, may be used to pattern the conductive layer with a patterned resist mask. In one embodiment, the interconnect 1266 includes a via contact 1264 in the via opening and a contact 1262 over the intermediate dielectric layer 1270. The metal line 1269, for example, may serve as the BL. After patterning the conductive layer, the mask layer is removed. For example, the mask and ARC layers are removed.
Additional processes may be performed to complete the formation of the device. For example, the processes may include forming additional ILD levels, pad level, passivation level, pad opening, dicing, assembly and testing. Other types of processes may also be performed.
Although the storage stack of the memory cell as described above includes a MTJ stack such as that shown in
The embodiments as described result in various advantages. For example, the alloying process performed at high temperature, such as 400° C. is important to maintain the performance and reliability of devices other than the MTJ stack. In the embodiments as described, the provision of the texture breaking layer having the composite spacer layer improves the thermal budget and is compatible with the alloying process. For example, the composite layer includes a diffusion barrier layer (Magnesium spacer layer) which blocks the diffusion of tantalum metal into the polarizer and tunnel barrier layers, thereby enhances the TMR of the MTJ element at high anneal temperature (e.g., 400° C.). Furthermore, the composite spacer layer may reduce the total magnetic moment in the second magnetic layer of the SAF layer, minimizing stray field which results in reduced offset field of the free layer. In some of the embodiments, the composite spacer layer which includes Ru spacer layer improves the PMA of the second magnetic layer of the SAF layer adjacent thereto and further reduces the overall thickness of the second magnetic layer of the SAF layer. This could lead to minimized thickness of a pMTJ stack. Moreover, the process as described is highly compatible with logic processing or technology.
The present disclosure may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments, therefore, are to be considered in all respects illustrative rather than limiting the invention described herein. Scope of the invention is thus indicated by the appended claims, rather than by the foregoing description, and all changes that come within the meaning and range of equivalency of the claims are intended to be embraced therein.
This application claims the priority of U.S. Provisional Application No. 62/249,378, entitled “Magnetic Tunnel Junction with High Thermal Budget” filed on Nov. 2, 2015, and U.S. Provisional Application No. 62/325,986, entitled “Perpendicular MTJ Stack with High TMR and High Thermal Endurance and Method for Forming Thereof” filed on Apr. 21, 2016, which are herein incorporated by reference in its entirety. This application also cross-references U.S. patent application Ser. No. 15/057,109, entitled “Magnetic Memory with High Thermal Budget” filed on Feb. 29, 2016; U.S. patent application Ser. No. 15/060,634, entitled “Magnetic Memory with Tunneling Magnetoresistance Enhanced Spacer Layer” filed on Mar. 4, 2016; patent application Ser. No. 15/071,180, entitled “High Thermal Budget Magnetic Memory” filed on Mar. 15, 2016; U.S. patent application Ser. No. 15/075,222, entitled “Bottom Electrode for Magnetic Memory to Increase TMR and Thermal Budget” filed on Mar. 21, 2016; U.S. patent application Ser. No. 15/081,971, entitled “Storage Layer for Magnetic Memory with High Thermal Stability” filed on Mar. 28, 2016; U.S. patent application Ser. No. 15/060,647, entitled “Magnetic Memory with Tunneling Magnetoresistance Enhanced Spacer Layer” filed on Mar. 4, 2016; and U.S. patent application Ser. No. 15/057,107, entitled “Magnetic Memory with High Thermal Budget” filed on Feb. 29, 2016; which are herein incorporated by references for all purposes.
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