Patent Application
20130115779
The present invention relates generally to combinatorial methods for device process development.
The manufacture of integrated circuits and other substrate-based components entails the integration and sequencing of many unit processing steps. As an example, IC manufacturing typically includes a series of processing steps such as cleaning, surface preparation, deposition, patterning, etching, thermal annealing, and other related unit processing steps. The precise sequencing and integration of the unit processing steps enables the formation of functional devices meeting desired performance metrics such as efficiency, power production, and reliability.
As part of the discovery, optimization and qualification of each unit process, it is desirable to be able to i) test different materials, ii) test different processing conditions within each unit process module, iii) test different sequencing and integration of processing modules within an integrated processing tool, iv) test different sequencing of processing tools in executing different process sequence integration flows, and combinations thereof in the manufacture of devices such as integrated circuits. In particular, there is a need to be able to test i) more than one material, ii) more than one processing condition, iii) more than one sequence of processing conditions, iv) more than one process sequence integration flow, and combinations thereof, collectively known as “combinatorial process sequence integration”, on a single monolithic substrate without the need of consuming the equivalent number of monolithic substrates per material(s), processing condition(s), sequence(s) of processing conditions, sequence(s) of processes, and combinations thereof. This can greatly improve both the speed and reduce the costs associated with the discovery, implementation, optimization, and qualification of material(s), process(es), and process integration sequence(s) required for manufacturing.
Systems and methods for High Productivity Combinatorial (HPC) processing are described in U.S. Pat. No. 7,544,574 filed on Feb. 10, 2006, U.S. Pat. No. 7,824,935 filed on Jul. 2, 2008, U.S. Pat. No. 7,871,928 filed on May 4, 2009, U.S. Pat. No. 7,902,063 filed on Feb. 10, 2006, and U.S. Pat. No. 7,947,531 filed on Aug. 28, 2009 which are all herein incorporated by reference. Systems and methods for HPC processing are further described in U.S. patent application Ser. No. 11/352,077 filed on Feb. 10, 2006, claiming priority from Oct. 15, 2005, U.S. patent application Ser. No. 11/419,174 filed on May 18, 2006, claiming priority from Oct. 15, 2005, U.S. patent application Ser. No. 11/674,132 filed on Feb. 12, 2007, claiming priority from Oct. 15, 2005, and U.S. patent application Ser. No. 11/674,137 filed on Feb. 12, 2007, claiming priority from Oct. 15, 2005 which are all herein incorporated by reference.
HPC processing techniques have been successfully adapted to wet chemical processing such as etching and cleaning. HPC processing techniques have also been successfully adapted to deposition processes such as physical vapor deposition (PVD), atomic layer deposition (ALD), and chemical vapor deposition (CVD).
Currently, good sealing on a surface coated with soft, deformable or sticky materials, such as a photoresist, can be difficult, for example, due to the tendency of the wet chemistry being tested to wick under the sealing surface through capillary action. In addition, the wicking action can generate partial reaction areas in the vicinity of the sealing surface. Thus there is a need for improve sealing in site isolated regions in HPC systems.
In some embodiments, the present invention discloses systems and methods for generating site isolated regions on a substrate, allowing combinatorial processing without cross contamination between regions. The site isolated regions are sealed against each other through a sealing mechanism that can be effective for different substrate surface conditions, including surface layer removal at the sealing interface.
In some embodiments, the sealing mechanism includes a thin sharp edge ring for pressing on the substrate surface with small contact area. For example, the sealing mechanism can include a conical seal having taper edges toward the substrate surface. The small sealing area can concentrate the sealing force, generating higher contact pressure to guard against fluid leakage across the sealing surface, for example, eliminating fluid wicking at the seal interface through capillary action.
In some embodiments, the conical seal can form a better seal with a deformable substrate layer, such as a photoresist layer, by heating the deformable layer before forming the seal contact. When cooling, the conical seal can be partially embedded in the deformable layer, improving the sealing characteristics (apply as a separate patent?).
In some embodiments, the sealing mechanism includes multiple protrusions, which contact the substrate leaving a small gap at the remaining portion of the sealing mechanism. The sealing mechanism can include minimal contact points with the substrate, which can significantly reduce the particle generation during processing. A pressure differential can be established across the sealing surface to prevent fluid leakage.
In some embodiments, the present conical seal can be used in a high productivity combinatorial (HPC) system. During normal operation of an HPC system, a reactor module comprising a plurality of reactors can create a plurality of isolated regions on a substrate surface. The isolated regions are processed with process conditions, device structure or materials varying in a combinatorial manner. In an exemplary configuration, a reactor comprises a conical seal, pressing on a region of the substrate surface to create an isolated processing region. The conical seal can improve the pressing contact characteristics, forming better seal due to the conical sharp edges, reducing fluid leakage due to higher contact pressure and reducing particles due to smaller contact area.
In some embodiments, the present invention discloses methods to operate an HPC system comprising reactors having conical seal. Photoresist stripping, layer etching, and depositing can be effectively confined to the site isolated regions with the conical seal.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. The drawings are not to scale and the relative dimensions of various elements in the drawings are depicted schematically and not necessarily to scale.
The techniques of the present invention can readily be understood by considering the following detailed description in conjunction with the accompanying drawings, in which:
A detailed description of one or more embodiments is provided below along with accompanying figures. The detailed description is provided in connection with such embodiments, but is not limited to any particular example. The scope is limited only by the claims and numerous alternatives, modifications, and equivalents are encompassed. Numerous specific details are set forth in the following description in order to provide a thorough understanding. These details are provided for the purpose of example and the described techniques may be practiced according to the claims without some or all of these specific details. For the purpose of clarity, technical material that is known in the technical fields related to the embodiments has not been described in detail to avoid unnecessarily obscuring the description.
In some embodiments, the current invention relates to systems and methods for sealing site-isolated for use in the development of processes for the manufacture of integrated circuits (IC). The systems and methods described below can provide sealing systems for use in isolating reactions in reactors that are in close proximity to other reactors. The reactors isolated according to the sealing systems and methods described herein include single reactors as well as one or more sets or groups of reactors used in one or more of serial, parallel, and/or serial parallel modes.
In some embodiments, the current invention discloses sealing the reactors with improved particle performance and fluid isolation. The seal can include a sharp edged sleeve, for example, a sleeve having conical edges for contacting the substrate to form site isolated regions. The conical sleeve can have a small contact area with a substrate, thus the applied force can be concentrated on a smaller area, e.g., at the tips of the conical edges, to provide greater contact pressure at the sealing interface. Further, the small contact area can reduce the number of generated particles. In addition, when the conical sleeve contacts deformable material, such as a resist layer, a good seal can be obtained by heating the sample before applying the conical sleeve.
In some embodiments, the seal can include a minimal contact sealing surface, such as a majority of the seal can form a small gap with the substrate. The seal can include three or more protrusions (or bumps) pressing on the substrate, leaving a small and consistent gap surrounding the sleeve. A pressure differential can be provided prevent leakage of fluid across the sleeve seal. For example, since there is no continuous wall to exclude chemicals from entering across the sleeve seal, the internal volume of the sleeve can be pressurized by an inert gas. The pressure/flow of the gas can be controlled so that it balances the pressure of the chemistry surrounding the sleeve. Alternatively, the outside ambient can be pressurized to prevent leakage of fluid from the sleeve interior.
“Combinatorial Processing” generally refers to techniques of differentially processing multiple regions of one or more substrates. Combinatorial processing generally varies materials, unit processes or process sequences across multiple regions on a substrate. The varied materials, unit processes, or process sequences can be evaluated (e.g., characterized) to determine whether further evaluation of certain process sequences is warranted or whether a particular solution is suitable for production or high volume manufacturing.
For example, thousands of materials are evaluated during a materials discovery stage, 102. Materials discovery stage, 102, is also known as a primary screening stage performed using primary screening techniques. Primary screening techniques may include dividing substrates into coupons and depositing materials using varied processes. The materials are then evaluated, and promising candidates are advanced to the secondary screen, or materials and process development stage, 104. Evaluation of the materials is performed using metrology tools such as electronic testers and imaging tools (i.e., microscopes).
The materials and process development stage, 104, may evaluate hundreds of materials (i.e., a magnitude smaller than the primary stage) and may focus on the processes used to deposit or develop those materials. Promising materials and processes are again selected, and advanced to the tertiary screen or process integration stage, 106, where tens of materials and/or processes and combinations are evaluated. The tertiary screen or process integration stage, 106, may focus on integrating the selected processes and materials with other processes and materials.
The most promising materials and processes from the tertiary screen are advanced to device qualification, 108. In device qualification, the materials and processes selected are evaluated for high volume manufacturing, which normally is conducted on full substrates within production tools, but need not be conducted in such a manner. The results are evaluated to determine the efficacy of the selected materials and processes. If successful, the use of the screened materials and processes can proceed to pilot manufacturing, 110.
The schematic diagram, 100, is an example of various techniques that may be used to evaluate and select materials and processes for the development of new materials and processes. The descriptions of primary, secondary, etc. screening and the various stages, 102-110, are arbitrary and the stages may overlap, occur out of sequence, be described and be performed in many other ways.
This application benefits from High Productivity Combinatorial (HPC) techniques described in U.S. patent application Ser. No. 11/674,137 filed on Feb. 12, 2007 which is hereby incorporated for reference in its entirety. Portions of the '137 application have been reproduced below to enhance the understanding of the present invention. The embodiments described herein enable the application of combinatorial techniques to process sequence integration in order to arrive at a globally optimal sequence of IC manufacturing operations by considering interaction effects between the unit manufacturing operations, the process conditions used to effect such unit manufacturing operations, hardware details used during the processing, as well as materials characteristics of components utilized within the unit manufacturing operations. Rather than only considering a series of local optimums, i.e., where the best conditions and materials for each manufacturing unit operation is considered in isolation, the embodiments described below consider interactions effects introduced due to the multitude of processing operations that are performed and the order in which such multitude of processing operations are performed when fabricating an IC device. A global optimum sequence order is therefore derived and as part of this derivation, the unit processes, unit process parameters and materials used in the unit process operations of the optimum sequence order are also considered.
The embodiments described further analyze a portion or sub-set of the overall process sequence used to manufacture an IC device. Once the subset of the process sequence is identified for analysis, combinatorial process sequence integration testing is performed to optimize the materials, unit processes, hardware details, and process sequence used to build that portion of the device or structure. During the processing of some embodiments described herein, structures are formed on the processed substrate that are equivalent to the structures formed during actual production of the IC device. For example, such structures may include, but would not be limited to, contact layers, buffer layers, absorber layers, or any other series of layers or unit processes that create an intermediate structure found on IC devices. While the combinatorial processing varies certain materials, unit processes, hardware details, or process sequences, the composition or thickness of the layers or structures or the action of the unit process, such as cleaning, surface preparation, deposition, surface treatment, etc. is substantially uniform through each discrete region. Furthermore, while different materials or unit processes may be used for corresponding layers or steps in the formation of a structure in different regions of the substrate during the combinatorial processing, the application of each layer or use of a given unit process is substantially consistent or uniform throughout the different regions in which it is intentionally applied. Thus, the processing is uniform within a region (inter-region uniformity) and between regions (intra-region uniformity), as desired. It should be noted that the process can be varied between regions, for example, where a thickness of a layer is varied or a material may be varied between the regions, etc., as desired by the design of the experiment.
The result is a series of regions on the substrate that contain structures or unit process sequences that have been uniformly applied within that region and, as applicable, across different regions. This process uniformity allows comparison of the properties within and across the different regions such that the variations in test results are due to the varied parameter (e.g., materials, unit processes, unit process parameters, hardware details, or process sequences) and not the lack of process uniformity. In the embodiments described herein, the positions of the discrete regions on the substrate can be defined as needed, but are preferably systematized for ease of tooling and design of experimentation. In addition, the number, variants and location of structures within each region are designed to enable valid statistical analysis of the test results within each region and across regions to be performed.
It should be appreciated that various other combinations of conventional and combinatorial processes can be included in the processing sequence with regard to
Under combinatorial processing operations the processing conditions at different regions can be controlled independently. Consequently, process material amounts, reactant species, processing temperatures, processing times, processing pressures, processing flow rates, processing powers, processing reagent compositions, the rates at which the reactions are quenched, deposition order of process materials, process sequence steps, hardware details, etc., can be varied from region to region on the substrate. Thus, for example, when exploring materials, a processing material delivered to a first and second region can be the same or different. If the processing material delivered to the first region is the same as the processing material delivered to the second region, this processing material can be offered to the first and second regions on the substrate at different concentrations. In addition, the material can be deposited under different processing parameters. Parameters which can be varied include, but are not limited to, process material amounts, reactant species, processing temperatures, processing times, processing pressures, processing flow rates, processing powers, processing reagent compositions, the rates at which the reactions are quenched, atmospheres in which the processes are conducted, an order in which materials are deposited, hardware details of the gas distribution assembly, etc. It should be appreciated that these process parameters are exemplary and not meant to be an exhaustive list as other process parameters commonly used in IC manufacturing may be varied.
As mentioned above, within a region, the process conditions are substantially uniform, in contrast to gradient processing techniques which rely on the inherent non-uniformity of the material deposition. That is, the embodiments, described herein locally perform the processing in a conventional manner, e.g., substantially consistent and substantially uniform, while globally over the substrate, the materials, processes, and process sequences may vary. Thus, the testing will find optimums without interference from process variation differences between processes that are meant to be the same. It should be appreciated that a region may be adjacent to another region in one embodiment or the regions may be isolated and, therefore, non-overlapping. When the regions are adjacent, there may be a slight overlap wherein the materials or precise process interactions are not known, however, a portion of the regions, normally at least 50% or more of the area, is uniform and all testing occurs within that region. Further, the potential overlap is only allowed with material of processes that will not adversely affect the result of the tests. Both types of regions are referred to herein as regions or discrete regions.
Combinatorial processing can be used to produce and evaluate different materials, chemicals, processes, process and integration sequences, and techniques related to semiconductor fabrication. For example, combinatorial processing can be used to determine optimal processing parameters (e.g., power, time, reactant flow rates, temperature, etc.) of dry processing techniques such as dry etching (e.g., plasma etching, flux-based etching, reactive ion etching (RIE)) and dry deposition techniques (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.). Combinatorial processing can be used to determine optimal processing parameters (e.g., time, concentration, temperature, stirring rate, etc.) of wet processing techniques such as wet etching, wet cleaning, rinsing, and wet deposition techniques (e.g., electroplating, electroless deposition, chemical bath deposition, etc.).
In some embodiments, the present invention discloses systems and methods for generating site isolated regions on a substrate, allowing combinatorial processing without cross contamination between regions. The site isolated regions are sealed against the substrate through a sealing mechanism that can be effective for different substrate surface conditions, including surface layer removal at the sealing interface.
Processing fluid 560, such as a processing solution or rinsing water, can be introduced to the reactors for processing the substrate regions isolated by the sealing areas. The fluid is bounded by a seal element, such as a conical seal 545 having sharp edges, to contain the fluid within the reactor volume. The processing of the fluid is then restricted to the isolated regions on the substrate surface inside the reactor areas, with the seal element 545 preventing liquid leakage from under the reactors.
An example of a structure for use in site-isolated processing of unique regions on a substrate includes the use of seals between reactors of the array and one or more regions of a target substrate. In some embodiments, the sealing systems and methods of sealing comprise one or more contact seals, using seals at the interface of the reactors and the substrate surface to enable effective containment of isolated reactions of reactors of an array. The reactors isolated according to the sealing systems and methods described herein include single reactors as well as one or more sets or groups of reactors used in one or more of serial, parallel, and/or serial parallel modes.
In some embodiments, the sealing mechanism comprises a thin sharp edge ring for pressing on the substrate surface with small contact area. For example, the sealing mechanism can comprise a conical seal having taper edges toward the substrate surface. The small sealing area can concentrate the sealing force, generating higher contact pressure to guard against fluid leakage across the sealing surface, for example, eliminating fluid wicking at the seal interface through capillary action. The conical seal 645 thus provides site-isolated reactors with small contact area, enabling higher contact pressure and lower particle contamination. Effective seals can therefore be achieved on the target substrate because the conical seal can ensure that no leakage of reactants takes place from the reactors.
In some embodiments, the reactor head 730 can comprise a reactor sleeve 745, defining a reactor reaction region 710 within the sleeve 745. In some embodiments, the sleeve 745 is coupled to an upper portion of the reactor head through an o-ring 720, controlling a floating of the sleeve 745 in the reactor 700 over a pre-specified range of motion. The range of motion of an embodiment is therefore determined by dimensions and/or properties of material of the compliance o-ring 720. The floating sleeve 745 and consequently the reactor 700 are shown to be circular but may take on a number of different shapes in other embodiments as appropriate to a processing system.
Therefore, the floating sleeve 745 can float within the reactor 700 so that the seal portion 770 of the sleeve contacts a surface of the substrate. Once the floating sleeve 745 is positioned relative to the substrate surface, the floating sleeve will flex so that an upper portion of the floating sleeve comes into firm contact with a portion of the reactor block so as to maintain the position of the floating sleeve in the reactor block during such time as a reaction is taking place in the reactor.
In some embodiments, the sleeve 745 comprises a seal portion having a conical shape 770 at the sealing surface 780, which presents a sharp edge contact to the substrate. The angle 785 of the sharp edge is less than 90 degrees, and preferably less than about 70 degrees. For stability purposes, the angle of the sharp edge can be greater than about 20 degrees, and preferably greater than about 30 degrees. In some embodiments, the sharp edge can be rounded, for example, to prevent flexing of the sharp tip which can generate particles.
In some embodiments, the sleeve 745 comprises an inert semi-compliant material such as fluoropolymer, which is a fluorocarbon based polymer with multiple strong carbon-fluorine bonds, characterized by a high resistance to solvents, acids, and bases. Examples of fluoropolymers include polychlorotrifluoroethylene (PCTFE), polyethylenechlorotrifluoroethylene (ECTFE), polytetrafluoroethylene (PTFE), perfluoroalkoxy polymer (PFA), polyethylenetetrafluoroethylene (ETFE), and fluorinated ethylene-propylene (FEP).
The contact sealing systems described above are provided as examples of integration into a site-isolated reactor of one or more of the floating sleeve, conical shape having sharp edges of the sealing surface, inert semi-compliant material of the floating sleeve configured to provide a seal of the reactor. Reactors of various alternative embodiments can include configuration variations, such as spring loaded sleeve instead of o-ring, solid construction of reactor head instead of the modular configuration of facility portion and reactor head portion. In addition, the drawings illustrate a conical sleeve with the sharp edges pointing inward, but the invention is not so limited, and any sleeve having sharp edges are within the scope of the present invention, for example, conical sleeve with sharp edge pointing outside, or sleeve with sharp edges in the middle of the sleeve wall.
In some embodiments, the present conical seal can be used in a high productivity combinatorial (HPC) system. During normal operation of an HPC system, a reactor module comprising a plurality of reactors can create a plurality of isolated regions on a substrate surface. The isolated regions are processed with process conditions, device structure or materials varying in a combinatorial manner. In an exemplary configuration, a reactor comprises a conical seal, pressing on a region of the substrate surface to create an isolated processing region. The conical seal can improve the pressing contact characteristics, forming better seal due to the conical sharp edges, reducing fluid leakage due to higher contact pressure and reducing particles due to smaller contact area.
In some embodiments, the present invention discloses methods to operate an HPC system comprising reactors having conical seal. Photoresist stripping, layer etching, and depositing can be effectively confined to the site isolated regions with the conical seal.
In some embodiments, the conical seal can form a good seal with a deformable substrate layer, such as a photoresist layer, by heating the deformable layer before forming the seal contact. When cooling, the conical seal can be partially embedded in the deformable layer, improving the sealing characteristics.
With the heating action to soften the photoresist layer, the conical sleeve can penetrate the photoresist layer, stopping on the substrate surface. The contact of the sleeve with the substrate surface can form a good seal for the isolated region, even in the event that the photoresist is removed during the subsequent process. In addition, the conical sleeve can form good seal on the photoresist layer, preventing potential wicking of liquid to the outside region by capillary action.
The above description describes an exemplary embodiment for processing photoresist layer, but the present invention is not so limited, and can be applied to any deformable layer or soft layer, such as organic layers, polymer layers or low-k layers. In some embodiments, the layer heating comprises a temperature to soften the layer, for example, to about two third of the melting point, or to about the glass transition temperature. In some embodiments, the heating temperature is less than about 200° C., and preferably less than about 100° C.
In some embodiments, the conical seal can form a good seal with a substrate layer during the removal of the layer within the reaction region.
In some embodiments, the current invention discloses a reactor for sealing with a substrate with minimal contacts. The small contact surface of the seal can reduce the amount of particles that are left on a substrate after performing a processing using site isolated regions.
In some embodiments, the seal forms a gap with the substrate, with three or more contacting points. A pressure differential can be applied to prevent fluid leakage across the seal. For example, the internal volume of the reactor can be pressurized by an inert gas, which can balance the pressure of the chemistry surrounding the cup. Alternatively, the internal volume can have a greater pressure than the surrounding ambient to induce a small amount of flow (e.g., bubbles).
In some embodiments, the site isolated regions are the areas of interest in a combinatorial process, since they provide the variations of process and material parameters, which can be evaluated to obtain the optimum device structures and fabrication processes. In some embodiments, the surface areas outside the isolated regions are also processed, such as, to clean or etch the outside surface area. For example, to clean the outside surface areas with a wet cleaning fluid, the isolated regions are protected and cleaning chemical is introduced to the substrate surface.
Although the foregoing examples have been described in some detail for purposes of clarity of understanding, the invention is not limited to the details provided. There are many alternative ways of implementing the invention. The disclosed examples are illustrative and not restrictive.
The present invention claims priority to U.S. provisional patent application Ser. No. 61/557,546, filed Nov. 9, 2011, entitled “Conical Sleeve for Reactors”, hereby incorporated by reference for all purposes.
| Number | Date | Country | |
|---|---|---|---|
| 61557546 | Nov 2011 | US |
