Claims
- 1. An improvement in a process for reducing re-entrant undercutting of aluminum on titanium interconnect conducting lines formed over a semiconductor substrate, said process comprising:
- forming an inter-metal layer dielectric consisting essentially of an oxide; and
- forming a patterned multi-layer structure on said inter-metal layer dielectric, said patterned multi-layer structure comprising a titanium nitride anti-reflection layer formed on an aluminum layer formed on a titanium layer formed on said oxide layer, the improvement consisting essentially of:
- (a) depositing in either order on said oxide to form said inter-metal layer dielectric (1) a layer consisting essentially of nitrogen and titanium and (2) said titanium layer, thereby forming a titanium-containing layer;
- (b) depositing said aluminum layer on said titanium-containing layer;
- (c) depositing said titanium nitride anti-reflection layer on said aluminum layer; and
- (d) patterning and etching all metal-containing layers to form said interconnect conducting lines.
- 2. The process of claim 1 wherein said nitrogen-containing titanium layer is deposited on said oxide layer first, followed by forming said titanium layer thereon.
- 3. The process of claim 2 wherein said nitrogen-containing titanium layer and said titanium layer are deposited by first supplying a titanium target with both a nitrogen-containing gas and argon gas in a sputtering chamber to form said nitrogen-containing titanium layer and then supplying only argon to form said titanium layer on said nitrogen-containing titanium layer.
- 4. The process of claim 1 wherein said titanium layer is deposited on said oxide layer first, followed by forming said nitrogen-containing titanium layer thereon.
- 5. The process of claim 4 wherein said titanium layer and said nitrogen-containing titanium layer are deposited by first supplying a titanium target with argon gas in a sputtering chamber to form said titanium layer and then supplying both a nitrogen-containing gas and argon gas to form said nitrogen-containing titanium layer on said titanium layer.
- 6. The process of claim 4 wherein said nitrogen-containing titanium layer is formed by first sputtering titanium in argon, then treating in a nitrogen-containing gas at a temperature elevated above room temperature.
- 7. The process of claim 6 wherein said treating is carried out by rapid thermal annealing at a temperature of about 600.degree. to 800.degree. C. in a nitrogen-containing gas selected from the group consisting of nitrogen gas, nitrogen oxide, and ammonia.
- 8. The process of claim 6 wherein said treating is carried out in a furnace at a temperature of about 400.degree. to 450.degree. C. for a period of time of about 30 to 60 minutes in ammonia.
- 9. The process of claim 1 wherein said nitrogen-containing titanium layer is formed by reactive sputtering of titanium in nitrogen gas.
- 10. The process of claim 1 wherein said nitrogen-containing titanium layer is formed by chemical vapor deposition.
- 11. The process of claim 1 wherein said nitrogen-containing titanium layer has a composition given by Ti.sub.x N.sub.y, where 0<x.ltoreq.1 and 0<y.ltoreq.1 and where the amount of nitrogen is at least 10 atomic percent of said composition.
- 12. The process of claim 1 wherein said nitrogen-containing titanium layer is formed to a thickness ranging from about 0.01 to 0.1 .mu.m.
- 13. The process of claim 1 wherein said oxide layer comprises silicon dioxide.
- 14. The process of claim 1 wherein said oxide layer comprises plasma-enhanced oxide.
- 15. The process of claim 11 where x.noteq.y.
Parent Case Info
This a continuation of application Ser. No. 08/250,985 filed May 31, 1994, now abandoned.
US Referenced Citations (10)
Foreign Referenced Citations (3)
Number |
Date |
Country |
0 354 717 |
Feb 1990 |
EPX |
06-104227 |
Apr 1992 |
JPX |
05-152245 |
Jun 1993 |
JPX |
Non-Patent Literature Citations (2)
Entry |
S. Wolf, "Silicon Processing for the VLSI Era, vol. 2", Lattice Press, pp. 194-199, Jun. 1990. |
S. Wolf, "Silicon Processing for the VLSI Euo, vol. I", Lottice Press 1986, p. 407. |
Continuations (1)
|
Number |
Date |
Country |
Parent |
250985 |
May 1994 |
|