1. Field of the Invention This invention relates to a memory, and particularly to a control circuit of SRAM and operating method thereof.
2. Description of the Prior Art
According to the operating type, the conventional memory can be divided into several categories, such as the dynamic random access memory (DRAM) and the static random access memory (SRAM). Wherein, the memory cell of the static random access memory (SRAM) is composed of a plurality of transistors, which has high switching speed and does not need any additional upgrading circuit. The so-called “static state” means when the power is applied to the static random access memory, the stored data can be kept constantly. On the contrary, the data stored in the dynamic random access memory (DRAM) has to be upgraded periodically. However, when the power supply is stopped completely, the data stored in the static random access memory will still be disappeared.
The static random access memory (SRAM) is generally applied to the products, such as the portable electronic device and the System-on-Chip (SOC) etc. At present, the design of common static random access memory (SRAM) comprises various types of structure, such as five-transistor structure, six-transistor structure or eight-transistor structure etc.
However, under the advanced semiconductor process, the write ability of static random access memory is relatively low, it is necessary to use more transistors to complete the memory cells of a bit, so that the unit capacity will be lower, and the power consumption will be higher. Therefore, although the word-line boost circuit is used, but its risk is that the gate oxidization layer will be easy to be penetrated.
Therefore, in order to produce more efficient static random access memory, provide better operating efficiency and lower manufacturing cost, it is necessary to research and develop the new auxiliary circuit of static random access memory.
It is an object of the present invention is to provide a control circuit of SRAM. In an embodiment, the control circuit of SRAM comprises a memory array, a word-line driver, a boost circuit and a voltage level detecting circuit. The memory array comprises a plurality of memory cells. Each memory cell includes a plurality of transistors. The word-line driver is to activate the word-line of the memory array for cell storage data access. The boost circuit is coupled with the word-line driver and the first operating voltage to provide the higher voltage source for the first operating voltage for boosting the first operating voltage to a second operating voltage. The voltage level detecting circuit is coupled with the first operating voltage and the DECT signal commencing to detect to control the operating of the boost circuit based on the detecting-trigger signal, the first operating voltage and a predetermined voltage.
In an embodiment, if the first operating voltage is smaller than the predetermined voltage, the voltage level detecting circuit will activate the boost circuit. If the first operating voltage is greater than the predetermined voltage, the voltage level detecting circuit will control the boost circuit for stopping the boost treatment of the first operating voltage.
In an embodiment, the voltage level detecting circuit also includes a reference unit and a detecting unit. The reference unit has a first node. The detecting unit has a second node. The voltage of the first node equals to the voltage of the second node when detecting.
In an embodiment, the voltage level detecting circuit also includes a reference unit, which is coupled with the first operating voltage and the detecting unit.
In an embodiment, the voltage level detecting circuit also includes a first inverter and a first transistor reference unit. The first inverter is coupled with the DECT signal. The first transistor is coupled with the output terminal, the ground terminal of the first inverter and the detecting unit.
In an embodiment, the detecting unit also includes a second inverter and a third inverter. The detecting unit is coupled with the reference unit, the DECT signal and the fourth inverter.
In an embodiment, the operating method for the control circuit of SRAM includes controlling the operating of the boost circuit based on the DECT signal, the first operating voltage and a predetermined voltage; using the boost circuit to boost the first operating voltage to a second operating voltage; and using the second operating voltage to drive several transistors in the memory array.
In an embodiment, if the first operating voltage is smaller than the predetermined voltage, the boost circuit will be controlled for boosting the first operating voltage to a second operating voltage.
In an embodiment, if the first operating voltage is greater than the predetermined voltage, the boost circuit will be controlled for stopping the boost treatment of the first operating voltage.
In comparison with the prior art, the control circuit and its operating method of the present invention uses the voltage level detecting circuit to detect whether the operating voltage (VDD) is greater than the predetermined voltage. If the operating voltage is greater than the predetermined voltage, the boost circuit will be shut down. If the operating voltage is smaller than the predetermined voltage, the boost circuit will be activated. In this kind of circuit design, the fault tolerance will be higher, and the gate oxidization layer of transistor in the memory cell will not be penetrated due to the boost circuit.
Therefore, the advantage and spirit of the present invention can be understood further by the following detail description of invention and attached Figures.
The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
The voltage level detecting circuit 11 of the present invention shown in
In the embodiment of
In the embodiment of
In the embodiment of
In addition, a second node ST2 is located between the first transistor pair 1123 and the second transistor pair 1124 of the detecting unit 112 shown in
However, in the other embodiment, the voltage level of the first node ST1 and the second node ST2 might be slightly different. In the detecting unit 112 of this embodiment, the input terminal of the third inverter 1121 is coupled with the second node ST2, the input terminal of the fourth inverter 1122 is coupled with the output terminal of the third inverter 1121, and the output terminal of the fourth inverter 1122 is coupled with the second transistor pair 1124. In addition, the input terminal of the second inverter 114 of the voltage level reference circuit 11 is coupled with the output terminal of the third inverter 1121 and the input terminal of the fourth inverter 1122. The output terminal of the second inverter 114 is coupled with the boost circuit 12 to control the operating of the boost circuit 12.
In
In Step S310 of
In Step S315 of
In comparison with the prior art, the embodiment of the present invention uses simple digital circuit to judge whether the operating voltage VDD is greater than a predetermined voltage, in order to determine the operating of the boost circuit. The circuit of the present invention copes with the word-line driver to get higher fault tolerance and can avoid penetrating the gate oxidation layer, in order to raise the operating efficiency of SRAM and reduce the manufacturing cost of SRAM.
It is understood that various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the scope and spirit of this invention. Accordingly, it is not intended that the scope of the claims appended hereto be limited to the description as set forth herein, but rather that the claims be construed as encompassing all the features of patentable novelty that reside in the present invention, including all features that would be treated as equivalents thereof by those skilled in the art to which this invention pertains.
Number | Date | Country | Kind |
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101132567 | Sep 2012 | TW | national |