Patent Application
20170178986
This invention generally relates to stacked, multi-wafer structures, and, in particular, to communication of information to and from such structures and providing power to them.
Huge quantities of data are being generated in the world in unconventional and unstructured formats (texts, video, images, sentiment, etc.). Making useful sense of these data requires new cognitive computing techniques similar to the way the human brain processes information.
These techniques, which require very high memory and communication bandwidths, reach fundamental limitations in a conventional von Neumann architecture, which suffers from a bottleneck between a separated CPU and memory.
Disclosed is a computing device that includes a wafer having multiple layers, the wafer including a top layer and sublayers disposed below it, the sublayers including one or more memory devices. The computing device also includes two or more shaped retainer elements shaped to mate with and at least partially surround at least the top of the wafer and in electrical contact with one or more chips disposed on a top of the top layer and a holding device that mates with the retainer elements to provide power to the retaining elements.
Also disclosed is a computing device that includes a wafer having multiple layers, the wafer including a top layer and sublayers disposed above it, the sublayers including one or more memory devices. The device also includes a holding device that mates with the wafer elements to provide at least power to the retaining elements, the holding device including wire springs that contact either the top layer or a bottom layer of the wafer.
Please include cooling in the summary
Referring to the exemplary drawings wherein like elements are numbered alike in the several Figures:
Embodiments of the invention provide a construct that allows for power/data communication with a cortical system. Additionally the embodiments provide cooling schemes to draw power away from the cortical system.
A cortical system may alleviate the CPU memory bandwidth problem of conventional computer architectures by transferring much of the memory intensive processing to a battalion of Simple Specialized Processors (SSPs) which are embedded in a large sea of computer memory. These SSPs carry out operations on their domains and then transmit very high level results to a number of General Management Processors (GMPs). The burden of the memory and communications bandwidth is therefore transferred largely to the SSPs. Since the SSPs report very high level results to the GMPs, the bandwidth required for the SSP-to-GMP communication is manageable. A more detailed description of how a cortical system may be formed may be found in U.S. patent application Ser. No. 14/713,689, which is incorporated herein by reference.
Each SSP is associated with a memory domain, one of which is shown at 106. The SSPs carry out operations on their domains 106 and then transmit very high level results to a small number of General Management Processors (GMPs). The SSPs may number between approximately 100-1000 per wafer. Each SSP is a specialized simple microprocessor to execute certain memory primitives for memory in its vicinity (domain). The SSPs are referred to as specialized because they are used for a limited number of functions. Any suitable processor may be used in embodiments of the invention as an SSP, and suitable processors are known in the art.
Examples of SSP jobs include: find largest or smallest element in domain; multiply matrix or vector by constant; matrix-matrix, matrix-vector, vector-vector products; fill the domain with random numbers. The SSP also has router/buffer capabilities, discussed below. Each memory domain is a region of neuron/synaptic data which is owned by one SSP—this is the SSP's domain.
Frontside wiring 212 on the final wiring wafer 210 is used, for example, to provide GMP-to-GMP communications. Communications between the GMP chips and the underlying SSPs can be done through a communication channel with only medium bandwidth capabilities such as a layer of micro C4s due to the modest bandwidth requirements, as discussed above. Inter-strata TSVs are used, for instance, for communication from GMP level to SSP level, and for connections to power and ground within the stack.
As illustrated, interlayer connections 214 may be used to allow data to be transferred between SSP wafers and between the SSP wafers and the top wiring wafer 210. Also illustrated is a power bus 216 that provides for the transmission of power to all wafers 204 and 210. The interconnectivity between layers is shown by example only in
In the stack of
The above-described wiring scheme is general, and many other suitable schemes may be used in embodiments of the invention. Also, for instance, in embodiments of the invention, backside wiring is optional, and power/ground can also be distributed on the front. Below, systems and methods for providing power/data from an external location to the wafer stack 202 are discussed.
The stack in
The two part retaining element 301 includes retainer halves 301a and 301b and allows for power to be provided to the wafer 300. It may also allow for data to be transferred to or from the wafer 300.
In this embodiment, the wafer 300 includes 2 GMPS 302. This number is purely by way of example and is in no way limited. The GMPs 302 may be bonded on a wiring wafer 304.
The GMPs 302 may be high performance processors. Any suitable processor may be used as a GMP, and suitable processors are known in the art. The GMPs communicate with external I/O connections 316. The GMP's may also receive power from a power supply 314. The power supplies may also provide power directly to the I/O connections 316 (as illustrated) or such power may be provided through the GMP's 302. One of ordinary skill will realize that any number of additional of GMP's, I/O connections, or any other kind of chip may be provided on the wiring wafer 304.
As illustrated, the two part retaining element 301 includes retainer halves 301a and 301b. These retainer halves may be forced together to contact and surround outer edges of the wafer 300. The outer edges are shown as element 320 in
The retainer halves 301a and 301b are shaped such that when brought together they will contact the outer edges 320 of the wafer stack 300. The retainer halves 301a, 301b include one or more curvilinear connectors 350 shaped to mate with the outer edge 320. As illustrated the retainer halves 301a, 301b include 4 separate connectors 350 labelled as 350a, 350b (contained in retainer half 301b) and 350c, 350d (contained in retainer half 301a) Of course the number of connectors may vary and be only one in one embodiment and can include any other number. The connectors allow power or data to be carried from or to an external location. For example, connectors 350c and 350d may be power connectors that receive power from external power lines 342a and 342b, respectively. The external power lines 342a, 342b may connect to another source of power off of wafer 300.
Similarly, connectors 350a and 350b may be data connectors that provide data to I/O connections 316a and 316b, respectively. The data may be received from or delivered to external data line 340a, 340b so that the wafer can transfer data to other wafers. The power lines and data lines can be on the surface of the wafer or between layers and, as such, are shown in dashed form.
In the above description the connectors 350 where described are part of retainer halves 301a and 301b. It shall be understood that in another embodiment, the connectors 350 could be attached to the wafer 300 first, and then inserted between the retainer halves 301a, 301b. The retainer halves 301a, 301b could then be brought together to contact and hold the assembly including the connectors and the wafer 300. The retainer halves 301 may form a holding device in one embodiment.
The wafer of
As illustrated, the wafer includes connectors 550 coupled to it outer edges. These connectors could be omitted in one embodiment. For example, if omitted, the wafer could be flipped over and placed face down such that the power/data access locations on the upper surface 304 may contact the springs 712. Of course, the power/data access locations could be location on an underside of the wafer 300 instead and, in such a case, the wafer 300 need not be flipped over. Such is shown in
Most wafer level packaging approaches involve attaching the chips to wafers, and then dicing the larger wafers to create 2-high stack chip-on-chip structures that can then be attached to chip-carrier substrates and then packaged in a similar manner to conventional 2D packages. Power delivery is achieved through the bottom chip with through silicon vias to the top chip. Cooling of such structures is then achieved by a TIM inserted between the top chip and a lid attached to the chip-carrier substrate. The bottom chip in the stack has a thermal penalty compared to a 2D chip since the heat dissipated in the bottom chip has to conduct through the top chip and the chip-chip interconnects.
To provide for cooling, in one in one embodiment, the board 720 includes a hole 722 that allows for air to flow to an underside of the wafer. In one embodiment, a heat sink 724 may be attached to the wafer on its underside. The heat sink can be attached to the top of the wafer, the bottom of the wafer or both. Further, referring again to
An example of a heat sink 900 that may be used is shown in
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
