Patent Application
20250201667
The present disclosure relates generally to semiconductor devices, and more particularly to a structure and fabrication method for semiconductor devices including back side power distribution networks and cooling of devices.
A through-silicon via (TSV) or through-chip via is a vertical electrical connection (via) that passes completely through a silicon wafer or die. TSVs are high-performance interconnect techniques used as an alternative to wire-bond and flip chips to create 3D packages and 3D integrated circuits. Compared to alternatives such as package-on-package, 3D packages and 3D integrated circuits are a significant new trend in semiconductor industry. It has tremendous benefits, including higher interconnect speeds and bandwidth, lower power, and smaller package size (miniaturization), as well as enabling new heterogenous integration platform for photonics IC and MEMS et al.
In thermal cooling of 3D package it has been determined that when the through silica via (TSV) and micro-channel structures are on the same substrate there can be a variety of problems. For example, the through silica via (TSV) structures are both electrical connection and thermal cooling, and typically are fabricated with the same processes. Thus, the cooling through silica vias (TSVs) are also well isolated from the silicon substrate, resulting in low heat dissipation efficiency. Additionally, the micro-channels and the TSVs have a space conflict, limiting the package miniaturization.
In one embodiment, cooling for structures including back side power distribution networks (BSPDN) can be provided using embedded through silicon vias (TSV) and micro channels in the front side of a silicon carrier structure, which is one mechanism by which the above noted difficulties with through silicon vias on the same device substrate may be overcome. More particularly, instead of being integrated into the same substrate that results in a space conflict, the through silicon via and the micro-channel structures provided herein for cooling for back side power distribution networks overcome space conflicts by integrating the through silicon vias and micro-channel on different substrates with active devices, e.g., different material layers.
In one embodiment, an electrical device is provided that includes a top die level including first thermal cooling through silicon vias (TSV) and microchannels, and a second die level including second thermal cooling through silicon vias (TSV) and electrical connection through silicon vias, wherein an active device layer is in a level of the electrical device that is separate from a level containing the first thermal cooling through silicon vias (TSV), the second thermal cooling through silicon vias and the electrical connection through silicon vias (TSV).
In one embodiment, the first die level includes a first semiconductor containing layer having the first thermal cooling through silicon vias (TSV) embedded therein. The first die level also includes metal wiring in a first back end of the line (BEOL) level that is in contact with the first thermal cooling through silicon vias (TSV) that are embedded in the first semiconductor containing layer. The first back end of the line (BEOL) level is positioned between a first active device layer of the at least one active device layer and the first semiconductor containing layer having the first thermal cooling through silicon vias (TSV) present therein. The first active device layer is also present on a first back side interconnect.
In some embodiments, the first die level and the second die level are separated by a fluidic channel level, wherein the electrical connection through silicon vias (TSV) extend through the fluidic channel level to transmit electrical current between the first and second die level. The second die level can include a second semiconductor containing layer having the second thermal cooling through silicon vias (TSV) and the electrical connection through silicon vias (TSV) embedded therein. The second die level includes a second active device layer. The second active device layer is separated from the second semiconductor containing layer by a second back end of the line (BEOL) level. The second thermal cooling through silicon vias (TSV) and the electrical connection through silicon vias (TSV) extend into the second back end of the line (BEOL) level. The second active device layer is present on a second back side interconnect.
In another aspect, an electrical device is provided that includes a fluidic channel level including thermal cooling through silicon vias (TSV) embedded through a semiconductor containing layer, wherein a cap layer for the fluidic channel level includes an opening therethrough to channels containing the thermal cooling through silicon vias (TSV). The electrical device also includes at least one active device layer is in a level of the electrical device that is separate from a level containing the thermal cooling through silicon vias (TSV). This electrical device can further include back end of the line (BEOL) level that is in contact with the thermal cooling through silicon vias (TSV) that are embedded in the semiconductor containing layer. The back end of the line (BEOL) level can be positioned between the at least one active device layer and the semiconductor containing layer having the thermal cooling through silicon vias (TSV) present therein. The at least one active device layer is present on a back side interconnect.
In another aspect, an electrical device is provided that includes thermal cooling through silicon vias (TSV) embedded through a semiconductor containing layer, wherein the semiconductor containing layer is at one end of a stacked structure providing the electrical device. The electrical device may also include at least one active device layer in the stacked structure that is present a level of the electrical device that is separate from a level containing the thermal cooling through silicon vias (TSV). In, this embodiment, the stacked structure does not need well isolation for fluidic channels.
In some embodiments, the thermal cooling through silicon vias (TSV) have a face that is coplanar with a face of the semiconductor containing layer. In some embodiments, the thermal cooling through silicon vias (TSV) have a face that protrudes beyond a face of the semiconductor containing layer.
In some embodiments, the electrical device further includes a back end of the line (BEOL) level that is in contact with the thermal cooling through silicon vias (TSV) that are embedded in the semiconductor containing layer. The back end of the line (BEOL) level is positioned between the at least one active device layer and the semiconductor containing layer having the thermal cooling through silicon vias (TSV) present therein. The at least one active device layer can be present on a back side interconnect.
The disclosure will provide details in the following description of preferred embodiments with reference to the following figures wherein:
Detailed embodiments of the claimed structures and methods are disclosed herein; however, it is to be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. In addition, each of the examples given in connection with the various embodiments are intended to be illustrative, and not restrictive. Further, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the methods and structures of the present disclosure. For purposes of the description hereinafter, the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the embodiments of the disclosure, as it is oriented in the drawing figures. The term “positioned on” means that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure, e.g. interface layer, may be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.
In thermal cooling of through silica via (TSV) structures it has been determined that when the active device and the through silica via (TSV) structures are on the same substrate there can be a variety of problems. For example, prior TSV structures suffer from low efficiency and also can result in space conflicts between micro channels and through silicon vias being integrated into the same substrate. The structures provided herein include embedded through silica via (TSV) structures and micro channels in a front side silicon carrier for use in cooling for back-side power distribution network containing devices, in which the active devices and through silicon vias are on different substrates, e.g., are in different material layers of the structure.
More particularly, the active device of the structure including the cooling for back side power distribution networks having embedded through silicon vias and micro-channels in the front side of the silica carrier are based upon, i.e., produced on, the silicon on oxide (SOI) substrate. The term “active device” refers to a devices that include, but are not limited to transistors, resistors and capacitors. The term “active device layer” refers to a wafer, die, or substrate of any size which includes electronic circuit elements such as but not limited to transistors, resistors and capacitors.
This is a separate layer in the final device structure that includes the through silica vias (TSV). As noted, the structure includes cooling for back side power distribution networks having embedded through silicon vias (TSV) and micro-channels in the front side of the silica carrier. To provide this, the active devices are first formed on the semiconductor on insulator (SOI) layer of an SOI substrate. Following formation of the active devices, as well as other process steps, such as metal wiring, e.g., back end of the line (BEOL) processing, the structure may be bonded to a carrier wafer. The through silicon vias (TSV) can be partially embedded in the carrier wafer, and bonding of the carrier wafer to the structure including the active devise can result in the formation of microchannels. This provides that the through silicon vias are in separate layers than the active devices. Thereafter, the bulk substrate of the SOI substrate is removed to expose the backside surface for processing in providing the back side power distribution network. This provides that the level of the device including the active devices is separate from the level of the device including the through silica vias (TSV), which solves the problems of the previous designs in which the through silica vias (TSV) compete for space with the active devices.
The methods and structures of the present disclosure are now discussed with more detail referring to
The term “through silicon via (TSV)” is a vertical metal containing (via) passing completely through a silicon wafer, substrate or die. As used herein, the term “through silicon via” is not intended to only be limited to silicon containing structures, as any substrate through which a via extends is suitable for providing a TSVs, including any composition of the substrate. For example, in addition to silicon containing substrates, such as silicon (Si), silicon germanium (SiGe), silicon doped with carbon (Si: C), and silicon carbide (SiC), TSV structures may be formed through other semiconductor substrates, such as other type IV semiconductors, such as germanium (Ge), and compound semiconductors, such as type III-V semiconductors, e.g., gallium arsenide (GaAs) containing semiconductor substrates.
The metal of the through silicon via 50, 55 may be any elemental metal, such as copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W) and combinations thereof.
As noted, the through silicon vias (TSV) 50, 55 are embedded in a semiconductor containing layer 51. This layer may be a component of a carrier wafer that is used in processing the device for providing back side interconnects, and/or a back side power distribution network. Although the term “semiconductor-containing” is intended to denote any semiconductor material, such as type IV semiconductor and type III-V semiconductors. For example, the semiconductor containing layer 51 may be composed of silicon. This is just one example, and it is not intended that the semiconductor containing layer 51 be limited to only silicon compositions. For example, in addition to silicon, the semiconductor containing layer may be, silicon germanium (SiGe), silicon doped with carbon (Si: C), and silicon carbide (SiC), germanium (Ge), and compound semiconductors, such as type III-V semiconductors, e.g., gallium arsenide (GaAs) containing semiconductor substrates.
The through silicon vias (TSV) may be an electrical connection through silicon via (TSV) 55 or a thermal cooling through silicon via (TSV) 50.
Electrical connection through-silicon vias (TSV) or through-chip via is a vertical electrical connection (via) that passes completely through a semiconductor level, silicon wafer or die. In the embodiment depicted in
Thermal cooling through silicon vias (TSV) are identified by reference number 50. The generation of heat within a confined region inherently gives rise to temperature elevation, and can thereby cause potential performance degradation and, in severe instances, physical harm to a circuit. Thermal cooling through silicon vias (TSV) 50 may be provided by thermally conductive pillars that are utilized to dissipate heat from the stacked electrical structures provided herein. Their role is comparable to that of through-silicon vias (TSVs). Thermally conductive pillars mitigate the effects of heat on 3D ICs. Thermal conductive pillars are vertical interconnects that traverse at least a portion of a thickness of a 3D IC. These pillars are responsible for dissipating heat from the IC's, which is essential for maintaining optimal operating temperatures. For example, copper containing thermally conductive pillars used for thermal cooling through silicon vias can dissipate heat, in which this phenomenon is attributed to the preferential heat transfer through a Cu TSV in the vertical direction caused by the high thermal conductivity of Cu. Copper TSVs are a solution for thermal management in 3D-ICs due to their excellent thermal conductivity properties. By providing an efficient vertical heat dissipation pathway, they can significantly reduce the temperature gradients within stacked ICs, leading to improved performance and reliability.
It is noted that although not depicted in the supplied figures, the thermal cooling through silicon vias (TSV) 50 can further include a liner. For example, if the thermal cooling through silicon vias (TSV) 50 have a core material of copper, and if the design is employing a water based coolant for cooling, the coolant can corrode an exposed Cu via. Therefore, a liner may be integrated to protect a core material from potential corrosion. IN some examples, the liner may be a dielectric, such as silicon nitride, silicon oxide, or any other suitable dielectric material, or combination thereof. The thickness of the liner may be selected to provide for corrosion protection while still maintaining thermal transports. For some dielectric liner materials, the liner for the thermal cooling through silicon vias (TSV) 50 can be much thinner than a liner that is present in the electrical connection through silicon vias 55. It is not required that the material of the liner be a dielectric. For example, in some embodiments, the corrosion protection liner may be composed of a metal. If it is only a metal liner, the composition could be any suitable BEOL metal. Examples may include TaN, TiN, Co, Ti, Ru and combinations thereof.
In some embodiments, the thermal cooling through silicon vias (TSV) 50 can be optionally connected to the ground layers in the back end of the line (BEOL) level 5, and maybe even the power layers. For example, if there is either dielectric fluid or a thinner dielectric liner on the cooling vias to prevent shorts.
The active device layer 10 may include a plurality of semiconductor devices present thereon. In some embodiments, as used herein, “semiconductor device” refers to an intrinsic semiconductor material that has been doped, that is, into which a doping agent has been introduced, giving it different electrical properties than the intrinsic semiconductor. Doping involves adding dopant atoms to an intrinsic semiconductor, which changes the electron and hole carrier concentrations of the intrinsic semiconductor at thermal equilibrium. Dominant carrier concentration in an extrinsic semiconductor determines the conductivity type of the semiconductor. The semiconductor devices may be switching devices, logic devices, and memory devices. Examples of switching devices and/or logic devices suitable for use with the present disclosure include p-n junction devices, bipolar junction transistors (BJT), field effect transistors, fin field effect transistors (FinFETS), Schottky barrier transistors, nanowire/nano-channel transistors and combinations thereof. As used herein, a “field effect transistor” is a transistor in which output current, i.e., source-drain current, is controlled by the voltage applied to the gate. A field effect transistor has three terminals, i.e., gate, source and drain. A “FinFET” is a semiconductor device, in which the channel of the device is present in a fin structure. As used herein, a “fin structure” refers to a semiconductor material, which is employed as the body of a semiconductor device, in which the gate structure is positioned around the fin structure such that charge flows down the channel on the two sidewalls of the fin structure and optionally along the top surface of the fin structure.
The active device layer 10, 110 may also include memory devices. As used herein, the term “memory device” means a structure in which the electrical state can be altered and then retained in the altered state, in this way a bit of information can be stored. The memory device may be volatile or non-volatile. Examples of memory devices suitable for use on the active device wafer include random access memory (RAM), dynamic random access memory (DRAM), embedded dynamic random access memory (EDRAM), phase change material (PCM) memory structures, FLASH memory, molecular memory and combinations thereof.
The active device layer 10, 110 may also include passive electrical devices, such as capacitors and resistors. The active device layer 10, 110 may also include middle of the line contacts 15, 115. As will be explained below the number of active device layers 10 may vary in the following examples, however the active device layer is separate from the layers including the through silicon vias (TSV), e.g., the electrical connection through silicon vias 55, and the thermal cooling through silicon vias (TSV) 50.
Referring to
The microchannels 53 are for coolant passages for coolant flow, thereby allowing coolant to come into contact with the thermal cooling through silicon vias (TSV) 50.
In one embodiment, the first die level includes a first semiconductor containing layer 51 having the first thermal cooling through silicon vias (TSV) 50 embedded therein. The first semiconductor containing layer 51 that is depicted in the embodiment illustrated in
The first die level also includes metal wiring in a first back end of the line (BEOL) level 5 that is in contact with the first thermal cooling through silicon vias (TSV) 50 that are embedded in the first silicon containing layer 51. The first back end of the line (BEOL) level 5 may be a multilayered level of dielectric interlevel dielectrics having metal lines for horizontal electrical communication and metal vias for vertical electrical communication present therein. The first back end of the line (BEOL) level 5 is positioned between a first active device layer 10 and the first semiconductor containing layer 51 having the first thermal cooling through silicon vias (TSV) 50 present therein. The first active device layer 10 is also present on a first back side interconnect 20. The back side interconnect 20 may be a component of a back side power distribution network.
In some embodiments, the first die level and the second die level are separated by a fluidic channel level 73, wherein the electrical connection through silicon vias (TSV) 55 extend through the fluidic channel level 73 to transmit electrical current between the first and second die level. In the embodiment that is depicted in
The second die level can include a second semiconductor containing layer 71 having the second thermal cooling through silicon vias (TSV) 50 and the electrical connection through silicon vias (TSV) 55 embedded therein. Different than the electrical connection through silicon vias (TSV) 55, the second thermal cooling through silicon vias (TSV) 50 are not encased in dielectric or semiconductor material. This can provide that the thermal cooling through silicon vias (TSV) 50 directly contact coolant that passes through the fluidic channel level 73.
The second die level includes a second active device layer 110. The second active device layer 110 is similar to the first active device layer 10 that has been described above. Therefore, the above description of the first active device layer 10 may provide at least one embodiment for the second active device layer 110 that is depicted in
The coolant may be water based. The coolant may be a non-dielectric coolant. Non-dielectric coolants typically have a thermal conductivity of 0.3 W·m−1·K−1 or greater. Examples of non-dielectric coolants include Ethylene Glycol (EG), Propylene Glycol (PG), Methanol/Water, Ethanol/Water, Calcium Chloride Solution, Potassium Formate/Acetate Solution, Liquid Metals, e.g., liquid metals of Ga—In—Sn chemistry, and combinations thereof. In the embodiments, in which dielectric coolants are employed within the coolant passages 110 the seal structures 120 may be omitted. Dielectric coolants generally have a thermal conductivity of less than 0.3 W·m−1·K−1. Dielectric coolants that may be used within the coolant passages 110 include aromatics, such as synthetic hydrocarbons of aromatic chemistry, e.g., diethyl benzene [DEB], dibenzyl toluene, diaryl alkyl, partially hydrogenated terphenyl; silicate-esters, such as Coolanol 25R; aliphatics, such as aliphatic hydrocarbons of paraffinic and iso-paraffinic type (including mineral oils), e.g., aliphatic chemistry (polyalphaolefins or PAO); silicones, such as dimethyl- and methyl phenyl-poly (siloxane); fluorocarbons, such as fluorinated compounds, e.g., perfluorocarbons (i.e., FC-72, FC-77) hydrofluoroethers (HFE) and perfluorocarbon ethers (PFE); and combinations thereof.
Still referring to
The active device layer 10 is in a level of the electrical device that is separate from a level containing the thermal cooling through silicon vias (TSV) 50. The active device layer 10 that is depicted in
The electrical device 101 depicted in
The at least one active device layer 5 is present on a back side interconnect. The back side interconnect 20 depicted in
Still referring to
The electrical device may also include at least one active device layer 10 in the stacked structure that is present a level of the electrical device 101 that is separate from a level containing the thermal cooling through silicon vias (TSV) 50.
In this embodiment, the stacked structure does not need well isolation for fluidic channels.
In some embodiments, the electrical device 101 further includes a back end of the line (BEOL) level 20 that is in contact with the thermal cooling through silicon vias (TSV) 50 that are embedded in the semiconductor containing layer 51. The back end of the line (BEOL) level 20 is positioned between the at least one active device layer 10 and the semiconductor containing layer 51 having the thermal cooling through silicon vias (TSV) 50 present therein. The at least one active device layer 10 can be present on a back side interconnect 120.
The electrical device may also include at least one active device layer 10 in the stacked structure that is present a level of the electrical device 101 that is separate from a level containing the thermal cooling through silicon vias (TSV) 50.
In this embodiment, the stacked structure does not need well isolation for fluidic channels.
In some embodiments, the electrical device 101 further includes a back end of the line (BEOL) level 20 that is in contact with the thermal cooling through silicon vias (TSV) 50 that are embedded in the semiconductor containing layer 51. The back end of the line (BEOL) level 20 is positioned between the at least one active device layer 10 and the semiconductor containing layer 51 having the thermal cooling through silicon vias (TSV) 50 present therein. The at least one active device layer 10 can be present on a back side interconnect 120.
In this embodiment, the stacked structure does not need well isolation for fluidic channels.
While the present disclosure has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present disclosure. It is therefore intended that the present disclosure not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.
