Patent Grant
6875692
As the copper (Cu) interconnection size scales down, the step coverage and overhang of the physical vapor deposition (PVD) barrier is becoming worse for the 0.1 μm generation and beyond, especially with deep vias and trenches.
U.S. Pat. No. 6,197,688 B1 to Simpson describes a palladium-tin (Pb—Sn) catalyst layer 31 for a copper (Cu) electroless deposition.
U.S. Pat. No. 6,022,808 to Nogami et al. describes an electroless Cu deposition with improved electromigration by forming a Sn-doped Cu layer over a Cu layer.
U.S. Pat. No. 6,147,000 to You et al. describes an electroless Cu deposition with improved electromigration by diffusing Sn into a Cu layer.
U.S. Pat. No. 6,268,291 B1 to Andricacos et al. describes an electroless Cu deposition with improved electromigration by implanting Sn into a Cu layer.
U.S. Pat. No. 6,162,667 to Funai et al. describes a method for fabricating thin film transistors that is related to the instant invention.
Accordingly, it is an object of one or more embodiments of the present invention to provide an improved method of reflowing bumps.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a substrate is provided. A patterned dielectric layer is formed over the substrate with the patterned dielectric layer having an opening exposing a portion of the substrate. The opening having exposed sidewalls. A Sn layer is formed directly upon the exposed sidewalls of the opening. A copper seed layer is formed upon the Sn layer within the opening. A bulk copper layer is formed over the copper seed layer, filling the opening. The structure is thermally annealed whereby Sn diffuses from the Sn layer into the copper seed layer and the bulk copper layer forming CuSn alloy within the copper seed layer and the bulk copper layer.
The present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements, regions and portions and in which:
Unless otherwise specified, all structures, layers, steps, methods, etc. may be formed or accomplished by conventional steps or methods known in the prior art.
Initial Structure
As shown in
Structure 10 is preferably a silicon substrate and is understood to possibly include a semiconductor wafer or substrate, active and passive devices formed within the wafer, conductive layers and dielectric layers (e.g., inter-poly oxide (IPO), intermetal dielectric (IMD), etc.) formed over the wafer surface. The term “semiconductor structure” is meant to include devices formed within a semiconductor wafer and the layers overlying the wafer.
A patterned dielectric layer 14 having opening 16 is formed over semiconductor substrate 10 and conductive structure 12 to a thickness of preferably from about 3000 to 15,000 Å and more preferably from about 4000 to 10,000 Å. Dielectric layer 14 is preferably comprised of a low-k dielectric material such as inorganic chemical vapor deposition (CVD) low-k dielectric material, organic spin-on low-k dielectric material or fluorine-doped silicon oxide and is more preferably comprised of fluorine-doped silicon oxide. Dielectric layer 14 has an upper surface 20.
Opening 16 may be a damascene or dual damascene opening and has exposed vertical and horizontal sidewalls 18. Opening 16 exposes a portion 19 of conductive structure 12.
One advantage of the present invention is that no barrier layer is formed within opening 16 upon sidewalls 18.
Formation of Mono-Layer 22 of Sn Upon Sidewalls 18 of Opening 16
As shown in
Sn mono-layer 22 may be formed by a wet acid immersion process using an acid solution comprised of stannous chloride and hydrogen chloride. The acid solution composition includes from about 10 to 150 g/l aqueous stannous chloride and from about 10 to 75 g/l aqueous hydrogen chloride.
Formation of Copper (Cu) Seed Layer 28
As shown in
Formation of Bulk Copper (Cu) Layer 26
As shown in
Thermal Annealing 28
As further shown in
The Sn thus serves to trap Cu atoms by diffusing into the grain boundary between the Sn mono-layer 22 and the Cu seed layer 24/Cu bulk layer 26 so that Cu diffusion and migration into the patterned dielectric layer 14 is inhibited.
Planarization of Cu bulk layer 26
As shown in
The inventors have determined that a marked decrease in the Cu grain boundary diffusivity and electromigration (EM) drift velocity is attributed to Sn trapping of Cu atoms. For example an addition of from about 0.2 to 2.5 weight % of Sn increased the activation energy for Cu EM from about 0.7 to 0.9 eV to about 1.1 to 1.3 eV.
Advantages of the Present Invention
The advantaged of one or more embodiments of the present invention include:
While particular embodiments of the present invention have been illustrated and described, it is not intended to limit the invention, except as defined by the following claims.
| Number | Name | Date | Kind |
|---|---|---|---|
| 6022808 | Nogami et al. | Feb 2000 | A |
| 6147000 | You et al. | Nov 2000 | A |
| 6162667 | Funai et al. | Dec 2000 | A |
| 6197688 | Simpson | Mar 2001 | B1 |
| 6268291 | Andricacos et al. | Jul 2001 | B1 |
| 6426293 | Wang et al. | Jul 2002 | B1 |
