Patent Application
20170215278
There is increasing demand for smaller electronic devices, particularly with respect to radio frequency (RF) wireless communication products, for example. These products include electrical circuitry comprising various components, such as resistors, capacitors, inductors, amplifiers, filters and the like, which are typically provided by printed circuit boards (PCBs) incorporated into the products.
In order to minimize dimensions and maximize use of available space, PCBs typically have substrates formed of multiple layers with electrical circuitry formed between and within the layers. The layers may be formed of “prepreg” material, which generally includes a base material, such as glass fabric impregnated with resin. The prepreg material layers are commonly applied to structural cores or carriers to provide the multi-layered PCBs. In a coreless manufacturing process, the prepreg material layers are eventually detached from the core after a certain number of metal layers, including patterned metal layers, have been added between the prepreg material layers (e.g., to provide fine traces and other electrical circuitry), and a symmetrical build-up is continued without the core for high layer count PCBs. In this case, the detach structure, consisting of layers of prepreg and metal, provide structural support in the absences of the core. Generally, prepreg-based coreless substrates provide a desirable balance between the package thickness reduction and thermo-mechanical stability.
With the continuous demand of functional integration in RF products, design feature scaling is required, and may be achieved in part using a primer based semi-additive patterning (PSAP) process. However, the PSAP process is not available for the starting (bottom) metal layer (layer adjacent to the carrier) of a coreless prepreg manufacturing process since there is no primer layer adjacent to the bottom metal layer, preventing fine traces and circuitry on the bottom metal layer. Alternatives for fine traces can be embedded traces, which reduce the need for additional prepreg and metal layers, but embedded traces increase production lead time, which is critical for products in mobile applications.
Proposed solutions also provide warpage benefits in the symmetric build-up of prepreg-based coreless substrates. Without the proposed solutions, an outer metal layer on one side of the substrate is embedded, resulting in a significant dielectric resin volume imbalance resulting in warpage issues.
The illustrative embodiments are best understood from the following detailed description when read with the accompanying drawing figures. It is emphasized that the various features are not necessarily drawn to scale. In fact, the dimensions may be arbitrarily increased or decreased for clarity of discussion. Wherever applicable and practical, like reference numerals refer to like elements throughout the drawings and written description.
In the following detailed description, for purposes of explanation and not limitation, example embodiments disclosing specific details are set forth in order to provide a thorough understanding of the present teachings. However, it will be apparent to one of ordinary skill in the art having the benefit of the present disclosure that other embodiments according to the present teachings that depart from the specific details disclosed herein remain within the scope of the appended claims. Moreover, descriptions of well-known apparatuses and methods may be omitted so as to not obscure the description of the example embodiments. Such methods and apparatuses are clearly within the scope of the present teachings.
The terminology used herein is for purposes of describing particular embodiments only, and is not intended to be limiting. The defined terms are in addition to the technical, scientific, or ordinary meanings of the defined terms as commonly understood and accepted in the relevant context.
The terms “a”, “an” and “the” include both singular and plural referents, unless the context clearly dictates otherwise. Thus, for example, “a device” includes one device and plural devices. The terms “substantial” or “substantially” mean to within acceptable limits or degree. The term “approximately” means to within an acceptable limit or amount to one of ordinary skill in the art. Relative terms, such as “above,” “below,” “top,” “bottom,” “upper” and “lower” may be used to describe the various elements” relationships to one another, as illustrated in the accompanying drawings. These relative terms are intended to encompass different orientations of the device and/or elements in addition to the orientation depicted in the drawings. For example, if the device were inverted with respect to the view in the drawings, an element described as “above” another element, for example, would now be below that element. Where a first device is said to be connected or coupled to a second device, this encompasses examples where one or more intermediate devices may be employed to connect the two devices to each other. In contrast, where a first device is said to be directly connected or directly coupled to a second device, this encompasses examples where the two devices are connected together without any intervening devices other than electrical connectors (e.g., wires, bonding materials, etc.).
In various representative embodiments, a coreless multi-layered PCB and a method for fabricating the coreless multi-layered PCB are provided, which involve innovative stacking of an organic core, a non-functional prepreg material, and metal layers with corresponding primer material. Generally, to provide an alternative lamination stack-up for the first metal layer of the PCB, an organic core material will be used rather than a conventional “off-the-shelf” carrier material with peelable copper foil. A layer of inexpensive non-functional prepreg material is stacked on the core material, followed by stacking of copper foil coated with primer material, which includes a carrier copper foil, as well. Stacking (or build-up) continues with a layer of functional prepreg material and an additional layer of primer material. Both layers of primer material face the layer of functional prepreg material. This stack is laminated through a hot press. The remainder of the process may follow traditional manufacturing steps. Accordingly, fine lines and space for routing are available in all the layers of the prepreg coreless substrate with the minimal processing time and steps. Also, the warpage risk is minimized in the sequentially built-up prepreg-based coreless substrate.
According to a representative embodiment, a coreless substrate of a PCB is provided. The coreless substrate includes a first outer metal layer corresponding to a first outer most surface of the coreless printed circuit board, post detach process; a first primer layer formed on the first outer metal layer; a first layer of functional prepreg material formed on the first primer layer; a second primer layer formed over the first layer of functional prepreg material; and a second outer metal layer formed on the second primer layer, the second outer metal layer corresponding to a second outer most surface of the PCB.
According to another representative embodiment, a coreless substrate of a laminated PCB is provided. The coreless substrate includes a first outer metal layer providing a first outer most surface of the PCB; a first primer layer disposed adjacent to the first outer metal layer; a first layer of functional prepreg material disposed adjacent to the first primer layer; a second outer metal layer providing a second outer most surface of the printed circuit board, opposite the first outer most surface; a second primer layer disposed adjacent to the second outer metal layer; a second layer of functional prepreg material disposed adjacent to the second primer layer; and at least one buried patterned metal layer and a corresponding at least one buried intermediate primer layer positioned between the first and second layers of the functional prepreg material.
According to another representative embodiment, a method is provided for fabricating a coreless substrate. The method includes providing an organic carrier layer; applying a layer of non-functional prepreg material to the organic carrier layer; applying a stack of a first carrier metal layer, a first release layer, a first metal layer, and a first primer layer to the layer of non-functional prepreg material; applying a first layer of functional prepreg material to the first primer layer; applying an inverted stack of a second carrier metal layer, a second release layer, a second metal layer and a second primer layer to the first layer of functional prepreg material; removing the second carrier metal layer and the release layer from the inverted stack; and removing the second metal layer to expose the second primer layer. The method further includes applying a metal layer to the exposed second primer layer, and patterning the metal layer to form a first patterned metal layer; applying a second layer of functional prepreg material over the first patterned metal layer; applying a third primer layer over the second layer of functional prepreg material; applying a third metal layer on the third primer layer; and removing the organic carrier layer, the layer of non-functional prepreg material, the first carrier layer and the first release layer from the first metal layer, resulting in the first metal layer and the third metal layer being outer most surfaces of the coreless substrate, respectively.
Referring to
The first primer layer 121 provides fine line and space enabling surface and adhesion of the first outer metal layer 111 to the next adjacent layer (e.g., a first layer of functional prepreg material 131) of the coreless substrate 100. In an embodiment, the first primer layer 121 is formed of an epoxy resin at a thickness of approximately 2 μm, for example, although other dielectric materials compatible with semiconductor processes, such as a polymer or another type of resin, may be incorporated without departing from the scope of the present teachings. In an embodiment, a surface of the first outer metal layer 111 contacting the first primer layer 121 is smoother than an opposite surface of the first outer metal layer 111.
The coreless substrate 100 further includes various multiple substrate layers, including layers functional prepreg material (e.g., first layer of functional prepreg material 131, second layer of functional prepreg material 132 and third layer of functional prepreg material 133), buried intermediate primer layers (e.g., second primer layer 122, third primer layer 123 and fourth primer layer 124), and buried patterned metal layers (first patterned metal layer 113 and second patterned metal layer 114), arranged between the first outer (bottom) metal layer 111 and a second outer (top) metal layer 112, where the second outer metal layer 112 may correspond to a second (top) outer most surface of the coreless substrate 100. The first and second outer most surfaces of the coreless substrate 100 (e.g., first and second outer metal layers 111 and 112) are symmetric, in that they are adjacent to corresponding primer layers (e.g., first and second primer layers 121 and 122), respectively.
Like the first outer metal layer 111 discussed above, the second outer metal layer 112 may be formed of copper (Cu) foil at a thickness of approximately 2 μm, for example, although other materials and/or thicknesses may be incorporated without departing from the scope of the present teachings. The second primer layer 122 provides fine line and space enabling surface and adhesion. Like the first primer layer 121 discussed above, the second primer layer 122 is formed of an epoxy resin at a thickness of approximately 2 μm, for example, although other materials and/or thicknesses may be incorporated without departing from the scope of the present teachings.
Also, as mentioned above, the presence of primer layers (e.g., first and second primer layers 121 and 122) adjacent to both outer metal layers (e.g., first and second outer metal layers 111 and 112) enables continuation of a symmetric build-up on the top and bottom outer surfaces of the PCB due to the availability of a primer layer on both sides of the coreless substrate 100, including addition of surface mounted technology (SMT), if desired.
With respect to the intermediate layers in the depicted embodiment, arranged between the first and second primer layers 121 and 122, the first layer of functional prepreg material 131 is formed on the first primer layer 121, the third primer layer 123 is formed on the first layer of functional prepreg material 131, the first patterned metal layer 113 is formed on the third primer layer 123, and the second layer of functional prepreg material 132 is formed on the first patterned metal layer 113 and portions of the third primer layer 123. Further, the fourth primer layer 124 is formed on the second layer of functional prepreg material 132, the second patterned metal layer 114 is formed on the fourth primer layer 124, and the third layer of functional prepreg material 133 is formed on the second patterned metal layer 114 and portions of the fourth primer layer 124. Of course, the number of intermediate layers may vary to provide unique benefits for any particular situation or to meet application specific design requirements of various implementations, as would be apparent to one skilled in the art.
In various embodiments, each of the first through third layers of functional prepreg material 131-133 provides structural support and electrical isolation, and may be formed of glass fabric impregnated with resin, for example, although other materials or combinations of materials may be incorporated without departing from the scope of the present teachings. Each of the first and second patterned metal layers 113 and 114 provides at least a portion of internal circuitry accommodating the electrical circuitry for which the PCB is designed. Various arrangements of traces, vias, terminals, ground planes and other electrical circuitry may be included to provide unique benefits for any particular situation or to meet application specific design requirements of various implementations, as would be apparent to one skilled in the art. The first and second patterned metal layers 113 and 114 may be formed of any metal(s) compatible with semiconductor processes, such copper (Cu), silver (Ag), gold (Au) and/or aluminum (Al), for example, at various thicknesses and having various layouts, as would be apparent to one of ordinary skill in the art. The material(s) and/or thickness(es) of the first and second patterned metal layers 113 and 114 may be the same as or different from those of the first and second outer metal layers 111 and 112, and likewise may be the same as or different from one another, without departing from the scope of the present teachings. The third and fourth primer layers 123 and 124 may be substantially the same as the first and second primer layers 121 and 122, described above, except located adjacent patterned metal layers (e.g., first and second patterned metal layers 113 and 114) as opposed to outer metal layers (e.g., first and second outer metal layers 111 and 112).
In an embodiment, each of the paired first outer metal layer 111 and first primer layer 121 and the paired second outer metal layer 112 and second primer layer 122 may be provided by a preformed sheet of metal/primer layers, such as PF-EL, available from Hitachi Chemical Co., for PCB fabrication. For example,
For example, in an embodiment, the preformed sheet 200 may be inverted and applied to the third layer of functional prepreg material 133, where the primer layer 204 (e.g., corresponding to the second primer layer 122 in
Referring to
In
Referring again to
The second carrier metal layer 117 is peeled away via the second release layer 116, as shown in
In
Referring to
As shown in
For purposed of comparison,
Referring to
In
The carrier metal layer 417 is peeled away via the second release layer 416, as shown in
Referring to
As shown in
The various components, structures and parameters are included by way of illustration and example only and not in any limiting sense. In view of this disclosure, those skilled in the art can implement the present teachings in determining their own applications and needed components, materials, structures and equipment to implement these applications, while remaining within the scope of the appended claims.
