Claims
- 1. A data processing system comprising:
a bus; a Read Only Memory (ROM), connected to said bus, for storing a program; a Random Access Memory (RAM), connected to said bus, for storing data; a data processor for executing said program stored in said ROM; and a least one peripheral device connected to said bus, wherein said program comprises:
a first program having instructions of a first instruction set and a second program having instructions of a second instruction set different from the first instruction set, and wherein when said data processor executes a predetermined instruction of said first instruction set, and said data processor executes an instruction of said second instruction set, wherein said data processor comprises:
a register for storing information which is used to control execution of an instruction of said second program in said data processor, and wherein the execution of an instruction of said second program is prohibited, if said register stores information for prohibiting the execution of the instruction of said second program.
Priority Claims (1)
Number |
Date |
Country |
Kind |
8-015016 |
Jan 1996 |
JP |
|
Parent Case Info
[0001] The present application is a continuation of application Ser. No. 09/382,598, filed Aug. 25, 1999; which is a continuation of application Ser. No. 08/791,811, filed Jan. 30, 1997, now U.S. Pat. No. 6,023,757, the contents of which are incorporated herein by reference.
Continuations (2)
|
Number |
Date |
Country |
Parent |
09382598 |
Aug 1999 |
US |
Child |
10281148 |
Oct 2002 |
US |
Parent |
08791811 |
Jan 1997 |
US |
Child |
09382598 |
Aug 1999 |
US |