Patent Application
20100115385
The instant application claims priority to Indian Patent Application No. 2502/Del/2008, filed Nov. 5, 2008, which application is incorporated herein by reference.
An embodiment of the present disclosure relates to data-storage-array devices and more specifically to detection of data-storage element-selection-errors during data access in data-storage arrays.
The term “word-line” has been used interchangeably with “data-access elements”, “data-storage element” has been used interchangeably with Memory Cell, and “Memory” has been used interchangeably with “data-storage array”.
Soft errors and hard errors are a common occurrence in address decoding, which at times occur due to erroneous selection of a data-access element or word-line in the memory. These errors reduce the probability of achieving a low value of Failure in Time (FIT), thus presenting a huge challenge in this arena.
Word-line selection is enabled by use of word-line generation circuitry, and any failure in the circuitry could lead to a wrong output or to data corruption in the memory. The following fault types and failure modes commonly occur in word-line generation circuitry for both hard errors/failures and soft errors/failures:
A single failure (e.g., short/open) may lead to a no-word-line failure or to a multiple-word-line failure, while for a wrong-word-line failure at least two failures (short/open) are typically required. Chances of at least two failures happening at the same time in one data-access cycle are very rare. Therefore, because no-word-line and multiple-word-line failures often result in the failure of read/write operations, the detection of such errors may be crucial.
Features and aspects of various embodiments of the disclosure will be better understood when the following detailed description is read with reference to the accompanying drawings in which like characters represent like parts throughout the drawings:
Embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. However, the present disclosure is not limited to these embodiments. The present disclosure may be modified in various forms. Furthermore, in the accompanying drawings, like reference numerals are used to indicate like components.
Various embodiments of the present disclosure teach detection of data-access-element-selection errors during data access in a data-storage array. According to an embodiment of the disclosure a system including a data-storage array comprises a first error identifier and a second error identifier to generate an error signal in case of data-access-element-selection errors. The first error identifier generates an error signal on selection of multiple data-access elements in the data-storage array. The second error identifier generates an error signal on absence of data-access element selection in the data-storage array.
An embodiment of the present disclosure comprises a common error-signal generator which provides an output when an error signal is generated by either of said error identifiers.
In accordance with an embodiment of the disclosure, each of said error identifiers comprise a first reference-voltage-level generator, a second reference-voltage-level generator, a voltage-level detector and a comparator. The first error identifier generates a first reference-voltage level greater than a voltage level produced when a single data-access element is selected and less than a voltage level produced when no data-access element is selected. The second reference-voltage-level generator generates a second reference-voltage level less than the voltage level produced when a single data-access element is selected and greater than the voltage level produced when multiple data-access elements are selected. The voltage-level detector detects the voltage produced when a data-access element is selected in the data-storage array. The comparator then compares the detected-voltage level with the first and second reference-voltage level to identify error if any.
According to another embodiment of the disclosure, error signals 104 and 105 enable a common error-signal generator 103 to provide an output 106 on generation of said error signals. According to an embodiment of the disclosure, separate error signals are output, while according to another embodiment of the disclosure, an output is provided by a common error-signal generator. Accordingly, the present embodiment is useful in a multi-bank data storage array where a separate error signal (if any selection error occurs) is generated for each bank.
a, 2b refer to error identifiers 101, 102 according to an embodiment of the disclosure. The error identifiers are used to identify occurrence of data-access-element-selection errors as specified under description of
a illustrates a reference-data-access element with a distributed structure of charge/discharge elements to generate desired reference-voltage levels in accordance with an embodiment of the disclosure. The reference-voltage-level generators generate the reference-voltage levels on the basis of the distributed structure of the charge/discharge elements. Pre-defined widths of these elements are used for generation of the reference-voltage level. The actual data-access element to be selected has charge/discharge elements 302(0), 302<1:126> and 302 (127) of approximate widths W and produces a voltage level when selected by the user. Reference-data-access element with charge/discharge elements 301(0) and 301(1) with widths approximately equal to 0.5 W produces a reference-voltage level which indicates the error of no selection of a data-access element. Reference-data-access element with charge/discharge elements 303(0) and 303(1) with widths approximately equal to 1.5 W indicates the error due to multiple data-access element selection. Sense amplifiers 304 and 305 act as comparators to compare voltage levels produced on selection of a data-access element and the reference-voltage levels. The output of the data-access elements 301, 302 and 303 are applied as F and T to the sense amplifiers 304 and 305. The outputs of the sense amplifiers are then processed through a logic gate 306 to produce a combined error signal.
That is, the transistor 301(1) is designed, when activated with an access voltage on its gate, to draw less current than one of the transistors 302 when activated with an access voltage on its gate—drawing less current results in a higher voltage on the bit line DBLwl—0.5 than on the bit line BLwl due to the slower discharge time for DBLwl—0.5. So if the sense amplifier 304 senses that the transistor 301(1) is drawing more current than the group of transistors 302 is drawing on the line BLwl, then this indicates that none of the transistors 302 is activated for access.
Furthermore, the transistors 303(1) is designed, when activated with an access voltage on its gate, to draw more current than one of the transistors 302 when activated with an access voltage on its gate—drawing more current results in a lower voltage on the bit line DBLwl—1.5 than on the bit line BLwl due to the faster discharge time for DBLwl—1.5. So if the sense amplifier 305 senses that the transistor 303(1) is drawing less current than the group of transistors 302 is drawing on the line BLwl, then this indicates that more than one of the transistors 302 is activated for access.
As an example of the above described embodiment, if no word-line or data-access element is selected, the T generated by reference-data-access element 302 is equal to ‘1’ and the output generated at sense amplifier 304 is ‘1’. The output generated at sense amplifier 305 is ‘0’ and thus after being applied to the logic gate 306 the error signal generated is low i.e. ‘0’ which indicates error. Therefore, error occurring due to no selection of a data-access element is detected.
The occurrence of an error is indicated according to the following table:
The number of charge/discharge elements 301 and 303 and their respective widths are modified according to the user requirement, e.g., according to the reference-voltage levels required by the application.
In another embodiment of the present disclosure, reference-column structures have discharge elements distributed equally on the top and bottom of the structures as shown in
According to an embodiment of the disclosure, the error signals generated at the left terminal and right terminal of the bank data-storage arrays are output separately to indicate the individual occurrence of an error condition.
Embodiments of the method for detecting selection errors during data access in data-storage arrays during each data access and a method for error identification are described in
The two reference-voltage levels are then compared to the voltage level produced by selection of a data-access element 603. If both levels match 604, memory operations taking place are correct. However, if the levels do not match, then an error signal is generated 605. The generated error signal indicates the occurrence of an error in the selection of a data-access element in a data-storage array during each data access.
The various embodiments of the present disclosure described, complete the detection of the error in selection of a data-access element in the data-storage array in the same cycle of a memory operation i.e. within read/write operation in the data-storage array.
Further, the various embodiments described are used for both volatile and non volatile data-storage arrays i.e. memories. The disclosure has wide applications in the field of Petrochemical (Highly intelligent Combustible Gas Detectors), Automotive (human life safety systems in motor vehicles') and various fields where failure could risk to human life; as it helps in achieving high SIL (safety integrity levels).
Although the disclosure shows and describes only some embodiments, other embodiments, combinations, modifications, and applications are contemplated, and the embodiments are capable of changes or modifications within the scope of the inventive concept as expressed herein. The embodiments described hereinabove are further intended to explain best modes known of practicing the disclosure and to enable others skilled in the art to utilize the disclosure in such, or other, embodiments and with the various modifications required by the particular applications or uses of the disclosure. Accordingly, the description is not intended to limit the disclosure as disclosed herein.
From the foregoing it will be appreciated that, although specific embodiments have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the disclosure. Furthermore, where an alternative is disclosed for a particular embodiment, this alternative may also apply to other embodiments even if not specifically stated.
| Number | Date | Country | Kind |
|---|---|---|---|
| 25.2/DEL/2008 | Nov 2008 | IN | national |
