Various embodiments describe in this disclosure are generally directed to methods controllers and devices for determining optimum threshold voltages used to read data values in memory cells of a solid-state, non-volatile memory.
Some embodiments involve methods of operating a memory device. Respective bit error rates affecting memory cells of a solid-state, non-volatile memory are determined for shifted threshold voltages used to read the data values in the memory cells. The shifted threshold voltages include an initial threshold voltage shifted by each of at least three voltage steps. A polynomial fit is applied to the respective bit error rates as a function of the at least three voltage steps. An optimal bit error rate having an associated optimal threshold voltage is determined in response to the polynomial fit. The optimal threshold voltage is applied to read the data values in the cells.
Some embodiments involve a controller that comprises a memory interface, a decoder, and a voltage analyzer. The memory interface is configured to receive data from a solid-state, non-volatile memory, the data read using threshold voltage shifted by each of at least three voltage steps. The decoder is configured to decode the received data and to determine respective bit error rates of cells of the memory for each of the shifted threshold voltages. The voltage threshold analyzer is configured to do at least three tasks. First, it applies a polynomial fit to the respective bit error rates as a function of the shifted threshold voltages. Second, it determines an optimal bit error rate having an associated optimal threshold voltage in response to the polynomial fit. Third, it sends the optimal threshold voltage for use in reading the data to the memory via the memory interface.
Some embodiments involve a device comprising a solid-state, non-volatile memory, read circuitry, a decoder, and a voltage threshold analyzer. The solid-state, non-volatile memory comprises an array of memory cells. The read circuitry is configured to read data from the memory cells using threshold voltages, including reading data using shifted threshold voltages comprising an initial threshold voltage shifted by each of at least three voltage steps. The decoder is configured to decode the data and to determine respective bit error rates of the memory cells for each of the shifted threshold voltages. The voltage threshold analyzer is configured to do at least three tasks. First, a polynomial fit is applied to the respective bit error rates as a function of the shifted threshold voltages. Second, an optimal bit error rate having an associated optimal threshold voltage is determined in response to the polynomial fit. Third, the optimal threshold voltage is sent to the read circuitry, wherein the read circuitry is configured to read data from the memory cells using the optimal threshold voltage.
Non-volatile memory devices are capable of retaining stored data for relatively long periods of time, even to the absence of external power. Non-volatile, solid-state memory include flash memory that programs data into memory cells by applying a voltage causing a charge to be stored on a floating gate of a transistor. The data can be read later from the memory cell by sensing the voltage of the transistor and comparing the sensed voltage to a read reference voltage. Flash memory technologies include NOR flash, NAND flash, 2D NAND flash, 3D NAND flash (also called NAND (VNAND)), and various other technologies known to the industry.
Memory cells are known to exhibit errors caused, for example, by charge leakage, manufacturing defects, and disturb effects. These errors may be manifested as bit errors in the decoded data. A memory device may use a number of measures to account for these errors, such as error correction codes (ECC) that utilize extra data for detecting and correcting bit errors. The memory device may generate a bit error rate (BER) signal based on ECC activity and can use BER to analyze system performance.
Non-volatile memory devices may include single level cells (SLCs) that store one bit of data per cell or may include multi-level cells (MLCs) that can be programmed to store two or more bits of information. Reading data stored in SLCs involves distinguishing between two possible voltage levels. Reading data stored in MLCs involves distinguishing between more than two possible voltage levels. In general, a memory cell may be programmed to a predetermined number of threshold voltage (VT) values.
The memory cells of a memory device can be grouped into data units referred to herein as data pages or blocks. A data page can correspond, for example, to a group of memory cells that are read at substantially the same time. A group of memory pages that are erased at substantially the same time may be referred to as a block or erasure unit. Memory cells are programmed in units of pages and the pages are not re-programmed, once programmed, until after the block of pages is erased. Garbage collection operations can be performed on the blocks of pages, wherein the blocks are erased after active data stored in each block is moved to another location. Thus, each memory cell of the memory device undergoes numerous program/erase (PE) cycles during the lifetime of the memory cell. In floating gate transistor memory cells, each PE cycle can degrade the cell, and after many PE cycles, lead to a decreased ability of the cell to retain data without substantial charge leakage.
The errors in reading the data may be decreased by modifying the threshold voltage (VT) also known as the read reference voltage used to read data stored in the memory cells. Charge retention through such means as, for example, leakage causes VT to shift to the negative voltage shift (−ve) direction while disturb effects forces it to shift to the positive voltage shift (+ve) direction. Thus, as search scheme must be developed to address the uncertainty in the attainment of optimum VT values during error recovery and actual drive operation. The current disclosure concerns an adaptive VT search scheme that not only finds the optimum VT value but also minimizes the search time to reduce the impact on Input/Output (IO) performance.
Embodiments described in this disclosure involve methods, controllers, and devices for determining whether a VT results in the lowest BER or needs to be changed to a more optimum VT with an even lower BER. In various implementations, a procedure is advanced for determining whether a new optimum threshold voltage exists that is then used in place of the initial threshold voltage in each memory cell that is analyzed.
The method embodiment for operating a memory device to determine an optimum VT comprises four steps. The first step is to determine respective BERs reported at the memory cells of a solid-state, non-volatile memory for shifted voltages, (VT values) used to read the data values in the memory cells, the shifted VT values comprising an initial VT shifted by each of at least three voltage steps. The second step is to apply a polynomial fit to the respective BERs as a function of the at least three voltage steps. The third step is to determine, in response to the polynomial fit, an optimal BER having an associated optimal VT. The fourth step is to apply the optimal VT to read the data values in the cells.
The size of the steps is often of a quantity chosen to adjust the initial VT in a manner that is likely to allow a new VT to be found with a lower BER when the cell has experienced either sufficient leakage or disturb effects to meaningfully increase the initial BER associated with the initial VT. Typically, a small shift is first chosen to determine if a meaningfully lower BER can be obtained. However, larger shift quantities may be chosen if the earlier results are inconclusive.
In some embodiments, a larger shifted VT is measured after a minimum BER is detected that is lower than that of the BER associated with the initial VT. This provides a measurement that permits a better fit of the data to a polynomial. The large shift also is used as a sanity check even if a new optimum VT was found to ensure that the actual minimum BER is a global minima and not a local one that can be ignored.
If the consistency decision of step 320 is yes, then at least two more samples are gathered for VT values having one and two more steps in voltage in the direction being analyzed as shown in step 340. Then the analysis proceeds to step 345 where consistency is determined. Here consistency means that the BERs are still trending downward and inconsistency means that at least the BERs associated with a shifted VT that is furthest from the initial VT is either flat or higher than the BER for the shifted VT immediately preceding that value. If consistency is determined, the analysis goes back to step 340 to gather more samples. If inconsistency is determined, the analysis proceeds to the select optimal VT as shown generally in step 350. Briefly, this step involves a polynomial interpolation in step 355 to generate a polynomial that fits the data for the direction of interest. Then an optimal VT is determined from the polynomial as shown in step 375.
Several examples illustrate the above process. In one example, a VT with a +1ve shift and a VT with −1ve shift show no decrease in associated BER over the BER associated with the initial BER. This continues for increased sizes of shifts until a maximum level of shifting occurs. No change in initial VT is made. In another example, a VT with −1ve shows a decrease in BER over the BER associated with the initial VT. The BERs for the first two additional shifted pairs of samples were consistently lower in associated BER over that of the immediately preceding shifted VT. The third additional pair was inconsistent with the BER being flat and increasing for the −6ve and −7ve shifted VT. A polynomial curve is fit to the data of BER vs. VT, a minimum BER is determined, and an associated optimal VT is determined replacing the initial VT.
If inconsistency is observed in the positive direction in step 518 then the analysis proceeds to step 520 where both directions are analyzed for inconsistency. Then, if only one direction has been analyzed at this point, steps 530 to 534 conduct the same analysis for −ve as steps 512 to 518 did for the positive branch. If both directions show inconsistencies, then the analysis proceeds to step 538 where the shift size is increased and the step 540 directs the analysis to begin again at step 500. As discussed above, the increase in ve has a predetermined limit. When the limit is reached, the analysis terminates rather than repeating and the default VT-old is unchanged.
If inconsistencies are not observed in the negative −ve direction in step 536, then the analysis proceeds down steps 542, 544 and 524, or 542, 550 and 530 in a manner similar to that discussed for the +ve from step 520 to step 522 to step 524, or step 520 to step 526 to step 512.
The above analysis is for each VT. However, a memory cell may have both an unchanged VT and an optimized VT. A VT exists for each pair of digital entry values. Thus, an SLC having only one pair of “1” and “0” for each memory cell has one VT. However, it is possible to have more than one VT in a memory cell. MLCs have more than one VT, each associated with a pair of individual digital entry values. Thus, an MLC may have at least one initial VT that was unchanged and at least one optimum VT that was changed.
The memory controller embodiment for operating a memory device to determine an optimum VT comprises a memory interface, a decoder, and a voltage analyzer. The memory interface is configured to receive data from a solid-state, non-volatile memory, the data read using VT shifted by each of at least three voltage steps. The decoder is configured to decode the received data and to determine respective BERs of cells of the memory for each of the shifted VT values. The VT analyzer is configured to perform at least three tasks. First, it applies a polynomial fit to the respective BERs as a function of the shifted VT values. Second, it determines an optimal BER having an associated optimal VT in response to the polynomial fit. Third, it sends the optimal VT for use in reading the data to the memory via the memory interface.
This embodiment has been discussed previously. The memory controller has been discussed above in
The device embodiment involves a device comprising a solid-state, non-volatile memory, read circuitry, a decoder, and a voltage threshold analyzer. The solid-state, non-volatile memory comprises an array of memory cells. The read circuitry is configured to read data from the memory cells using VT values, including reading data using shifted VT values comprising an initial VT shifted by each of at least three voltage steps. The decoder is configured to decode the data and to determine respective BERs of the memory cells for each of the shifted VT values. The VT analyzer is configured to perform at least three tasks. First, a polynomial fit is applied to the respective BERs as a function of the shifted VT values. Second, an optimal BER having an associated optimal VT is determined in response to the polynomial fit. Third, the optimal VT is sent to the read circuitry, wherein the read circuitry is configured to read data from the memory cells using the optimal VT.
This embodiment has been discussed previously. The device has been discussed above in general and in
The foregoing description of the example embodiments have been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the inventive concepts to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. Any or all features of the disclosed embodiments can be applied individually or in any combination, not meant to be limiting but purely illustrative. It is intended that the scope be limited by the claims appended herein and not with the detailed description.
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