Patent Application
20240178219
The present disclosure relates to semiconductor structures and, more particularly, to a device with plasma induced damage (PID) protection and methods of manufacture and operation.
Plasma induced damage (PID) is a source of yield loss and product field returns. In particular, PID may occur after a wafer goes through a multi back end of the line (BEOL) tool routing to charge the wafer. In this scenario, PID may cause an early fail and a loss of device performance.
In known circuits, gate protection diodes may help reduce or eliminate PID. However, gate protection diodes add restrictions to a design and reduce performance of a product. In addition, in known circuits, ground rule requirements to ensure an allowed metal to gate oxide area ratios are complex, represent challenges and add limitations to circuit designers.
In known circuits, PID mitigation may include improving tool control, adding gate protection devices to eliminate electrostatic and triboelectric charge accumulation, and limit back end of the line (BEOL) wiring. In an example, a MOSFET may include a reverse diode (or back to back diode) from a gate to a substrate to provide a current leakage path and voltage neutralization if a displacement voltage builds up from the PID. However, in this example, the circuit will only work in an inversion mode because the diode will be forward biased in an accumulation mode. Further, in this example, additional parasitic capacitance and parasitic impedance occurs on a host device (e.g., transistor). Thus, known circuits do not have the ability to prevent parasitic capacitance or parasitic impendence, and include restrictive ground rules.
In an aspect of the disclosure, a structure comprises: a transistor comprising a gate structure, source region and a drain region, the transistor being on a substrate; and a first gate-protecting line connecting to the gate structure of the transistor and the substrate.
In an aspect of the disclosure, a structure comprises: a gate structure of a transistor on a substrate; a first gate-protecting line at a first wiring level above the transistor, the first gate-protecting line connecting to the gate structure of the transistor and the substrate and includes a cut which breaks any connection between the gate structure and the substrate; and a second gate-protecting line at a second wiring level above the first wiring level, the second gate-protecting line connecting the gate structure of the transistor and the substrate.
In an aspect of the disclosure, a method comprises: forming a gate structure of a transistor on a substrate; forming a first gate-protecting line at a first wiring level above the transistor, the first gate-protecting line connecting to the gate structure of the transistor and the substrate and includes a cut which breaks any connection between the gate structure and the substrate; and forming a second gate-protecting line at a second wiring level above the first wiring level, the second gate-protecting line connecting the gate structure of the transistor and the substrate, wherein the cut is formed after the formation of the second gate-protecting line.
The present disclosure is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure.
The present disclosure relates to semiconductor structures and, more particularly, to a device with plasma induced damage (PID) protection and methods of manufacture and operation. In embodiments, the present disclosure includes a protecting metal line from a gate pad to a local n-well or a substrate. The present disclosure may also include lower metal lines that have a sever or are broken between a gate to a n-well or a substrate. Advantageously, the present disclosure may provide a method of PID protection while eliminating issues in known circuits such as restrictive ground rules, parasitic impedance, parasitic capacitance, and an inability to operate devices in an accumulation mode. In addition, the present disclosure may also provide the ability to protect metal-oxide-semiconductor field-effect transistors (MOSFETS) with minimal additional area.
In more specific embodiments, the present disclosure may include a metal line connecting a MOSFET gate contact to an n-well or a substrate to create a conductive path for charge equilibrium during BEOL processing to maintain approximately a constant net zero volts across an oxide. In embodiments, fabricating such structure may include fabricating a lower metal line (i.e., lowest wiring level above a transistor) from either the gate to the substrate or the gate to the n-well. After the formation of the lower metal line is completed, an upper metal line may be fabricated over the lower metal line. In this configuration, the lower metal line may be severed after fabricating the upper metal line. The method may further include additional metal lines at upper levels, with the lower metal lines being broken.
The device of the present disclosure may be manufactured in several ways using a number of different tools. In general, though, the methodologies and tools are used to form structures with dimensions in the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to manufacture the device of the present disclosure have been adopted from integrated circuit (IC) technology. For example, the structures are built on wafers and are realized in films of material patterned by photolithographic processes on the top of a wafer. In particular, the fabrication of the device uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask.
In
In
In
The M3 gate-protecting metal line 18 may be a duplicative connection between the gate (G) of the transistor 11 to the semiconductor substrate or local N-well (NW). In this circuit design, though, the gate-protecting metal lines 14, 16 may be severed or cut as represented by reference numerals 15, 17, respectively. The gate-protecting metal line 16 may be severed or cut after formation of the gate-protecting metal line 18. The gate-protecting metal line 18 maintains the direct connection between the gate and n-well or substrate.
Although the circuits 10, 10a, 10b are shown with respective gate-protecting metal lines 14, 16, and 18 corresponding to M1, M2, and M3 wiring levels, it should be understood by those of skill in the art that other gate-protecting metal lines at different wiring levels are also contemplated herein. For example, there may be any number “N” gate-protecting metal lines in the BEOL stack, with “N” being any integer corresponding to a number of wiring levels below the non-metal lines of the transistor circuit 10. Further, in embodiments, each of the gate-protecting metal lines 14, 16, and 18 may comprise aluminum, copper, tungsten, or any other suitable metal. Advantageously, by breaking (e.g., etching) the gate-protecting metal lines 14, 16 in
The gate-protecting metal lines 14, 16, 18, 40, 44 may be formed on respective wiring levels M1-M5. The gate-protecting metal lines 14, 16, 18, 40 may be formed at lower wiring levels M1-M4, than the top gate-protecting metal line 44 on wiring level M5. The gate-protecting metal lines 14, 16, 18, 40 may each include a sever or cut at reference numerals 15, 17, 21, 22, respectively, to ensure that there is no connection between the gate structure (G) and the substrate or N-well 12. Via 53 may be connected between the gate-protecting metal line 40 and the top gate-protecting metal line 44. Via 51 may be connected between the gate-protecting metal line 40 and the gate-protecting metal line 18. Via 39 may be connected between the gate-protecting metal line 18 and the gate-protecting metal line 16. Via 23 may be connected between the gate-protecting metal line 16 and the gate-protecting metal line 14. A tie down device (e.g., a stack of diodes) as represented by reference numeral 45 may be used, for example, in bulk Si technology. As shown in
In
The silicide 28 may be formed on the patterned semiconductor materials. As should be understood by those of skill in the art, the silicide process begins with deposition of a thin transition metal layer, e.g., nickel, cobalt, or titanium, over fully formed and patterned semiconductor devices (e.g., source and drain regions and gate structure). After deposition of the material, the structure is heated allowing the transition metal to react with exposed silicon (or other semiconductor material as described herein) in the active region 24 of the semiconductor device (e.g., source, drain, gate contact region) forming a low-resistance transition metal silicide 28. Following the reaction, any remaining transition metal is removed by chemical etching, leaving silicide contacts 28 in the active regions of the device.
In embodiments of the present disclosure, the top gate protecting metal line 44 at wiring level M5 may be cut (as shown in
The devices may be utilized in system on chip (SoC) technology. The SoC is an integrated circuit (also known as a “chip”) that integrates all components of an electronic system on a single chip or substrate. As the components are integrated on a single substrate, SoCs consume much less power and take up much less area than multi-chip designs with equivalent functionality. Because of this, SoCs are becoming the dominant force in the mobile computing (such as in Smartphones) and edge computing markets. SoC is also used in embedded systems and the Internet of Things.
The method(s) as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips may be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either surface interconnections and buried interconnections or both surface interconnections and buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product may be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
