Claims
- 1. A device, comprising:
- a substrate including semiconductor material; and
- a field effect transistor (FET) including a source, a drain, a gate insulator and a gate formed in and on said substrate, said gate insulator comprising a layer of silicon oxide and said gate comprising a polysilicon layer on said gate insulator over a region of said substrate between said source and said drain, said gate including on said polysilicon a layer of tantalum silicide, CHARACTERIZED IN THAT
- said layer of tantalum silicide has at least one essentially vertical wall where the maximum lateral displacement of any portion of said wall relative to any other portion of said wall is less than about one-quarter the height of the wall, and said FET is essentially free of conductive etch residues.
Parent Case Info
This application is a continuation of application Ser. No. 616,915, filed June 4, 1984, now abandoned, which is a continuation-in-part of U.S. patent application Ser. No. 266,433 filed on May 22, 1981 by Jean S. Deslauriers and Hyman J. Levinstein.
US Referenced Citations (1)
Number |
Name |
Date |
Kind |
4488166 |
Lehrer |
Dec 1984 |
|
Non-Patent Literature Citations (1)
Entry |
Leung et al.--IEEE-IEDM Tech. Dig.--1980, "Refractory Metal Silicide/N+ Polysilicon in CMOS/SOS". |
Divisions (1)
|
Number |
Date |
Country |
Parent |
449441 |
Dec 1992 |
|
Continuations (1)
|
Number |
Date |
Country |
Parent |
616915 |
Jun 1984 |
|
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
266433 |
May 1981 |
|