Claims
- 1. A data processing device comprising:
a circuit having status conditions wherein a particular set of the status conditions can occur in operation of the circuit; an instruction register operative to hold a branch instruction conditional on a particular set of the status conditions; a decoder connected to said instruction register and said circuit; and a program counter coupled to said decoder wherein said decoder is operable to enter a branch address into the program counter in response to the branch instruction when the particular set of the status conditions of said circuit are present.
- 2. The data processing device of claim 1 wherein said circuit includes an electronic computation unit.
- 3. The data processing device of claim 1 wherein said instruction register includes locations for holding bits representative of the branch instruction, and at least three status bits representative of at least three conditions of the circuit.
- 4. The data processing device of claim 3 wherein said instruction register further includes locations for masking bits to select any one or more of the status bits for said decoder.
- 5. The data processing device of claim 4 wherein said circuit includes an accumulator.
- 6. The data processing device of claim 1 wherein said circuit includes a register for holding numerical values and said instruction register has locations for bits representing conditions including A) contents relating to a predetermined value and B) overflow.
- 7. The data processing device of claim 1 wherein said circuit includes a register for holding numerical values and said instruction register has locations for bits representing conditions including A) contents relating to a predetermined value and B) carry.
- 8. The data processing device of claim 1 wherein said circuit includes a register for holding numerical values and said instruction register has locations for bits representing conditions including A) carry and B) overflow.
- 9. The data processing device of claim 8 wherein said instruction register further has a location for a bit representing C) contents relating to a predetermined value.
- 10. The data processing device of claim 1 wherein said circuit includes an accumulator and said instruction register has predetermined locations for bits representing conditions including A) equal to zero, B) less than zero, C) carry and D) overflow.
- 11. The data processing device of claim 10 wherein said decoder includes logic array means for decoding the predetermined locations corresponding to said conditions when the branch instruction is present in the instruction register.
- 12. The data processing device of claim 11 wherein said decoder includes means for also decoding predetermined mask locations corresponding to said conditions to selectively respond to certain ones of the conditions when the branch instruction is present in said instruction register.
- 13. The data processing device of claim 10 wherein said instruction register further has mask locations and said decoder includes means for decoding the mask locations corresponding to said conditions to selectively respond to certain ones of the conditions when the branch instruction is present in said instruction register.
- 14. A data processing device comprising:
memory means for storing instructions at different addresses; circuit means for executing electronic operations having status conditions wherein a particular set of the status conditions can occur in operation of the circuit means; means for temporarily holding the instructions successively, the instructions including a conditional branch instruction conditional on the particular set of the status conditions; means for generating addresses of said memory means in incremental sequence and initiating successive transfers of said instructions at the addresses respectively to said means for temporarily holding; and means, connected to said circuit means, for decoding said instructions to direct the electronic operations and further responsive to the conditional branch instruction for signaling said means for generating addresses to supply a branch address that departs from the incremental sequence when the particular set of the status conditions of said circuit are present.
- 15. The data processing device of claim 14 wherein said means for temporarily holding has bit locations and said means for decoding includes means for selectively decoding predetermined ones of the bit locations as mask bits when said conditional branch instruction is present.
- 16. The data processing device of claim 14 wherein said means for temporarily holding has bit locations and said means for decoding includes means for selectively decoding predetermined ones of the bit locations as status bits when said conditional branch instruction is present.
- 17. The data processing device of claim 14 wherein said means for generating addresses and initiating transfers includes a program counter.
- 18. The data processing device of claim 14 wherein said means for temprorarily holding instructions includes an instruction register.
- 19. The data processing device of claim 14 wherein said circuit means includes an electronic computation unit and the device has a pipeline organization.
- 20. The data processing device of claim 14 wherein said memory means includes a read only memory (ROM).
- 21. A data processing device comprising:
a memory for storing instructions; an instruction register; a program counter for holding an address of an instruction; a controller for transferring from said memory to said instruction register the instruction having the address held in said program counter; an accumulator; and a decoder connected to said accumulator and said instruction register to insert a branch address into said program counter depending on whether at least three bits of a particular instruction in said instruction register correspond to respective conditions occurring in said accumulator.
- 22. The data processing device of claim 21 wherein three of said bits respectively indicate the presence or absence of conditions representing A) accumulator contents equal to zero, B) accumulator contents less than zero and C) accumulator carry.
- 23. The data processing device of claim 21 wherein three of said bits respectively indicate the presence of absence of conditions representing A) accumulator contents relating to a predetermined number, B) accumulator and C) accumulator overflow.
- 24. The data processing device of claim 21 wherein said decoder further includes means for selectively ignoring predetermined bits of said instruction register when the particular instruction is present.
- 25. A data processing system comprising:
an analog-to-digital converter; an electronic processor connected to said analog-to-digital converter and including an electronic computation unit for executing multiple-precision arithmetic and an accumulator having conditions including A) carry, B) overflow and C) contents relative to a predetermined number; an instruction register; and a decoder connected to said instruction register and said accumulator for branching when conditions of the accumulator selected by the contents of the instruction register actually occur.
- 26. The data processing system of claim 25 further comprising an instruction memory connected to said electronic processor.
- 27. The data processing system of claim 25 further comprising an output circuit connected to said electronic processor and responsive to results of executing the multiple precision arithmetic.
- 28. A method of operating a data processing system having an instruction register, a program counter, and a circuit that has status conditions wherein a particular set of the status conditions can occur in operation of the circuit, the method comprising the steps of:
entering a branch instruction into said instruction register with status bits representing the particular set of status conditions; and electronically decoding the contents of the instruction register in accordance with the branch instruction to enter a branch address into the program counter, providing the circuit currently has the particular set of status conditions represented by the status bits in the instruction register.
- 29. A data processing device comprising:
first circuit means for executing operations and having status conditions wherein a particular status condition cap occur in operation of the first circuit means; instruction register means for holding a conditional instruction directing the first circuit means to execute a further operation provided that the particular status condition is present; decoder means connected to said instruction register means and said first circuit means, for decoding the conditional instruction; and control circuit means, operative in response to said decoder means and connected to said first circuit means, for causing said first circuit means to execute the further operation when the particular status condition is present and otherwise to cause the first circuit means to omit the further operation.
- 30. The data processing device of claim 29 wherein said first circuit means for executing operations has a pipeline organization and a branch for the particular status condition would cause a pipeline hit, whereby said conditional instruction is advantageous compared to the branch.
- 31. The data processing device of claim 29 wherein said first circuit means includes an accumulator and the particular status condition is an accumulator status condition.
- 32. The data processing device of claim 29 wherein said instruction register means has predetermined status locations for bits representing status conditions and said decoder means includes means for decoding the predetermined status locations corresponding to said status conditions when the conditional instruction is present in the instruction register means.
- 33. The data processing device of claim 32 wherein said instruction register means has predetermined mask locations and said decoder means includes means for also decoding the predetermined mask locations corresponding to said status conditions to selectively respond to certain ones of the predetermined status locations when the conditional instruction is present in said instruction register means.
- 34. A data processing system comprising:
an analog-to-digital converter; an electronic processor connected to said analog-to-digital converter and including an electronic computation unit for executing operations and an accumulator having status conditions including A) carry, B) overflow and C) contents relative to a predetermined number wherein a particular one or more of the status conditions can occur in operation; an instruction register operative to hold a conditional instruction directing the electronic processor to execute a further operation provided the particular status condition is present; and a control circuit connected to said instruction register and said accumulator to cause said processor to execute the further operation when the conditional instruction and the particular status condition are present and otherwise to cause the electronic processor to omit the further operation when the conditional instruction is present and the particular status condition is absent.
- 35. The data processing system of claim 34 further comprising an instruction memory connected to said electronic processor.
- 36. The data processing system of claim 34 further comprising a video output circuit connected to said electronic processor and a video display connected to said video output circuit.
- 37. The data processing system of claim 34 wherein said electronic computation unit includes means for executing multiple precision arithmetic.
- 38. The data processing system of claim 34 wherein said conditional instruction directs the circuit to execute or omit a plurality of operations depending on the status condition being present.
- 39. A method of operating a data processing system having an instruction register and a circuit for executing operations according to instructions in the instruction register, the circuit having status conditions wherein a particular status condition can occur in operation of the circuit, the method comprising the steps of:
entering a conditional instruction into said instruction register directing the circuit to execute a further operation provided the particular status condition is present; and electronically decoding the contents of the instruction register in accordance with the conditional instruction to cause the circuit to execute the further operation when the particular status condition is present and otherwise to cause the circuit to omit the further operation.
- 40. A data processing device comprising:
a first circuit having status condition lines wherein a particular set of status conditions can occur in operation of the circuit; an electronic memory having memory locations occupied by instructions at addresses of said memory; an instruction register connected to an output of said electronic memory; a program counter connected to address said electronic memory thereby to transfer a conditional instruction to said instruction register directing the first circuit to execute a further operation provided that the particular status condition is present; and a control circuit having logic circuitry with inputs connected to said instruction register and to said status condition lines from said first circuit, said control circuit further having an output connected to said first circuit to initiate the further operation by the first circuit when the status condition lines are active with the particular set of status conditions and otherwise to cause the first circuit to omit the further operation.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is related to coassigned applications Ser. No. ______, (TI-14079), Ser. No. ______, (TI-14080), Ser. No. ______, (TI-14081), Ser. No. ______, (TI-14082), Ser. No. ______, (TI-14083), and Ser. No. ______, (TI-14147), all filed contemporaneously herewith and incorporated herein by reference.
Divisions (4)
|
Number |
Date |
Country |
Parent |
09431801 |
Nov 1999 |
US |
Child |
10337028 |
Jan 2003 |
US |
Parent |
09360488 |
Jul 1999 |
US |
Child |
09431801 |
Nov 1999 |
US |
Parent |
08906863 |
Aug 1997 |
US |
Child |
09360488 |
Jul 1999 |
US |
Parent |
08293259 |
Aug 1994 |
US |
Child |
08906863 |
Aug 1997 |
US |