The description relates to manufacturing semiconductor devices and manufacturing integrated circuits (ICs).
Non-Etched Adhesion Promoter (NEAP) leadframe surface finish is now commonly used in manufacturing semiconductor devices. This is primarily in view of the excellent adhesion to the molding compound facilitated by a very thin oxide layer. For instance, such a thin oxide layer can be formed on a silver-plated leadframe with the NEAP product marketed under the trade designation “AgPrep” by Atotech Deutschland GmbH.
It is otherwise noted that NEAP finish can be hardly proposed for high-reliability packages where high thermal and electrical conductivity are desired features.
Indeed, a NEAP oxide layer may exhibit reduced compatibility with solder materials involving some sort of sintering (such as hybrid glue and sintering paste, for instance) or based on metal bonds (such as soft solder and solder paste, for instance), which results in reduced bonding strength between an integrated circuit chip and the leadframe.
One or more embodiments of the present disclosure contribute in overcoming the drawbacks outlined in the foregoing while also providing an improved process for mounting semiconductor chips on a substrate, such as a NEAP-finished leadframe.
One or more embodiments relate to a method having the features set forth in the detailed description that follows. One or more embodiments relate to a corresponding semiconductor device (an integrated circuit, for instance).
The claims are an integral part of the technical teaching provided herein in respect of the embodiments.
One or more embodiments involve (selective) removal of the NEAP layer, via laser beam ablation, for instance, in order to restore wettability of the underlying material (copper, silver or various alloys, for instance) which facilitates soft-solder die attachment in combination with NEAP handling extended to flip-chip power Quad-Flat No-leads (QFN) die packages.
In various examples presented herein, ablated NEAP areas are used as a solder mask (for, e.g., hybrid glue) in order to define die-to-leadframe connection areas for a semiconductor chip such as a flip-chip power die.
In various examples presented herein, ablated NEAP areas match a wettable area in the die when flipped. This can provide electrical connection to the power die. For instance, a power transistor may have its drain and gate connected to a die pad with the source connection provided by a further clip.
In various examples presented herein, a device package and an associated manufacturing method may involve selective removal of NEAP to provide a sort of solder mask defining at least two electrically isolated die pad regions to provide two corresponding areas for the provision of die attach material; flip-chip mounting of a die can thus occur at the solder wettable regions thus formed.
One or more embodiments will now be described, by way of example, with reference to the annexed figures, wherein:
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.
The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.
The edges of features drawn in the figures do not necessarily indicate the termination of the extent of the feature.
In the ensuing description one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.
Reference to “an embodiment” or “one embodiment” in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment” or “in one embodiment” that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment.
Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.
The references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.
A semiconductor device 10 as considered herein (see, e.g., the plan view of
Such a device 10 includes (along with other elements/features not visible in the figure for simplicity) a substrate such as a so-called leadframe 12 (of, e.g., copper, silver or various alloys) intended to include (mutually isolated) die pad areas 12A, 12A′ where a semiconductor chip or die 16 can be attached, e.g., via electrically conductive solder material 120 (see, e.g.,
In the following, mounting a single chip or die 16 on the substrate 12 will be discussed for simplicity; in various embodiments, plural chips or dice 16 can be mounted on the substrate (leadframe) 12.
The leadframe 12 also includes an array of electrically conductive leads 12B around the die pad(s) 12A, 12A′ and the semiconductor chip or die 16 (the terms chip and die are used herein as synonyms) attached thereon.
The designation “leadframe” (or “lead frame”) is currently used (see, for instance the USPC Consolidated Glossary of the United States Patent and Trademark Office) to indicate a metal frame that provides support (e.g., at a die pad such as 12A) for an integrated circuit chip or die 16 (these terms are used herein as synonyms) as well as electrical leads such as 12B to interconnect the integrated circuit in the die or chip to other electrical components or contacts.
Leadframes are conventionally created using technologies such as a photo-etching technology. With this technology, metal material (e.g., copper, silver or various alloys) in the form of a foil or tape is etched on the top and bottom sides to create various pads and leads.
A mass 18 of package molding compound—an epoxy resin, for instance—whose outline is illustrated in dashed lines in
It is noted that the indication “No-leads” referred to a QFN device 10 as depicted herein is not in contradiction with such a package comprising an array of leads such as 12B: in fact, the indication “No-leads” is related to the fact that a QFN package is substantially exempt from external (distal) tips of the leads in the leadframe 12 protruding from the encapsulation 18.
As illustrated, the device 10 comprises (at least) one semiconductor chip or die 16 mounted bridge-like between the first die pad 12A and the second die pad 12A′ in the leadframe 12. This may be via die attachment material 120.
A soft-solder attach material can be exemplary of such a die attachment material.
The designation “soft-solder” belongs to the current language in the area of semiconductor circuit manufacturing as a conventional designation for solders such as, for instance, tin-lead (Sn—Pb) solders that are commercially available with tin concentrations between 5% and 70% by weight. A composition of Pb 95%/Sn 5% or sometimes 1-2% Ag and Sn balance may be exemplary of such a soft-solder attach material.
As discussed, Non-Etched Adhesion Promoter (NEAP) leadframe surface finish is now used in manufacturing semiconductor devices in view of the excellent adhesion to the molding compound facilitated by a very thin oxide layer.
It is otherwise noted that NEAP finish can be hardly proposed for high-reliability packages where high thermal and electrical conductivity are desired features. Indeed, a NEAP oxide layer may exhibit reduced compatibility with materials involving some sort of sintering (such as hybrid glue and sintering paste, for instance) or based on metal bonds (such as soft solder and solder paste, for instance).
As discussed previously, while promoting good adhesion with the package compound (e.g., 18 in
Even without wishing to be bound to any specific theory in that respect, one may note, for instance, that in hybrid glues, hybrid die attach material—with high resin contents to exploit (also) chemical adhesion—has limited thermal and electrical performance.
Conversely, a reduced amount of resin and a high content of filler (e.g., silver particles) may result in a reduced adhesion to a NEAP leadframe. This is in contrast with standard glues, which may achieve good adhesion to a thin oxide layer thanks to the high amount of resin.
Also, the portion of the leadframe under the die pad area could be protected through masking during the process of forming the last oxide layer of NEAP. This would otherwise lead to a fairly expensive process, not flexible enough to adapt to variable die sizes and shapes.
Examples as considered herein address these issues along the same line of document US 2020/402895 A1 (assigned to the same assignee of the present application), where selectively removing a surface layer on a die pad before die attach is proposed.
As noted,
It will be otherwise appreciated that the sequence of steps of
In the first place, manufacturing a single device 10 is illustrated in
In fact, current production processes of semiconductor devices involve a chain or string of devices manufactured simultaneously to be finally separated into individual devices 10 via a “singulation” step (e.g., cutting the chain or string between adjacent devices via a blade).
Also:
As discussed, mounting a single chip or die 16 on the leadframe (substrate) 12 will be considered herein for simplicity. In various embodiments, plural chips or dice 16 can be mounted on the leadframe 12.
Also, the topology of the leadframe 12 illustrated herein is merely exemplary: the embodiments are in fact largely “transparent” to the leadframe configuration.
It is noted that various leadframe suppliers have the capability of supplying leadframe material 12 that has been already subjected to NEAP processing and thus already include a NEAP layer 1200 as supplied from the supplier.
According to one embodiment, a plating process, comprising at least one silver plating can be applied to the leadframe prior to the NEAP treatment. Alternatively, a silver-plated leadframe (with no Cu layer underneath) can be used, as provided by a leadframe supplier.
This is in order to re-expose the underlying metal (e.g., copper, silver or various alloys) of the leadframe 12.
As illustrated in the cross-sectional view of
As illustrated in the cross-sectional view of
As likewise visible in the cross-sectional view of
In that way, the solder material 120 will (marginally) overflow with respect to the substrate 12: that is, the solder material 120 will have an upper or external surface somewhat protruding or emerging with respect to the surface of the adjacent regions of the leadframe 12.
It will be otherwise appreciated that the “unablated” NEAP layer forms (e.g., around the die pads 12A, 12A′) a sort of peripheral containment rim (or “dyke”) that effectively counters undesired spilling (splashing) of the solder material 120—in a flowable state—sidewise of the die pads 12A and 12A′ that have been re-exposed via laser ablation.
The sequence of
As represented in
That is:
As exemplified in
Once the lead or chip 16 flipped onto the leadframe 12 (on top of solder material 120), the masses of solder material 120 dispensed at the die pads 12A and 12A′ will be sandwiched, respectively:
By way of example, letting the die pads 12A and 12A′ and the attachment regions 16A, 16A′ have complementary geometries can be simply obtained by ablating the die pads 12A and 12A′ at positions and with shapes that are mirror-images of the positions and shapes of attachment regions 16A, 16A′ (with respect to the notional tilting axis XT).
In the examples illustrated herein, the first die area 16A extends over a major portion (e.g., 80%-90%) of the die attachment surface of the semiconductor die 16. This facilitates effective removal of heat produced by the chip 12 during operation.
The second die area (16A′) extends over a minor portion (20%-10%) of the die attachment surface of the at least one semiconductor die 16, optionally at a corner of the die or chip 16.
Once the lead or chip 16 flipped onto the leadframe 12 (with the solder paste 120 solidified, e.g., via thermal or UV curing) the resulting assembly can be submitted to reflow and other processing steps (e.g., molding the encapsulation compound 18, singulation, and so on) to complete the device 10.
The sequence of
As illustrated, the semiconductor die 16 has an attachment surface comprising at least one first die area 16A and one second die area 16A′.
These areas 16A, and 16A′ are wettable by electrically conductive solder material 120, with the first die area 16A and second die area 16A′ otherwise mutually electrically isolated.
Selectively removing (e.g., via laser ablation as exemplified by the reference LA in
In that way, the NEAP-ablated areas 12A, 12A′ can be used as a solder mask for solder material (e.g., hybrid glue) 120 to define die-to-leadframe connection areas for a flip-chip, e.g., power die. The NEAP-ablated areas 12A, 12A′ match the die wettable areas 16, 16A′ when the die 16 is flipped.
This provides (at least) two electrical connections to the die 16.
For instance, this may be a field-effect power transistor, with drain and gate terminals connected to the die pad 12A, 12A′ and the source connection provided, e.g., via a clip.
As visible, e.g., at the bottom of
A device package and manufacturing method are thus provided where selective removal of a NEAP layer at two mutually electrically isolated die pad regions (12A and 12A′) provides two “mask” reasons for dispensing die attach material such as the paste 120 at the solder mask regions 12A, 12A′ thus facilitating flip-chip mounting of a die 16 with wettable regions 16 and 16A′ matching the regions 12A, 12A′ laser-ablated in the NEAP layer 1200.
As exemplified, laser ablation can be customized in a variety of ways ranging from partial laser ablation (e.g., stripe-like, via laser beam raster scan as exemplified in
The various ways for selective laser ablation of thin NEAP oxide layer 1200 illustrated herein facilitate re-exposing selected pad surfaces (e.g., 12A, 12A′) that can precisely match the “wettable” connection areas 16A, 16A′ in the chip or die 16.
Selective laser ablation of the NEAP layer facilitates letting the geometry of the ablated areas (e.g., 12A, 12A′) fully and accurately match the geometry of the “wettable” areas 16A, 16A′ of the semiconductor ship or die.
Also, areas exposed in the leadframe material (e.g., metals) are compatible with solder paste such as the solder paste 120.
Additionally, the ablated areas 12A, 12A′ being somewhat “engraved” effectively counters undesired solder paste “splashing” in response to “flip-chip” mounting of the chip 16, and/or during reflow.
Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example without departing from the scope of protection.
A method, may be summarized as including attaching at least one semiconductor die (16) onto a die mounting surface of a substrate (12) having a non-etched adhesion promoter, NEAP layer (1200) over the die mounting surface, wherein the at least one semiconductor die (16) has an attachment surface including at least one first die area (16A) and one second die area (16A′), the first (16A) and second (16A′) die areas wettable by electrically conductive solder material (120), the first (16A) and second (16A′) die areas mutually electrically isolated, wherein the method includes selectively removing (LA) the NEAP layer (1200) from at least one first substrate area (12A) and one second substrate area (12A′) of the die mounting surface of the substrate (12), wherein the first substrate area (12A) and the second substrate area (12A′) of the substrate (12) have complementary shapes with respect to the first (16A) die area and the second (16A′) die area of the semiconductor die (16), respectively, dispensing electrically conductive solder material (120) on the first substrate area (12A) and the second substrate area (12A′) of the substrate (12), and flipping the at least one semiconductor die (16) onto the die (16) mounting substrate (12) with the first die area (16A) and the second die area (16A′) aligned with the first substrate area (12A) and the second substrate area (12A′) of the substrate (12) having the solder material (120) dispensed thereon, wherein the electrically conductive solder material (120) provides electrical coupling of the first die area (16A) and the first substrate area (12A), and the second die area (16A′) and the second substrate area (12A′).
Selectively removing (LA) the NEAP layer (1200) may include laser ablating (LA) the NEAP layer (1200) at said at least one first substrate area (12A) and one second substrate area (12A′) of the die mounting surface of the substrate (12).
Selectively removing (LA) the NEAP layer (1200) may include removing the NEAP layer (1200) over the entirety of said at least one first substrate area (12A) and one second substrate area (12A′) of the die mounting surface of the substrate (12), or removing the NEAP layer (1200) over a portion of said at least one first substrate area (12A) and one second substrate area (12A′) of the die mounting surface of the substrate (12).
Selectively removing (LA) the NEAP layer (1200) may include removing the NEAP layer (1200) over a portion of said at least one first substrate area (12A) and one second substrate area (12A′) of the die mounting surface of the substrate (12), wherein said removing follows a striped pattern.
Selectively removing (LA) the NEAP layer (1200) may include ablating (LA) material of the substrate (12) underlying the NEAP layer (1200) at said at least one first substrate area (12A) and one second substrate area (12A′) of the die mounting surface of the substrate (12).
The method may include dispensing electrically conductive solder material (120) by overfilling said at least one first substrate area (12A) and one second substrate area (12A′) of the die mounting surface of the substrate (12).
A device (10), may be summarized as including at least one semiconductor die (16) attached onto a die mounting surface of a substrate (12) having a non-etched adhesion promoter, NEAP layer (1200) over the die mounting surface, wherein the at least one semiconductor die (16) has an attachment surface including at least one first die area (16A) and one second die area (16A′), the first (16A) and second (16A′) die areas having electrically conductive solder material (120) thereon, the first (16A) and second (16A′) die areas mutually electrically isolated, wherein at least one first substrate area (12A) and one second substrate area (12A′) of the die mounting surface of the substrate (12) have the NEAP layer (1200) removed therefrom, wherein the first substrate area (12A) and the second substrate area (12A′) of the substrate (12) have complementary shapes with respect to the first (16A) die area and the second (16A′) die area of the semiconductor die (16), respectively, the at least one semiconductor die (16) flip-mounted onto the die (16) mounting substrate (12) with the first die area (16A) and the second die area (16A′) aligned with the first substrate area (12A) and the second substrate area (12A′) of the substrate (12) having the solder material (120) dispensed thereon, wherein the electrically conductive solder material (120) provides electrical coupling of the first die area (16A) and the first substrate area (12A), and the second die area (16A′) and the second substrate area (12A′).
The at least one first substrate area (12A) and one second substrate area (12A′) of the die mounting surface of the substrate (12) may have the NEAP layer (1200) removed therefrom over the entirety of said at least one first substrate area (12A) and one second substrate area (12A′), or over a, preferably stripe-like, portion of said at least one first substrate area (12A) and one second substrate area (12A′).
Material of the substrate (12) may be ablated (LA) from at said at least one first substrate area (12A) and one second substrate area (12A′) of the die mounting surface of the substrate (12).
The at least one first die area (16A) may extend over a major portion of the die attachment surface of the at least one semiconductor die (16) and the at least one second die area (16A′) may extend over a minor portion of the die attachment surface of the at least one semiconductor die (16), preferably at a corner thereof.
The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.
Number | Date | Country | Kind |
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102021000031007 | Dec 2021 | IT | national |