Patent Grant
10388456
This patent application is a national phase filing under section 371 of PCT/EP2016/061701, filed May 24, 2016, which claims the priority of Japanese patent application 2015-107731, filed May 27, 2015 and Japanese patent application 2015-256458, filed Dec. 28, 2015, each of which is incorporated herein by reference in its entirety.
The present invention relates to a dielectric composition, a dielectric element, an electronic component and a laminated electronic component which are advantageously used for medium- and high-voltage applications with a high rated voltage, and are also advantageously used under a high-temperature environment.
Laminated electronic components such as laminated ceramic capacitors are widely used as compact, large-capacity and highly reliable electronic components. As devices have become more compact and higher performing in recent years, there has been an increasingly strong demand for further miniaturization, increased capacity, lower cost and greater reliability in electronic components and especially in laminated electronic components such as laminated ceramic capacitors.
Laminated ceramic capacitors are normally produced by laminating a paste for internal electrode layers and a paste for dielectric layers using a sheet process or a printing process etc., and then simultaneously baking the internal electrode layers and the dielectric layers in the laminated body.
A barium titanate-based dielectric composition comprising barium titanate as the main component which has a high dielectric constant is conventionally widely known as a dielectric composition which is used for the dielectric layer. There is a problem with a barium titanate-based dielectric composition, however, in that the insulation resistance thereof deteriorates markedly at high temperatures of 100° C. or above.
Furthermore, a capacitor may be used with a DC voltage superimposed on an AC voltage. The DC bias characteristics are important when a capacitor is used with a DC voltage superimposed on an AC voltage. The DC bias characteristics express a change in the dielectric constant which is dependent on application of a DC voltage. The DC bias characteristics are higher the smaller the change in the dielectric constant with respect to application of a DC voltage. It is known that a capacitor employing a conventional barium titanate-based dielectric composition has low DC bias characteristics, and the greater the DC voltage, the lower the dielectric constant.
In addition, when the dielectric layer is made thinner in order to make the laminated ceramic capacitor more compact and to increase the capacity thereof, the electric field applied to the dielectric layer becomes more intense when a DC voltage is applied, so there is a further drop in the DC bias characteristics.
Furthermore, Pd or Pd alloy is generally used as the conductive material of the internal electrode layers in the laminated ceramic capacitor. However, Pd is costly so in recent years use has also been made of relatively inexpensive base metals such as Ni and Cu.
When a base metal such as Ni or Cu is used as the conductive material of the internal electrode layer, the internal electrode layer oxidizes when baking is carried out under the atmosphere. This means that it is necessary for the dielectric layer and the internal electrode layer to be simultaneously baked under a reducing atmosphere. When baking is carried out under a reducing atmosphere, however, the dielectric layer is reduced and there is a drop in insulation resistance.
In view of this, there is a need for a non-reducing dielectric composition which has excellent DC bias characteristics and has high insulation resistance at high temperatures.
As a means for resolving this situation, for example, Japanese Patent JP 3334607 describes a laminated ceramic capacitor which has good DC bias characteristics and high insulation resistance at high temperatures, and a barium titanate-based dielectric composition which is suitable for the laminated ceramic capacitor.
However, although the dielectric constant of the dielectric composition in Patent Japanese Patent JP 3334607 is relatively high at around 900-950 when a DC electric field of 5 V/μm is applied, the dielectric constant decreases when an even higher DC electric field is applied, so the DC bias characteristics are inadequate to cope with the thinning of the layers which accompanies a reduction in size and increased capacity.
Furthermore, the dielectric composition in Japanese Patent JP 3334607 has relatively high insulation resistance at a high temperature of 150° C. However, this is still inadequate in comparison with the magnitude of insulation resistance required in recent years.
Embodiments provide a dielectric composition which has excellent DC bias characteristics and high insulation resistance at high temperatures. Further embodiments provide a dielectric element, an electronic component and a laminated electronic component.
Various embodiments provide a dielectric composition having a perovskite compound in which the main component comprises Bi, Na, Sr, Ln and Ti, and the Ln is at least one type of rare earth element, characterized in that the mean crystal grain size is between 0.1 μm and 1 μm.
A dielectric composition having this constitution can achieve excellent DC bias characteristics and high insulation resistance at high temperatures.
In various further embodiments, the dielectric composition according to the present invention has a main component represented by (BiaNabSrcLnd)TiO3, where a, b, c and d satisfy the following, respectively: 0<a<0.50, 0<b<0.50, 0<c≤0.80, 0<d≤0.20 and 0.90≤a+b+c+d≤1.05.
The dielectric composition according to embodiments of the present invention preferably contains between 5 molar parts and 18 molar parts of at least one from the group consisting of Li and K as an auxiliary component, with respect to 100 molar parts of Ti contained in the main component.
The dielectric composition according to embodiments of the present invention preferably contains between 0.2 molar parts and 1 molar part of at least one from the group consisting of Cu, Mn, Zn, Mg and Co as an auxiliary component, with respect to 100 molar parts of Ti contained in the main component. As a result, the sintering properties are improved and it is possible to achieve high insulation resistance.
A dielectric element according to embodiments of the present invention comprises the abovementioned dielectric composition.
The dielectric element according to embodiments of the present invention comprises the abovementioned dielectric composition and can therefore be made more compact and higher performing.
An electronic component according to embodiments of the present invention is provided with a dielectric layer comprising the abovementioned dielectric composition.
A laminated electronic component according to embodiments of the present invention has a laminated portion which is formed by alternately laminating an internal electrode layer and a dielectric layer comprising the abovementioned dielectric composition.
The electronic component and the laminated electronic component according to embodiments the present invention are provided with a dielectric layer comprising the abovementioned dielectric composition and can therefore be made more compact and higher performing.
FIGURE is a schematic diagram of a laminated ceramic capacitor according to a mode of embodiment of the present invention.
FIGURE shows a laminated ceramic capacitor 1 according to a mode of embodiment of the present invention comprising a capacitor element main body 10 having a structure in which dielectric layers 2 and internal electrode layers 3 are alternately stacked. The internal electrode layers 3 are stacked in such a way that the end surfaces thereof are alternately exposed at the two opposing ends of the capacitor element main body 10. A pair of external electrodes 4 is formed at both ends of the capacitor element main body 10, and are connected to the exposed end surfaces of the alternately-arranged internal electrode layers 3 to form a capacitor circuit.
Is shown in
The capacitor element main body 10 normally has a cuboid shape, but is not particularly limited to this. Furthermore, there is no particular limitation as to the dimensions of the capacitor element main body. In general, the dimensions are normally (long side)×(short side)×(height)=(0.6 mm-70.0 mm)×(0.3 mm-6.4 mm)×(0.3 mm-2.5 mm).
The dielectric layers 2 of the laminated ceramic capacitor 1 according to a mode of embodiment of the present invention comprise a sintered compact formed by crystal grains of a dielectric composition having, as the main component, a perovskite compound including Bi, Na, Sr, Ln (where Ln is a rare earth element) and Ti.
The dielectric composition has a composition according to the following general formula (1), where a, b, c and d satisfy the following, respectively: 0<a<0.50, 0<b<0.50, 0<c≤0.80, 0<d≤0.20 and 0.90≤a+b+c+d≤1.05.
(BiaNabSrcLnd)TiO3 (1)
The reason that the dielectric composition according to the present invention includes Ln (rare earth element) is to improve the dielectric constant and the insulation resistivity of the dielectric composition when a DC bias is applied.
It should be noted that a, b, c and d each represent the ratio of the number of atoms of Bi, Na, Sr and Ln when the number of atoms of Ti is 1.
The reason that a, b, c and d are preferably within the abovementioned ranges in the laminated ceramic capacitor is because a high dielectric constant is exhibited when a DC bias is applied and high insulation resistance is exhibited at high temperatures. Furthermore, it is also because this facilitates suppressing grain growth when the dielectric particles (to be described later) are baked.
It should be noted that the phrase “when a DC bias is applied” means a case in which an AC electric field of between 0.02 V/μm (preferably 0.2 V/μm or greater, more preferably 0.5 V/μm or greater) and 5 V/μm and a DC electric field of between 1 V/μm and 8 V/μm superimposed thereon are applied to the laminated ceramic capacitor. According to the present invention, it is important that the dielectric constant be high even when a DC electric field, in particular of greater than 5 V/μm and no greater than 8 V/μm, is applied.
Furthermore, when a, b, c and d satisfy the following, respectively: 0.20≤a≤0.40, 0.20≤b≤0.40, 0.15≤c≤0.50, 0.90≤d≤0.15 and 0.90≤a+b+c+d≤1.01, it is possible to achieve a high dielectric constant when a DC bias is applied and it is possible to achieve high insulation resistance at high temperatures.
The crystal grains (referred to below as “dielectric particles”) forming the dielectric layers 2 will be described next.
The dielectric particles form the abovementioned dielectric layers 2 and a feature of the present invention lies in the fact that the mean crystal grain size of the dielectric particles is between 0.10 μm and 1.0 μm. By setting the mean crystal grain size of the dielectric particles at between 0.10 μm and 1.0 μm, the laminated ceramic capacitor 1 which is ultimately produced has excellent DC bias characteristics while also having high insulation resistance even at a high temperature of 150° C. Furthermore, the mean crystal grain size of the dielectric particles contained in the dielectric composition is preferably between 0.10 μm and 0.50 μm. When the mean crystal grain size of the dielectric particles is between 0.10 μm and 0.50 μm, it is possible to achieve a high dielectric constant when a DC bias is applied and to achieve high insulation resistance at high temperatures. The effect of the present invention is particularly pronounced when a, b, c and d satisfy the following, respectively: 0.20≤a≤0.40, 0.20≤b≤0.40, 0.15≤c≤0.50, 0.01≤d≤0.15 and 0.90≤a+b+c+d≤1.01 and at the same time the mean crystal grain size of the dielectric particles is between 0.10 μm and 0.50 μm.
The mean crystal grain size of the dielectric particles can be adjusted by a conventional method in this technical field. There is no particular limitation as to the method of adjusting the mean crystal grain size. For example, the mean crystal grain size may be adjusted by varying the particle size of the starting material of the dielectric particles or the baking conditions (baking time, baking temperature etc.).
If the mean crystal grain size of the dielectric particles is less than 0.10 μm, the dielectric constant is markedly reduced and becomes 800 or less when a DC bias of 8 V/μm is applied. Furthermore, if the mean crystal grain size of the dielectric particles exceeds 1.0 μm, there is a deterioration in the insulation resistance at high temperatures and the insulation resistivity at 150° C. becomes less than 1012 Ω·cm.
The mean crystal grain size of the dielectric particles according to the present invention is determined by the chord method. The method for determining the mean crystal grain size by means of the chord method will be described below. It should be noted that in the following explanation, the mean crystal grain size may be referred to as D.
First of all, an image is captured by a microscope on a measurement surface for measuring the mean crystal grain size D. A straight line is drawn anywhere in the image and the length of the straight line within the image is taken as L. The number N of intersections between the straight line and grain boundaries is measured, and L is divided by N to obtain the mean length between grain boundaries. If the dielectric particles are assumed to be large spheres of equal size, a value corresponding to the abovementioned mean length multiplied by 1.5 is taken as the mean crystal grain size D.
It should be noted that there is no particular limitation as to the magnification of the image, but an image is preferably captured at a magnification of 5000 to 50 000 times. Furthermore, a plurality of straight lines are drawn in a plurality of images in such a way that the number N of intersections is at least 100 and preferably at least 300. There is no particular limitation as to the number of lines.
In the present application, the dielectric particles are assumed to be large spheres of equal size for measurement of the mean crystal grain size D. That is to say, in the present application, the mean crystal grain size D is calculated by means of formula (2).
D=1.5×(L/N) (2)
Furthermore, the dielectric composition according to the present invention may also contain lithium oxide (Li2O) and/or potassium oxide (K2O) as auxiliary components. In the following description, these auxiliary components may be referred to as auxiliary component A. During baking, the auxiliary component A has the effect of promoting sintering at low temperature and has the effect of suppressing grain growth in the dielectric particles. The content of the auxiliary component A is preferably at least 5 molar parts when the content of the main component Ti is 100 molar parts, in order to adequately achieve the abovementioned effects. Furthermore, in order to maintain high insulation resistance, the content of the auxiliary component A is preferably no greater than 18 molar parts. It should be noted that the content of the auxiliary component A is the total of the content of lithium oxide as Li equivalent and the content of potassium oxide as K equivalent.
Furthermore, the dielectric composition according to the present invention may contain, separately from the auxiliary component A, one or more oxides selected from the group consisting of copper oxide (CuO), manganese oxide (MnO2), zinc oxide (ZnO), magnesium oxide (MgO) and cobalt oxide (Co3O4). In the following description, these auxiliary components may also be referred to as auxiliary component M. The auxiliary component M demonstrates the effect of promoting sintering and the effect of suppressing a drop in insulation resistance during baking under a reducing atmosphere. That is to say, the auxiliary component M has the effect of bringing the dielectric composition close to non-reductive. The content of the auxiliary component M is preferably between 0.2 molar parts and 1.5 molar parts when the content of the main component Ti is 100 molar parts, and more preferably between 0.2 molar parts and 0.5 molar parts, in order to adequately demonstrate the abovementioned effects. It should be noted that the content of the auxiliary component M is the total of the content of copper oxide as Cu equivalent, the content of manganese oxide as Mn equivalent, the content of zinc oxide as Zn equivalent, the content of magnesium oxide as Mg equivalent and the content of cobalt oxide as Co equivalent.
Various conditions such as the number of laminations and the thickness etc. of the dielectric layers 2 should be determined as appropriate according to the aim or the application. The thickness of the dielectric layers 2 is normally no greater than 30 μm and is preferably no greater than 10 μm from the point of view of compactness.
The laminated ceramic capacitor 1 according to a mode of embodiment of the present invention can increase the capacity and can properly maintain the insulation resistance at high temperatures when the thickness of the dielectric layers 2 is reduced to no greater than 10 μm. It should be noted that there is no particular restriction as to the lower limit for the thickness of the dielectric layers 2, but it is preferably no less than 1 μm in order to facilitate properly maintaining the insulation resistance at high temperatures. Furthermore, the number of laminations in the dielectric layers 2 is normally around 50-1000.
The internal electrode layers 3 are provided alternately with the dielectric layers 2 and are stacked in such a way that the end surfaces thereof are alternately exposed at the two opposing ends of the capacitor element main body 10. Furthermore, the pair of external electrodes 4 are formed at both ends of the capacitor element main body 10, and are connected to the exposed end surfaces of the alternately-arranged internal electrode layers 3 to form the laminated ceramic capacitor 1.
The internal electrode layers 3 are formed from a conductive material which is a noble metal or a base metal that acts essentially as an electrode. Specifically, the noble metal or base metal conductive material comprises any of Ag, Ag alloy, Cu or Cu alloy. There is no particular limitation as to metals other than Ag or Cu which are contained in the Ag alloy or Cu alloy, but one or more metals selected from Ni, Mn, Cr, Co, Al and W are preferred. Furthermore, if Ag alloy is used, the Ag content is preferably at least 95 wt % when the Ag alloy is taken as 100 wt %. If Cu alloy is used, the Cu content is preferably at least 95 wt % when the Cu alloy is taken as 100 wt %.
Various trace components such as P, C, Nb, Fe, Cl, B, Li, Na, K, F and S may also be included in the conductive material in a total amount of no greater than 0.1%.
Various conditions such as the number of laminations and the thickness etc. of the internal electrode layers 3 should be determined as appropriate in accordance with the aim or application. The thickness of the internal electrode layers 3 is preferably around 0.1 μm-4.0 μm and more preferably 0.2 μm-3.0 μm.
The external electrodes 4 are electrodes which conduct with the internal electrode layers 3 disposed alternately inside the laminated dielectric element main body 10, and are formed as a pair at both ends of the laminated dielectric element main body 10. There is no particular limitation as to the metal forming the external electrodes 4. One type of metal selected from Ni, Pd, Ag, Au, Cu, Pt, Rh, Ru and Ir etc. may be used alone, or an alloy of two or more metals may be used. Cu, Cu alloy, Ni, Ni alloy, Ag, Ag—Pd alloy, or In—Ga alloy or the like is normally used for the external electrodes 4.
The thickness of the external electrodes 4 should be determined as appropriate in accordance with the application etc. The thickness of the external electrodes 4 is preferably around 10-200 VIM.
(Method for Producing the Laminated Ceramic Capacitor)
There is no particular limitation as to the method for producing the laminated ceramic capacitor according to the present invention. For example, it may be produced in the same way as a conventional laminated ceramic capacitor, by preparing a green chip using a normal sheet method or printing method employing a paste, baking the green chip and then printing or transcribing the external electrodes and then baking. The method for producing the laminated ceramic capacitor will be described in specific terms below.
There is no particular limitation as to the type of paste used for the dielectric ceramic layers. For example, the paste may be an organic paint comprising a mixture of a dielectric starting material and an organic vehicle, or it may be an aqueous paint comprising a mixture of a dielectric starting material and an aqueous vehicle.
For the dielectric starting material, it is possible to use a metal contained in the main component and the auxiliary component, for example, an oxide of a metal selected from the group consisting of Bi, Na, Sr, Ln, Ti, Li, K, Cu, Mn, Zn, Mg and Co, or a mixture thereof, or a composite oxide may be used. In addition, the dielectric starting material may be appropriately selected from various types of compounds which form the abovementioned oxides or composite oxides as a result of baking, e.g., carbonates, oxalates, nitrates, hydroxides and organometallic compounds etc. and these may be mixed for use. The content of each compound in the dielectric starting material should be determined in such a way that the abovementioned dielectric composition is formed after baking. A powder having a mean particle size of the order of 0.1-3 μm is normally used as the dielectric starting material. The dielectric starting material is preferably a powder having a mean particle size of 0.1-1 μm. Furthermore, the mean particle size of the dielectric starting material may be adjusted by appropriately varying the time for which the starting material is mixed.
When the paste for the dielectric layers is an organic paint, the dielectric starting material and an organic vehicle in which a binder or the like is dissolved in an organic solvent should be mixed. There is no particular limitation as to the binder which is used in the organic vehicle, and it should be appropriately selected from various normal binders such as ethyl cellulose and polyvinyl butyral. Furthermore, there is no particular limitation as to the organic solvent which is used in the organic vehicle, and it should be appropriately selected from various types of organic solvents such as terpineol, butyl carbitol, acetone and toluene, in accordance with the method which is used, namely the printing method or sheet method etc.
Furthermore, when the paste for the dielectric layers is an aqueous paint, the dielectric starting material and an aqueous vehicle in which a water-soluble binder and a dispersant etc. are dissolved in water should be mixed. There is no particular limitation as to the water-soluble binder which is used in the aqueous vehicle, and examples of binders which may be used include polyvinyl alcohol, cellulose and water-soluble acrylic resin.
The paste for the internal electrode layers is prepared by mixing a conductive material comprising various types of the abovementioned metals or alloys, or various types of compounds which form the conductive material after baking, organometallic compounds, resinates, and the like, with the abovementioned organic vehicle or aqueous vehicle. The paste for the external electrodes may be prepared in the same way as the paste for the internal electrodes.
When an organic vehicle is used to prepare the abovementioned pastes, there is no particular limitation as to the content of said organic vehicle. For example, the binder may be present in an amount of the order of 1-5 wt % and the organic solvent may be present in an amount of the order of 10-50 wt %. Furthermore, the pastes may contain additives selected from various types of dispersants, plasticizers, dielectrics, and insulators etc., as required. The total content of these additives is preferably no greater than 10 wt %.
When a printing method is used, the paste for the dielectric layers and the paste for the internal electrode layers are printed in layers on a substrate made of polyethylene terephthalate (PET) or the like and cut to a predetermined shape, after which they are peeled from the substrate to form a green chip. Furthermore, when the sheet method is used, a green sheet is formed using the paste for the dielectric layers, and the paste for the internal electrode layers is printed on the green sheet, after which the green sheets are stacked to form a green chip.
Before the green chip is baked, a debinding treatment is performed. There is no particular limitation as to the conditions of the debinding treatment and it should be carried out under normal conditions.
When a single base metal or alloy comprising base metals, such as Cu or Cu alloy, is used as the conductive material for the internal electrode layers, the debinding treatment is preferably carried out under a reducing atmosphere. There is no particular limitation as to the type of reducing atmosphere, and it is possible to use humidified N2 gas or a mixed gas comprising humidified N2 and H2, for example.
There is no particular limitation as to the temperature increase rate, holding rate or temperature holding time in the debinding treatment. The temperature increase rate is preferably 0.1-100° C./hr, and more preferably 1-10° C./hr. The holding temperature is preferably 200-500° C. and more preferably 300-450° C. The temperature holding time is preferably 1-48 hours and more preferably 2-24 hours. The organic component of the binder component etc. is preferably removed by means of the debinding treatment down to around 300 ppm, and more preferably it is removed down to around 200 ppm.
The atmosphere under which the green chip is baked to obtain the capacitor element main body should be appropriately selected according to the type of conductive material in the paste for the internal electrode layers.
When a single base metal or alloy comprising base metals, such as Cu or Cu alloy, is used as the conductive material in the paste for the internal electrode layers, the oxygen partial pressure in the baking atmosphere is preferably between 10−6 and 10−8 atm. By setting the oxygen partial pressure at 10−8 atm or greater, it is possible to suppress a drop in insulation resistance and degradation of the components forming the dielectric layers. Furthermore, by setting the oxygen partial pressure at 10−6 atm or less, it is possible to suppress oxidation of the internal electrode layers.
Furthermore, the holding temperature during baking is preferably 900-1100° C. and more preferably 950-1050° C. By setting the holding temperature at 900° C. or greater, this makes densification more likely to progress adequately due to baking. Furthermore, by setting the holding temperature at 1100° C. or less, this facilitates suppressing diffusion of the various materials forming the internal electrode layers and abnormal sintering of the internal electrode layers. By suppressing abnormal sintering of the internal electrode layers, this facilitates preventing breakage of the internal electrodes. By suppressing diffusion of the various materials forming the internal electrode layers, this facilitates preventing deterioration of the DC bias characteristics.
By appropriately setting the holding temperature during baking within the abovementioned temperature ranges, this facilitates obtaining the required crystal grain size. Furthermore, there is no particular limitation as to the baking atmosphere. The baking atmosphere is preferably a reducing atmosphere in order to suppress oxidation of the internal electrode layers. There is no particular restriction as to the gas atmosphere. A mixed gas comprising N2 and H2 is preferably humidified for use as the gas atmosphere, for example. Furthermore, there is no particular limitation as to the baking time.
When the laminated ceramic capacitor according to this mode of embodiment is produced, annealing (re-oxidation) may be carried out. The annealing should be carried out under normal conditions. There is no particular limitation as to the annealing atmosphere. It is possible to use humidified N2 gas or a mixed gas comprising humidified N2 and H2, for example.
In order to humidify the N2 gas or mixed gas comprising N2 and H2, in the abovementioned debinding, baking and annealing, a wetter or the like should be used, for example. In this case, the water temperature is preferably around 20-90° C.
The debinding, baking and annealing may be carried out consecutively or independently. When they are carried out consecutively, the debinding is preferably carried out, after which the atmosphere is changed without cooling, and then the temperature is raised to the baking holding temperature and baking is carried out. On the other hand, when they are carried out independently, during the baking, the temperature is preferably raised under an N2 gas atmosphere to the holding temperature for the debinding treatment, after which the atmosphere is changed and then a further temperature increase is continued, and following the baking, cooling is preferably carried out to the holding temperature for the debinding treatment, after which the atmosphere is once again changed to an N2 gas atmosphere and further cooling is continued. It should be noted that the abovementioned N2 gas may or may not be humidified.
The end surfaces of the capacitor element main body obtained in this way are polished by means of barrel polishing or sandblasting, for example, the paste for the external electrodes is printed or transcribed thereon, baking is carried out and the external electrodes are formed. The paste for the external electrodes is preferably baked under a mixed gas comprising humidified N2 and H2 at 600-800° C. for a time of around 10 minutes to 1 hour, for example. A coating layer is formed by means of plating or the like on the external electrode surface, as required.
There is no particular limitation as to the application of the laminated ceramic capacitor according to a mode of embodiment of the present invention produced in this way. For example, it may be mounted on a printed circuit board or the like by means of solder or the like, or it may be used in various types of electronic devices, e.g., a mobile telephone or a digital television etc.
The laminated ceramic capacitor and the method for producing same in accordance with a mode of embodiment of the present invention have been described above, but the present invention is not limited in any way to this mode of embodiment and various modes may of course be implemented with a scope that does not depart from the essential point of the present invention.
The present invention will be described in further detail below with the aid of exemplary embodiments and comparative examples. However the present invention is not limited to the following exemplary embodiments.
A starting material powder for the main component and a starting material powder for the auxiliary component indicated below were first of all prepared as starting materials for producing the dielectric ceramic layers. It should be noted that the mean particle size of the starting material powders prepared was 0.1-1 μm in all cases.
The starting material powders of the main components (Bi2O3, Na2CO3, SrCO3, Ln2O3 and TiO2) were weighed out in such a way that the dielectric compositions after baking satisfied the compositions in table 1 to table 3, then they were wet-mixed by means of a ball mill, after which the resulting mixtures were calcined for 2 hours at 750° C.-850° C. under the air, and main component powders were prepared. Ln is one element selected from among La, Nd, Sm, Gd, Dy and Yb. In table 1 to table 3, a, b, c and d denote numerical values of a, b, c and d in the following formula (1).
(BiaNabSrcLnd)TiO3 (1)
Starting material powders of the auxiliary components (Li2CO3, K2CO3, CuO, MnCO3, ZnO, MgO and Co3O4) were then prepared. The starting material powders were weighed out in such a way that the compositions after baking achieve the molar parts shown in table 1 to table 3 with respect to 100 molar parts in terms of Ti content in the main component, they were then mixed with the main component powders and mixed powders were obtained.
An organic solvent and an organic vehicle were then added to the mixed powders and the materials were wet-mixed using a ball mill to prepare pastes for the dielectric layers. At the same time, Ag powder, Ag—Pd alloy powder or Cu powder was mixed with the organic vehicle as a conductive material powder, and Ag, Ag—Pd alloy or Cu pastes for various types of internal electrode layers were prepared. The pastes for the dielectric layers were then moulded into sheets by means of a sheet-moulding method, and ceramic green sheets having a thickness of 10 μm were obtained.
The paste for the internal electrode layers was coated on the ceramic green sheets by means of screen printing to print the internal electrode layers. The ceramic green sheets on which the internal electrode layers had been printed were laminated, after which they were cut into block shapes having dimensions of 4.5×4.3×1.0 mm, whereby laminated green chips were prepared. The thickness of the internal electrode layers was 2 μm and the number of laminations was 10. The laminated green chips were subjected to debinding at 300° C.-500° C. and the organic component was removed down to around 300 ppm. After the debinding, the green chips were baked under the atmosphere or under a reducing atmosphere at 850° C.-1100° C. The baking time was varied as appropriate. When the baking was carried out under a reducing atmosphere, the gas atmosphere which was used was a mixed gas comprising humidified N2 and H2. After the baking, the exposed surfaces of the internal electrodes were polished, a paste for the external electrodes having Ag or Cu as a conductive material was applied thereto, and laminated ceramic capacitors were obtained.
Moreover, it was confirmed that the compositions were the same as those shown in table 1 to table 3 by dissolving the dielectric layers of the baked laminated green chips in a solvent and performing ICP optical emission spectroscopy.
The mean crystal grain size of the dielectric particles forming the dielectric layers was also measured. The chord method was used to measure the mean crystal grain size of the dialectic particles. A photograph of the dielectric layers was captured at a magnification of 10 000-20 000 times using an electron microscope (Hitachi High-Tech, S-4700). A straight line was drawn on a plurality of photographs in such a way that the number N of intersections between the straight line and the grain boundaries was about 300, and the mean crystal grain size D was calculated.
The capacitance when a DC bias of 8 V/μm was applied at room temperature of 25° C. with an AC voltage of 0.1 V/μm superimposed, and the insulation resistance at 150° C. were further measured for each of the laminated ceramic capacitors prepared. The dielectric constant and insulation resistivity were further calculated from the capacitance, insulation resistance, electrode surface area and distance between dielectric layers.
A DC high-voltage power source (Glassman High Voltage, WX10P90) was connected to a digital LCR meter (Hewlett-Packard, 4284A), and the capacitance was measured by said digital LCR meter at room temperature of 25° C. while a DC bias of 8 V/μm was applied to each of the laminated ceramic capacitors.
The insulation resistance was obtained by using a DC high-voltage power source (Glassman High Voltage, WX10P90) to apply a voltage corresponding to 8 V/μm to each of the laminated ceramic capacitors and measuring the current value inside a thermostatic tank at 150° C.
The dielectric constant when a DC bias of 8 V/μm was applied at room temperature of 25° C., and the insulation resistivity at 150° C. for each of the exemplary embodiments and comparative examples are shown in table 1 to table 3. A dielectric constant of 800 or greater when a DC bias of 8 V/μm was applied was deemed to be good. Furthermore, insulation resistivity of 1012 Ω·cm or greater was deemed to be good.
As is clear from the results of table 1 to table 3, it was confirmed that when the main component comprised Bi, Na, Sr, Ln and Ti and the mean crystal grain size of the dielectric particles was in the range of 0.1 μm-1 μm (Exemplary Embodiments 1-102), the insulation resistivity at 150° C. was 1012 Ω·cm or greater and the dielectric constant when a DC bias of 8 V/μm was applied was 800 or greater.
On the other hand, the results showed that in Comparative Examples 1 and 2 in which the mean crystal grain size of the dielectric particles exceeded 1 μm and the main component did not contain the rare earth element Ln, the dielectric constant and the insulation resistivity were both excessively low. The results further showed that in Comparative Example 3 in which the main component did not contain the rare earth element Ln, the dielectric constant and electrical resistivity were both excessively low, even though the mean crystal grain size of the dielectric particles was in the range of 0.1 μm-1 μm.
The results further showed that in Comparative Example 4 in which the mean crystal grain size of the dielectric particles was 1.23 μm, the insulation resistivity at 150° C. was excessively low at 7×1011 Ω·cm. The results also showed that in Comparative Example 5 in which the mean crystal grain size of the dielectric particles was 0.09 μm, the dielectric constant when a DC bias was applied was excessively low at 650.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2015-107731 | May 2015 | JP | national |
| 2015-256458 | Dec 2015 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/EP2016/061701 | 5/24/2016 | WO | 00 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2016/189003 | 12/1/2016 | WO | A |
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