A typical solid-state memory device has multiple memory cells coupled to bit lines that facilitate the extraction of data stored in memory cells, the extracted data to be presented at an output of the device. When data is to be read from a cell, the cell is activated and a transistor in the cell (generally referred to as an access transistor) will or will not change a pre-established voltage on the bit line depending on the data stored in the active cell. Because transistors in the memory cells are typically very small and thus are weak, and generally each bit-line is coupled to hundreds of other (inactive) cells resulting in each bit-line having significant capacitive loading, the amount of change in bit-line voltage during a defined time period is relatively small. To determine what data value, the active cell is storing, each bit-line has attached thereto a sense amplifier that amplifies any change in the bit-line voltage and “slices” the amplified voltage change to produce at an output of the sense amplifier a binary one or zero. The output of the sense amplifier is then coupled to the output of the memory for use in the apparatus using the memory device, e.g., a computer.
Bit-lines are of two types: differential and single-ended. Differential bit-lines are less susceptible to induced noise than single-ended hit-lines but a memory having differential bit-lines requires twice the number of bit-line conductors compared to a memory with single-ended bit-lines and a concomitant increase in memory complexity and area. However, a memory with differential bit lines might have the fastest memory access time (used here as the time required for the memory to present data at its output measured from when an address is first applied to the memory and the memory enabled) and is normally used where a memory cell has differential outputs, e.g., static random access memory (SRAM). For those memory devices having non-differential output memory cells, single-ended bit-lines are used, such as in a read-only memory (ROM), electrically-programmable memory (e.g., EEPROM, FLASH, etc.), or a dynamic random access memory (DRAM). However, some memory designs that would otherwise use single-ended bit-lines, it might be desirable to find a way to use differential bit-lines so that the memory can operate faster than a single-ended design.
This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.
Described embodiments provide a memory having at least one sense amplifier. The at least one sense amplifier has a cross-coupled gain stage with first and second amplifier nodes, first and second switches, and first and second capacitors. The first switch, in response to a control signal, selectively couples the first amplifier node to a first input of the sense amplifier. The second switch, in response to the control signal, selectively couples a first internal node to a second input of the sense amplifier. The first capacitor is coupled between the first internal node and the second amplifier node, and the second capacitor is coupled between the first amplifier input and a second internal node.
Other embodiments of the present invention will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings in which like reference numerals identify similar or identical elements.
Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments necessarily mutually exclusive of other embodiments. The same applies to the term “implementation”.
It should be understood that the steps of the exemplary methods set forth herein are not necessarily required to be performed in the order described, and the order of the steps of such methods should be understood to be merely exemplary. Likewise, additional steps might be included in such methods, and certain steps might be omitted or combined, in methods consistent with various embodiments of the present invention.
Also for purposes of this description, the terms “couple”, “coupling”, “coupled”, “connect”, “connecting”, or “connected” refer to any manner known in the art or later developed in which energy is allowed to be transferred between two or more elements, and the interposition of one or more additional elements is contemplated, although not required. Conversely, the terms “directly coupled”, “directly connected”, etc., imply the absence of such additional elements. Signals and corresponding nodes or ports might be referred to by the same name and are interchangeable for purposes here. The term “or” should be interpreted as inclusive unless stated otherwise. Further, elements in a figure having subscripted reference numbers, (e.g., 1001, 1002, . . . 100K might be collectively referred to herein using the reference number 100.
The present invention will be described herein in the context of illustrative embodiments of a sense amplifier adapted for use in a solid-state memory, such as a read-only, a dynamic random access memory, or the like. It is to be appreciated, however, that the invention is not limited to the specific apparatus and methods illustratively shown and described herein.
The memory 100 is organized into two banks, a top bank 102 and a substantially identical bottom bank 104. These banks share common sense amplifiers 106 although only one bank at a time is active. For purposes here, only the top bank 102 is described but the features and operation of the bottom bank 104 is the same.
In the top bank 102, a conventional address decoder 108 receives a multi-bit address via address bus 110 from a utilization device such as a computer or the like. The address decoder 108 enables one of several word lines WL0-WLN (N is an integer ≧1) in response to the address. In this example, an enabled word line has a voltage substantially equal to VDD (the power supply voltage) whereas the remaining word lines have a voltage of substantially zero volts. These voltages are sufficient to turn on and turn off an access transistor in each of the memory cells 112, described below. It is understood that the decoder 108 may assert other voltages on the word lines.
Each of the memory cells 112 have an input coupled to a corresponding word line and an output coupled to corresponding bit line pairs BL0, BL0′-BLM, BLM′ where M is an integer ≧0. The bit lines couple the outputs of the memory cells coupled thereto to an input TOP_INP, TOP_INN of a corresponding sense amplifier 1060-106M. As will be explained in more detail below in connection with
In this embodiment, each of the memory cells 112 comprises an access transistor (not numbered) having a gate or control terminal coupled to the corresponding word line (WL) and a drain terminal (an output terminal) coupled to a first (true) corresponding bit line (BL). The data value stored in a given memory cell is established by whether or not the source terminal (also an output terminal) of the access transistor is coupled to a second (complementary) bit line (BL′) or is not so connected. For example, the source terminal of the access transistor in memory cell 1122 is coupled to the bit line BLM′ and thus stores a logical 0, whereas the access transistor in cell 1121 is not connected to bit line BL0′ and that cell stores a logical 1 although in an alternative embodiment the logic values are reversed. In an alternative embodiment, in each memory cell the source terminal is coupled to the complementary bit line and the drain terminals are either coupled or not coupled to the corresponding true bit line depending on the data value to be stored in the memory cell.
Data on the bit line pairs BL, BL′ is described herein as “complementary” even though the voltages on the bit lines do not change significantly when a memory cell does not conduct (a non-discharge condition).
Operation of the memory 100 is under the control of controller 120. The controller 120 is a conventional state machine or logic block configured to perform a read operation (and write operations if the memory is suitably configured) in response to a read request. The controller receives a subset (not shown) of the memory address bits from bus 110 so as to configure the sense amplifiers 106 to read data from the desired memory bank or, when the sense amplifiers are coupled to multiple bit line pairs in one bank, read data from the desired pair of the multiple bit line pairs.
In response to the controller 120 and prior to reading data out of the memory 100, the bit line pairs BL0, BL0′-BLN′ are precharged/discharged by the sense amplifiers 106. As will be explained in more detail in connection with
Each of the inputs 202, 202′ and 204, 204′ are coupled to corresponding nodes 206, 206′ and 208, 208′ by multiplexers 210 and 212, respectively. These nodes can be connected to other multiplexers (not shown) to facilitate sharing of the sense amplifier 106 with additional bit line pairs in the respective banks 102, 104 to reduce the total number of sense amplifiers in the memory 100 as required. Selection of which multiplexer is enabled is determined by the address applied to the controller 120.
The multiplexers 210, 212 each have two pairs of switches 214, 216 and 218, 220. Referring to just multiplexer 210 (multiplexer 212 is substantially the same as multiplexer 210 in this embodiment), the first pair of switches 214, 216, controlled by a common control signal TOP_MUX_ENABLE, either couple the bit line connected to input 202 to a power supply node VDD or to the node 206. Similarly, the second pair of switches 218, 220, controlled by the common control signal that controls switches 214 and 216, either couple the bit line connected to input 202′ to ground or to the node 206′. Switches 214, 218 are closed to precharge the bit lines and switches 216, 220 are closed when data is being read out of the top bank 102.
In one embodiment, the switches 214, 216 are p-channel metal-oxide-semiconductor (PMOS) transistors and switches 218, 220 are n-channel metal-oxide-semiconductor (NMOS) transistors.
In response to control signal SENSE_TOP_ENABLE, switch 222 couples node 206 to node 224 when data is being read from the top bank 102 and switch 226, in response to control signal SENSE_BOT_ENABLE, couples node 208 to node 228 when data is being read from the bottom bank. As will be explained in more detail in connection with
Capacitor 232 AC-couples the node 206′ to node 228 and capacitor 234 AC-couples node 208′ to node 224. These capacitors allow the bit lines in each pair of bit lines to have a significant voltage difference (e.g., bit line BL at VDD and BL′ at ground) during precharge or idle state of the memory without upsetting operation of the cross-coupled amplifier during the evaluation state or phase of reading data from the memory as will be explained in more detail in connection with
To precharge the capacitors 232 and 234 prior to reading data from the memory cells 112 (
Each of the capacitors 232, 234 can be implemented using MOS transistors or metal-insulator-metal (MIM) capacitors. To implement the capacitors using MOS transistors, the gate terminal as one terminal of the capacitor and the source and drain terminals connected together as the other terminal of the capacitor.
Cross-coupled amplifier 230 has two conventional inverters (not numbered) with the input of each inverter connected to the output of the other inverter. Both inverters have an NMOS transistor and a PMOS transistor serially coupled between the power supply node VDD and a common node 238. A switch 238, typically an NMOS transistor, couples the node 236 to ground when enabled by control signal SENSE_AMP_ENABLE.
As will be explained in more detail in connection with
The signal BUMP is substantially equal to ground potential during the idle state of the memory 100 so that the switches 240, 242 assure that the capacitors 234, 232, respectively, are discharged. However, if the top bank 102 is to be read, then switch 242 opens so that any change in voltage on the bit line connected to terminal 202′ is conveyed to the cross-coupled amplifier 230. Similarly, if the bottom bank 104 is to be read, then switch 240 opens so that any change in voltage on the bit line connected to terminal 204′ is conveyed to the cross-coupled amplifier 230.
The data value of the enabled memory cell is determined by the cross-coupled amplifier 230 is buffered by inverters 246 coupled to nodes 224, 228. The inverters in turn drive output stage 248 of serially connected transistors (not numbered) that produces the output of the sense amplifier, DATA OUT. It is understood that the output implementation shown here is exemplary and that other implementations may be used instead of that shown here.
Operation of the memory 100 has three exemplary states: idle, transition, and evaluation.
Referring to
Once an address is applied to the address decoder 108 and a read request signal is asserted to controller 120, the memory enters the transition state 304 during which a word line WL is driven high (to approximately VDD), the bit lines BL, BL′ are released from VDD and VSS, respectively, the bit lines coupled to corresponding inputs 206, 206′ due to the reconfiguration of the switches in multiplexer 210. Depending on the address applied to the decoder 108 and controller 120, other multiplexers (not shown) will couple other bit lines to nodes 206, 206′ as discussed above.
During the transition state, the memory cells coupled to the enabled word line either draw together the voltages on their respective bit line pairs (i.e., the voltage on bit line BL and node 206 decreases from VDD while the voltage on bit line BL′ and node 206′ concurrently increases from VSS) or leave the voltages on the bit lines essentially unchanged. However and unlike switch 222, switch 226 opens to reduce capacitive loading on node 228 since in tins example data is being read from the top bank 102.
As the voltage on hit line pairs coupled to the inputs 206, 206′ changes, the voltages on corresponding nodes 224 and 228 also change. As shown in
After waiting a sufficient time for the enabled memory cell to change the voltages on the bit line pairs BL, BL′ by a desired amount, e.g. 100 mV, then the controller 120 opens switch 222 decouple bit line BL from the node 224 initiating the evaluation phase 306. The opening of switch 222 reduces capacitive loading on node 224 to speed-up operation of the cross-coupled amplifier 230, once enabled, during the evaluation phase.
The purpose of which will be described in more detail in connection with
After waiting a short delay after the beginning of the evaluation state to allow for the charge injection by the BUMP signal to take effect, the controller 120 closes switch 238 to enable the cross-coupled amplifier 230. Because of the difference in voltage between nodes 224 and 228, the cross-coupled amplifier 230 regeneratively amplifies this voltage difference to quickly resolve what the logic value is stored in the enabled memory cell (a logical “0” in this instance) and DATA OUT goes low.
The timing relationship between the transition in the signal BUMP, closing of switch 238, and opening of switch 222 is exemplar and might be different, depending on requirements of the memory 100, the integrated circuit manufacturing process used to fabricate the memory, operating voltage and temperature, etc.
In contrast to the exemplary operation shown in
The “bump” in the voltage on node 224 serves to unbalance the amplifier 230 to allow the amplifier to quickly converge when no significant change in the bit line voltages occurs or to overcome any offset voltage, intentional (e.g., by using different device sizes) or unintentional (e.g., due to manufacturing variations), the amplifier 230 might have. The amount of capacitance for capacitor 234 (and capacitor 232) is chosen to be sufficient for injecting, enough charge so that the concomitant voltage “bump” 410 is sufficient for the amplifier 230 to rapidly converge but not so much that the amount of voltage “bump” 310 is sufficient to cause the cross-coupled amplifier 230 to operate incorrectly and produce the wrong output data (e.g., a logical “1” instead of a logical “0”) over all expected processing, voltage, and temperature parameter limits of the memory 100.
While embodiments have been described with respect to circuit functions, the embodiments of the present invention are not so limited. Possible implementations, either as a stand-alone memory or as memory embedded with other circuit functions, may be embodied in or part of a single integrated circuit, a multi-chip module, a single card, system-on-a-chip, or a multi-card circuit pack, etc. but are not limited thereto. As would be apparent to one skilled in the art, the various embodiments might also be implemented as part of a larger system. Such embodiments might be employed in conjunction with, for example, a digital signal processor, microcontroller, field-programmable gate allay, application-specific integrated circuit, or general-purpose computer. It is understood that embodiments of the invention are not limited to the described embodiments, and that various other embodiments within the scope of the following claims will be apparent to those skilled in the art.