Claims
- 1. A digital signal processor comprising:A. a first data bus carrying first data signals; B. a first address bus carrying first address signals indicating the address of the first data signals in a first address space; C. a second data bus separate from the first data bus and carrying second data signals; D. a second address bus separate from the first address bus and carrying second address signals indicating the address of the second data signals in a second address space; E. arithmetic and logic circuitry coupled to the first and second data buses, the arithmetic and logic circuitry including multiplier circuitry coupled to an input of an arithmetic and logic unit and an accumulator coupled to an output of the arithmetic and logic unit; and F. a memory wait state register coupled to the first data bus and the first address bus, the wait state register having plural portions.
- 2. The processor of claim 1 in which the first address space is segmented into plural portions and a portion of the memory wait state register corresponds to a segment in the first address space.
- 3. The processor of claim 1 in which the memory wait state register has at least four portions.
- 4. The processor of claim 1 in which each portion of the memory wait state register contains four bits of information.
- 5. The processor of claim 1 in which the first data bus is a data bus and the second data bus is an instruction bus.
- 6. The processor of claim 1 in which each portion of the memory wait state register contains at least three bits of information.
- 7. The processor of claim 1 in which the memory wait state register is connected to the first data bus to receive wait state data signals from the first data bus.
- 8. The processor of claim 1 in which the memory wait state register has 16 portions.
Parent Case Info
This application is a divisional of application Ser. No. 09/360,488, filed Jul. 23, 1999, now pending; which is a divisional of application Ser. No. 08/906,863, filed Aug. 6, 1997, now U.S. Pat. No. 5,946,483; which is a divisional of application Ser. No. 08/293,259, filed Aug. 19, 1994, now U.S. Pat. No. 5,907,714; which is a continuation of application Ser. No. 07/967,942, filed Oct. 28, 1992, now abandoned; which is a continuation of application Ser. No. 07/347,967, filed May 4, 1989, now abandoned.
US Referenced Citations (26)
Non-Patent Literature Citations (6)
Entry |
Second Generation TMS320 User's Guide ; p. 3-6, 5-2-5-7, 3-34.* |
Lin et al. The TMS320 Family of Digital Signal Processors pp. 1143-1159.* |
First-Generation TMS320 User's Guide, Texas Instruments, pp. 3-9, A-1-20, 6-2-5, Apr. 1988. |
“DSP56000 Digital Signal Processor's User's Manual”, Motorola, 1986, pp. 2-12-18, 3-2, 7-1-3. |
“DSP96001”, Motorola, 1988, pp. 1, 2, 6, 9, 10. |
Second-Generation TMS320 User's Guide, Texas Instruments, pp. 6-10-26,Dec. 1987. |
Continuations (2)
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Number |
Date |
Country |
Parent |
07/967942 |
Oct 1992 |
US |
Child |
08/293259 |
|
US |
Parent |
07/347967 |
May 1989 |
US |
Child |
07/967942 |
|
US |