The invention relates to the field of photolithographic processing. More particularly, various aspects of the invention relate to reducing the number of iterations required for performing optical proximity correction (OPC) on microcircuit layout designs.
Electronic circuits, such as integrated microcircuits, are used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating microcircuit devices typically involves many steps, sometimes referred to as the “design flow.” The particular steps of a design flow often are dependent upon the type of microcircuit, its complexity, the design team, and the microcircuit fabricator or foundry that will manufacture the microcircuit. Typically, software and hardware “tools” verify the design at various stages of the design flow by running software simulators and/or hardware emulators. These steps aid in the discovery of errors in the design, and allow the designers and engineers to correct or otherwise improve the design. These various microcircuits are often referred to as integrated circuits (IC's).
Several steps are common to most design flows. Initially, the specification for a new circuit is transformed into a logical design, sometimes referred to as a register transfer level (RTL) description of the circuit. With this logical design, the circuit is described in terms of both the exchange of signals between hardware registers and the logical operations that are performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as the Very high speed integrated circuit Hardware Design Language (VHDL). The logic of the circuit is then analyzed, to confirm that it will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as “functional verification.”
After the accuracy of the logical design is confirmed, it is converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist, describes the specific electronic devices (such as transistors, resistors, and capacitors) that will be used in the circuit, along with their interconnections. This device design generally corresponds to the level of representation displayed in conventional circuit diagrams. The relationships between the electronic devices are analyzed, to confirm that the circuit described by the device design will correctly perform the desired functions. This analysis is sometimes referred to as “formal verification.” Additionally, preliminary timing estimates for portions of the circuit are often made at this stage, using an assumed characteristic speed for each device, and incorporated into the verification process.
Once the components and their interconnections are established, the design is again transformed, this time into a physical design that describes specific geometric elements. This type of design often is referred to as a “layout” design. The geometric elements, which typically are polygons, define the shapes that will be created in various layers of material to manufacture the circuit. Typically, a designer will select groups of geometric elements representing circuit device components (e.g., contacts, channels, gates, etc.) and place them in a design area. These groups of geometric elements may be custom designed, selected from a library of previously-created designs, or some combination of both. Lines are then routed between the geometric elements, which will form the wiring used to interconnect the electronic devices. Layout tools (often referred to as “place and route” tools), such as Mentor Graphics' IC Station or Cadence's Virtuoso, are commonly used for both of these tasks.
IC layout descriptions can be provided in many different formats. The Graphic Data System II (GDSII) format is a popular format for transferring and archiving two-dimensional graphical IC layout data. Among other features, it contains a hierarchy of structures, each structure containing layout elements (e.g., polygons, paths or poly-lines, circles and textboxes). Other formats include an open source format named Open Access, Milkyway by Synopsys, Inc., EDDM by Mentor Graphics, Inc., and the more recent Open Artwork System Interchange Standard (OASIS) proposed by Semiconductor Equipment and Materials International (SEMI). These various industry formats are used to define the geometrical information in IC layout designs that are employed to manufacture integrated circuits. Once the microcircuit device design is finalized, the layout portion of the design can be used by fabrication tools to manufacturer the device using a photolithographic process.
There are many different fabrication processes for manufacturing a circuit, but most processes include a series of steps that deposit layers of different materials on a substrate, expose specific portions of each layer to radiation, and then etch the exposed (or non-exposed) portions of the layer away. For example, a simple semiconductor device component could be manufactured by the following steps. First, a positive type epitaxial layer is grown on a silicon substrate through chemical vapor deposition. Next, a nitride layer is deposited over the epitaxial layer. Then specific areas of the nitride layer are exposed to radiation, and the exposed areas are etched away, leaving behind exposed areas on the epitaxial layer, (i.e., areas no longer covered by the nitride layer). The exposed areas then are subjected to a diffusion or ion implantation process, causing dopants, for example phosphorus, to enter the exposed epitaxial layer and form charged wells. This process of depositing layers of material on the substrate or subsequent material layers, and then exposing specific patterns to radiation, etching, and dopants or other diffusion materials, is repeated a number of times, allowing the different physical layers of the circuit to be manufactured.
Each time that a layer of material is exposed to radiation, a mask must be created to expose only the desired areas to the radiation, and to protect the other areas from exposure. The mask is created from circuit layout data. That is, the geometric elements described in layout design data define the relative locations or areas of the circuit device that will be exposed to radiation through the mask. A mask or reticle writing tool is used to create the mask or reticle based upon the layout design data, after which the mask can be used in a photolithographic process. The image created in the mask is often referred to as the intended or target image, while the image created on the substrate, by employing the mask in the photolithographic process is referred to as the printed image.
As designers and manufacturers continue to increase the number of circuit components in a given area and/or shrink the size of circuit components, the shapes reproduced on the substrate (and thus the shapes in the mask) become smaller and are placed closer together. This reduction in feature size increases the difficulty of faithfully reproducing the image intended by the layout design onto the substrate. Adding to the difficulty associated with increasingly smaller feature size is the diffractive effects of light. As light illuminates the mask, the transmitted light diffracts at different angles in different regions of the mask. These effects often result in defects where the intended image is not accurately “printed” onto the substrate during the photolithographic process, creating flaws in the manufactured device.
To address this problem, one or more resolution enhancement techniques are often employed to improve the resolution of the image that the mask forms on the substrate during the photolithographic process. Examples of various resolution enhancement techniques are discussed in “Resolution Enhancement Technology: The Past, the Present, and Extensions for the Future,” Frank M. Schellenberg, Optical Microlithography XVII, edited by Bruce W. Smith, Proceedings of SPIE Vol. 5377, which article is incorporated entirely herein by reference. One of these techniques, radiation amplitude control, is often facilitated by modifying the layout design data employed to create the lithographic mask. One way to implement this technique, for example, is to adjust the edges of the geometric elements in the layout design so that the mask created from the modified layout data will control the radiation amplitude in a desired way during a lithographic process. The process of modifying the layout design data in this manner is often referred to as “optical proximity correction” or “optical process correction” (OPC).
As previously noted, a layout design is made up of a variety of geometric elements, which typically are polygons. In a conventional optical proximity correction process, the edges of these polygons are fragmented. More particularly, the individual edges of each polygon are divided into smaller sections, often referred to as edge segments or edge fragments. The size of the fragments and the particular edges to be fragmented are dependent upon parameters of the optical proximity correction process. The fragmenting of edges facilitates the optical proximity correction process by allowing the edge segments to be rearranged or edited to realize the desired modifications. Additionally, geometric features that will increase the fidelity of the photolithographic process may be added to the design by moving or displacing the fragments. For example, some optical proximity correction processes will reconfigure the edge segments of a polygon to create serifs at one or more corners.
Optical proximity correction is an iterative process. That is, the lithographic process that will be used to manufacture the integrated circuit is simulated to determine if the simulated printed image matches the intended printed image. Modifications are made to the layout design based upon the simulation results, and the lithograph process is simulated again. When the simulated printed image cannot be substantially improved by further displacement of the edge segments, it is often said that the optical proximity correction process has converged. This process of simulation, modification, and simulation is repeated until the simulated printed image significantly corresponds to the intended printed image, or until the optical proximity correction process has converged.
Layout designs can be very large. For example, one layout data file for a single layer of a field programmable gate array may be approximately 58 gigabytes. Accordingly, performing even a single iteration of an optical proximity correction process on a design is computationally intensive. Repeating the optical proximity correction process until the simulated printed image matches the intended printed image, or until the optical proximity process has converged, only adds to the time required to finalize the layout design. Often, it can take as many as eight iterations for an optical proximity correction process to converge. Due to the number of iterations of optical proximity correction required and the complexity and size of modern layout designs, even when employing advanced computer processing techniques, the time required to perform optical proximity correction is often measured in days.
Aspects of the present invention relate to techniques for reducing the number of iterations required to have an optical proximity correction process converge upon a suitable solution.
Various implementations of the present invention provide methods for adjusting edge segments within a layout design such that fewer iterations of an optical proximity correction process are required for covergence. With some implementations, multiple iterations of an optical proximity correction process are performed on a portion of a layout design. The displacement of various edge segment within the subportion is recorded at each iteration of the optical proximity correction process, including the final displacement. Furthermore, the various edge segments within the subportion are categorized according to type. The categorization of edge segments within the subportion along with their final displacement then are used to adjust the edge segments within the layout design.
In some implementations, a select number of iterations of the optical proximity correction process are performed upon the remainder of the layout design prior to the edge segments being adjusted. With still other implementations of the invention, the optical proximity process is performed on the remainder of the layout design after the edge segments have been adjusted based upon the recorded final displacement for like categorized edge segments. In further examples of the invention, the displacement of particular types of edge segments in a first layout design is used to adjust edge segments in a second layout design.
These and additional aspects of the invention will be further understood from the following detailed disclosure of illustrative embodiments.
The present invention will be described by way of illustrative embodiments shown in the accompanying drawings in which like references denote similar elements, and in which:
The disclosed technology includes all novel and unobvious features, aspects, and embodiments of the systems and methods described herein, both alone and in various combinations and sub-combinations thereof. The disclosed features, aspects, and embodiments can be used alone or in various novel and unobvious combinations and sub-combinations with one another.
Although the operations of the disclosed methods are described in a particular sequential order for convenient presentation, it should be understood that this manner of description encompasses rearrangements, unless a particular ordering is required by specific language set forth below. For example, operations described sequentially may in some cases be rearranged or performed concurrently. Moreover, for the sake of simplicity, the disclosed flow charts and block diagrams typically do not show the various ways in which particular methods can be used in conjunction with other methods. Additionally, the detailed description sometimes uses terms like “determine” to describe the disclosed methods. Such terms are high-level abstractions of the actual operations that are performed. The actual operations that correspond to these terms will vary depending on the particular implementation and are readily discernible by one of ordinary skill in the art.
Some of the methods described herein can be implemented by software stored on a computer readable storage medium, or executed on a computer. Additionally, some of the disclosed methods may be implemented as part of a computer implemented electronic design automation (EDA) tool. The selected methods could be executed on a single computer or a computer networked with another computer or computers. For clarity, only those aspects of the software germane to these disclosed methods are described; product details well known in the art are omitted.
As described above, various examples of the invention may be implemented through the execution of software instructions by a computing device, such as a programmable computer. Accordingly,
The processing unit 105 and the system memory 107 are connected, either directly or indirectly, through a bus 113 or alternate communication structure, to one or more peripheral devices. For example, the processing unit 105 or the system memory 107 may be directly or indirectly connected to one or more additional memory storage devices, such as a fixed magnetic disk drive 115, a removable magnetic disk drive 117, an optical disk drive 119, or a flash memory device 121. The processing unit 105 and the system memory 107 also may be directly or indirectly connected to one or more input devices 123 and one or more output devices 125. The input devices 123 may include, for example, a keyboard, a pointing device (such as a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. The output devices 125 may include, for example, a monitor display, a printer and speakers. With various examples of the computing device 101, one or more of the peripheral devices 115-125 may be internally housed with the computing unit 103. Alternately, one or more of the peripheral devices 115-125 may be external to the housing for the computing unit 103 and connected to the bus 113 through, for example, a Universal Serial Bus (USB) connection.
With some implementations, the computing unit 103 may be directly or indirectly connected to one or more network interfaces 127 for communicating with other devices making up a network. The network interface 127 translates data and control signals from the computing unit 103 into network messages according to one or more communication protocols, such as the transmission control protocol (TCP) or the Internet protocol (IP). Also, the network interface 127 may employ any suitable connection agent (or combination of agents) for connecting to a network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art, and thus will not be discussed here in more detail.
It should be appreciated that the computer 101 is illustrated as an example only, and is not intended to be limiting. Various embodiments of the invention may be implemented using one or more computing devices that include the components of the computer 101 illustrated in
In a photolithographic process, as explained above, electromagnetic radiation is transmitted through selectively transparent areas of a mask. The radiation passing through these transparent areas then irradiates desired portions of a photoresistive material on a layer of semiconductor substrate. The mask in turn is created from layout design data describing the geometric features that should be manufactured on the semiconductor substrate, by way of the photolithographic process, in order to create the desired circuit. For example, if a transistor should have a rectangular gate region, then the layout design data will include a rectangle defining that gate region. This rectangle in the layout design data is then implemented in a mask for “printing” the rectangular gate region onto the substrate.
During a photolithographic process, however, optical effects will prevent the shapes defined by the mask from being faithfully imaged onto the substrate. Diffractive effects, for example, may distort the image produced by a mask. Moreover, these distortions become more pronounced as the images produced by the mask become smaller relative to the wavelength of radiation used in the photolithographic process. Thus, the rectangular mask feature 201 illustrated in
To correct for these optical distortions, many circuit designers will attempt to modify the layout design data, producing modified mask features, to enhance the resolution of the images that will be produced by the modified mask during the photolithographic process. Thus, some designers will employ an optical proximity correction (OPC) process on the layout design data, in an effort to better control the amplitude and phase of the radiation transmitted by the mask at specific locations. In a conventional optical proximity correction process, the edges of the geometric elements in the design are fragmented. For example, as shown in
In attempting to correct for optical distortions within the photolithographic process, the optical proximity correction process simulates the printed image. That is, the photolithographic process is simulated in order to produce a simulated printed image.
Next, the edge segments are individually moved in order to improve the resolution of the simulated printed image for the resulting mask. For example, as shown in
This process of simulating the image that would be produced using the mask feature, comparing the simulated image to the target image, and moving edge segments accordingly may be repeated a number of times. Each cycle of simulation, compare, and move is referred to as an iteration of the optical proximity correction process. Typically, selecting edge segments to be moved during a given iteration, and the distance the edge segments are displaced, are determined based upon the edge placement errors for the edge fragment. For example, an optical proximity correction process may move an edge segment some factor of the edge placement error for that edge fragment away from the simulated printed image or the target image. Additionally, each edge segment may be displaced the same distance during a given iteration. The specific parameters that control edge movement are dependent upon the tool used to implement the optical proximity correction process and the optical proximity correction process recipe.
Typically, the optical proximity correction process is allowed to iterate until the simulated image is sufficiently similar to the target image (e.g., both d1 and d2 are smaller than a threshold value), or until it is determined that the edge segments have converged on locations where no further movement of the edge segments will improve the simulated image.
As stated above, optical proximity correction is an iterative process. The number of iterations required for the process to converge on a suitable solution may be eight to ten iterations or more, depending upon the layout design and the “recipe”. Even with advanced computing resources, sophisticated optical proximity correction tools, and good recipes, the time needed to perform eight to ten iterations is typically a few days. One reason for the high number of required iterations is due to fragments oscillating around a final target. Without carefully designed feedback processes individual to a particular layout design, edge segments will typically oscillate around the final target further adding to the number of iterations required for the process to converge. Another reason that the number of required iterations is high is due to the differing speed with which different types of edge segments converge. For example, with some layout designs the short edge segments forming the end edge between two longer edges (typically called line end fragments) converge much slower than other types of edge segments within the layout design do.
With some implementations of the invention, the edge fragment movements are observed and tracked while optical proximity correction is applied to a small portion or “clip” of a layout design. The tracked movements are used to speed the rate of convergence while optical proximity correction is applied to the balance of the layout design. For example, the observed final displacement for selected categories of edge segments can be used to “fast forward” the movements or displacement of similarly categorized edge segments.
With some implementations of the invention, the optical proximity correction unit 503 is a conventional optical proximity tool. For example, embodiments of the present invention may be implemented in conjunction with the Calibre optical proximity correction tools by Mentor Graphics Corporation of Wilsonville, Oreg. In other implementation of the invention, the optical proximity correction tool 503 is one designed specifically for use by the displacement aware correction tool 501. As seen in
As described in detail above, optical proximity correction is an iterative process whereby edges in a layout design are partitioned into edge segments and the edge segments are displaced. As the specifics of optical proximity correction have already been discussed in detail above, the detailed implementations of the optical proximity correction processes employed by various implementations of the invention have been omitted from the balance of this disclosure. Instead, general operations germane to an optical proximity correction process, for example, edge segment, displacement, iteration, or convergence are used to describe the optical proximity correction operations implemented with various embodiments of the present invention. These abstract descriptions are to be interpreted in light of the above description of optical proximity correction and the accompanying figures, as well as the knowledge possessed by those of ordinary skill in the art related to optical proximity correction and the photolithographic process.
As described above,
With some implementations of the invention, a tool such as the displacement aware optical proximity correction tool 501 may be employed to perform the method detailed in
Once the operation 407 and the operation 409 of performing optical proximity correction on a select portion of a layout design and recording the edge segment movements is complete, categorizing the edge segments is initiated by the operation 411. The edge segment classification unit 519 of the displacement aware optical proximity correction tool 501 may be used to perform the operation 411. With some implementations, the edge segments will have been categorized by the optical proximity correction process. More particularly, some optical proximity correction processes categorize the edge segments as part of the optical proximity correction process. For example, the edge segments may be categorized as a line end, an edge, or a corner segment.
With other implementations of the invention, the edge segments may be categorized based upon the length of the segments. With still other implementations, the edge segments may be categorized by the type of corners associated with the edge segments. With yet other implementations of the invention, the edge segments may be categorized by the length and the edge segment corner types. As an example, some implementations of the invention will assign a value to each edge segment corner type. For example, an edge segment without a corner may be assigned a value of 0, a convex corner may be assigned a value of 1, and a concave corner a may be assigned a value of 2. More particularly, the edge segment 301A of
After the operation 411 is completed, the operation 413 associates a recorded final displacement with an edge segment category. With some implementations of the invention, this is accomplished at the same time that the edge segments are classified, for example, by the edge segment classification unit 519. Still with other implementations of the invention, a final displacement is associated with each edge segment category after the edge segments are categorized. For example, by a tool such as the category compilation unit 521 of the displacement aware optical proximity correction tool 501. In various implementations of the invention, the recorded final displacement associated with a select edge segment category is the average of all the recorded final displacements for the edge segments within the selected category. With other implementations, the recorded final displacement associated with a select edge segment category is the largest recorded displacement of all the recorded final displacements for the edge segments within the selected category. Still, with other implementations, the recorded final displacement associated with a select edge segment category is the smallest of all the recorded final displacements for the edge segments within the selected category.
With still further implementations of the invention, an associative array or “look up table” may be compiled from the edge segment categories and associated final displacements. For example, the category compilation unit 521 of the displacement aware optical proximity correction tool 501 might compile an associative array of key value pairs. Wherein each key would correspond to an edge segment category and each value would correspond to the associated final displacement for the category.
The displacement aware categorization process 601 further includes an operation 613 for capturing the displacements of selected edge segments during the optical proximity correction process. As can be seen in
As can be seen in
As described previously,
With some implementations of the invention, the displacement aware optical proximity correction tool 501 may be used to perform the operation 405. As explained previously, the tool 501 includes an optical proximity correction unit 503, which may be employed to perform optical proximity correction on a layout design. More particularly, the optical proximity correction unit 503 may be used to perform the operations 415 and 421 of the method 405. With some implementations of the invention, the operation 415 for pre-processing the layout design will include performing a selected number of iterations of optical proximity correction on the layout design and recording various edge segment displacements during the optical proximity correction process. Still, with some implementations of the invention, the operation 417 for pre-processing the layout design will merely ensure the polygon edges within the layout design are properly fragmented into edge segments. With various implementations of the invention, the operation 417 for pre-processing the layout design will depend upon the specific method employed to classify the edge segments.
More particularly, with some implementations of the invention, the edge segments are classified based upon the length of the edge segment, the edge segment corner types, the edge segment displacement during the first iteration of optical proximity correction, and the edge segment displacement during the second iteration of optical proximity correction. Accordingly, the operation 417 for pre-processing the layout design would include performing at least two iterations of optical proximity correction on the layout design, such that the edge segments within the layout design may be properly classified. For example,
The edge segment classification unit 523 of the tool 501 may be employed to perform the operation 417 for categorizing the edge segments within a layout design. In some implementations of the invention, the edge segment classification unit 519 is the same as the edge segment classification unit 523, while with other implementations of the invention, the edge segment classification units 519 and 523 are separate and different apparatuses. As explained previously, some implementations categorize the edge segments within a layout design based upon the edge segment type. For example, a line end, an edge, or a corner segment. As seen in
Once the edge segments within the layout design are classified, the category search unit 525 and the edge segment displacement unit 527 may be employed to identify the final displacement associated to selected edge segment categories within the layout design and adjust the edge segment displacement accordingly. More particularly, the operation 413 associates a final edges segment displacement with a particular edge segment category. With the operation 419, the final displacement must be identified and applied to the particular edge segment. For example, the edge segment 803 of
The displacement aware optical proximity correction process 901 further includes an operation for performing a first iteration 907 of an optical proximity correction process on the layout design 903, an operation for performing a second iteration 909 of the optical proximity correction process on the layout design 903, an operation 911 for adjusting the edge segment displacements within the layout design, an operation for performing a third iteration 913 of the optical proximity correction process on the layout design, resulting in an adjusted layout design 915. With various implementations of the invention, the adjusted layout design 915 is saved to a memory storage location.
Although certain devices and methods have been described above in terms of the illustrative embodiments, the person of ordinary skill in the art will recognize that other embodiments, examples, substitutions, modification and alterations are possible. It is intended that the following claims cover such other embodiments, examples, substitutions, modifications and alterations within the spirit and scope of the claims.
Methods and apparatuses for altering a portion of a layout design have been shown. More particularly, techniques for reducing the number of iterations required to have an optical proximity correction process converge upon a suitable solution have been disclosed. In some implementations, multiple iterations of an optical proximity correction process are performed on a portion of a layout design. The displacement of various edge segments within the subportion are recorded at each iteration of the optical proximity correction process, including the final displacement. Furthermore, the various edge segments within the subportion are categorized according to type. The categorization of edge segments within the subportion along with their final displacement then are used to adjust the edge segments within the layout design.
In some implementations, a select number of iterations of the optical proximity correction process are performed upon the remainder of the layout design prior to the edge segments being adjusted. With still other implementations of the invention, the optical proximity process is performed on the remainder of the layout design after the edge segments have been adjusted based upon the recorded final displacement for like categorized edge segments. In further examples of the invention, the displacement of particular types of edge segments in a first layout design is used to adjust edge segments in a second layout design.
This application claims priority under 35 U.S.C. § 119(e) to U.S. Provisional Patent Application No. 60/973,085 entitled “A Generic Technique for Reducing OPC Iteration: Fast Forward OPC” filed on Sep. 17, 2008, and naming Le Hong et al. as inventors, which application is incorporated entirely herein by reference.
Number | Date | Country | |
---|---|---|---|
60973085 | Sep 2007 | US |