Patent Application
20250167095
This application claims priority to Taiwan Application Serial Number 112145013, filed Nov. 21, 2023, which is herein incorporated by reference in its entirety.
The present disclosure relates to a display device. More particularly, the present disclosure relates to a display device including a switch panel disposed under a display panel.
With the development of information technology, the demand for display devices that display images has also increased in various forms. Recently, research on transparent display devices is being actively carried out. One of the transparent display devices may include a transparent display panel with a certain degree of transparency and a switch panel disposed behind the transparent display panel. When the switch panel is in the light transmitting mode, the user can see the image information displayed on the transparent display panel, and can see the background information behind the transparent display panel; when the switch panel is in the opaque mode, the user can only see the image information displayed on the transparent display panel, but cannot see the background information behind the transparent display panel. Therefore, the transmittance of the light transmitting mode of the switch panel and the switching speed between the light transmitting mode and the opaque mode affect the display quality of the display device.
At least one embodiment of the present disclosure provides a display device including a switch panel disposed under a display panel. The switch panel includes a transparent electrode layer, a metal pattern layer and a transparent conductive pattern layer sequentially disposed on a substrate. The grain size of the transparent conductive pattern layer is less than the grain size of the transparent electrode layer, and the metal pattern layer and the transparent conductive pattern layer include openings to expose the transparent electrode layer. By setting the metal pattern layer and the transparent conductive pattern layer, the resistance is reduced to increase the switching speed between the light transmitting mode and the opaque mode, and the metal pattern layer and the transparent conductive pattern layer including openings to expose the transparent electrode layer can maintain or increase the transmittance of the light transmitting mode, thereby improving the display quality of the display device.
The display device according to at least one embodiment of the present disclosure includes a display panel and a switch panel. The display panel has a display surface and a bottom surface opposite to the display surface, where the bottom surface is located between the display surface and the switch panel. The switch panel includes a first substrate, a first transparent electrode layer, a first metal pattern layer, a first transparent conductive pattern layer, a second substrate, and a display medium disposed between the first substrate and the second substrate. The first transparent electrode layer is disposed on the first substrate and has a first grain size. The first metal pattern layer is disposed on the first transparent electrode layer and includes multiple first openings exposing the first transparent electrode layer. The first transparent conductive pattern layer covers the first metal pattern layer and includes multiple second openings exposing the first transparent electrode layer, and the first transparent conductive pattern layer has a second grain size less than the first grain size.
The display device according to at least another embodiment of the present disclosure includes a transparent display panel and a switch panel. The transparent display panel has a display surface and a bottom surface opposite to the display surface, where the bottom surface is located between the display surface and the switch panel. The switch panel includes a first substrate, a first transparent electrode layer, a first metal pattern layer, a first transparent conductive pattern layer, a second substrate, and a display medium disposed between the first substrate and the second substrate. The first transparent electrode layer is disposed on the first substrate and has a first grain size. The first metal pattern layer is disposed on the first transparent electrode layer and includes multiple first openings exposing the first transparent electrode layer. The first transparent conductive pattern layer covers the first metal pattern layer and includes multiple second openings exposing the first transparent electrode layer, and the first transparent conductive pattern layer has a second grain size less than the first grain size.
In the following description, in order to clearly present the technical features of the present disclosure, the dimensions (such as length, width, thickness, and depth) of elements (such as layers, films, substrates, and areas) in the drawings will be enlarged in unequal proportions. Therefore, the description and explanation of the following embodiments are not limited to the sizes and shapes presented by the elements in the drawings, but should cover the sizes, shapes, and deviations of the two due to actual manufacturing processes and/or tolerances. For example, the flat surface shown in the drawings may have rough and/or non-linear characteristics, and the acute angle shown in the drawings may be round. Therefore, the elements presented in the drawings in this case are mainly for illustration, and are not intended to accurately depict the actual shape of the elements, nor are they intended to limit the scope of patent applications in this case.
Furthermore, the words “about”, “approximately” or “substantially” used in the present disclosure not only cover the clearly stated numerical values and numerical ranges, but also cover those that can be understood by a person with ordinary knowledge in the technical field to which the present disclosure belongs. The permissible deviation range can be determined by the error generated during measurement, and the error is caused, for example, by limitations of the measurement system or process conditions. For example, two objects (such as the plane or traces of a substrate) are “substantially parallel” or “substantially perpendicular,” where “substantially parallel” and “substantially perpendicular,” respectively, mean that parallelism and perpendicularity between the two objects can include non-parallelism and non-perpendicularity caused by permissible deviation ranges.
In addition, “about” may mean within one or more standard deviations of the above values, such as within +30%, +20%, +10%, or +5%. Such words as “about”, “approximately”, or “substantially” as appearing in the present disclosure may be used to select an acceptable range of deviation or standard deviation according to optical properties, etching properties, mechanical properties, or other properties, rather than applying all of the above optical properties, etching properties, mechanical properties, and other properties with a single standard deviation.
The spatial relative terms used in the present disclosure, such as “below,” “under,” “above,” “on,” and the like, are intended to facilitate the recitation of a relative relationship between one element or feature and another as depicted in the drawings. The true meaning of these spatial relative terms includes other orientations. For example, the relationship between one element and another may change from “below” and “under” to “above” and “on” when the drawing is turned 180 degrees up or down. In addition, spatially relative descriptions used in the present disclosure should be interpreted in the same manner.
It should be understood that while the present disclosure may use terms such as “first”, “second”, “third” to describe various elements or features, these elements or features should not be limited by these terms. These terms are primarily used to distinguish one element from another, or one feature from another. In addition, the term “or” as used in the present disclosure may include, as appropriate, any one or a combination of the listed items in association.
Moreover, the present disclosure may be implemented or applied in various other specific embodiments, and the details of the present disclosure may be combined, modified, and altered in various embodiments based on different viewpoints and applications, without departing from the idea of the present disclosure.
By disposing the switch panel 20 under the display panel 10 and being independent of the display panel 10, the light transmitting mode and the opaque mode can be easily switched. Furthermore, by setting the first transparent electrode layer 201 with a larger grain size, and the first transparent electrode layer 201 being exposed by the first openings O1 of the first metal pattern layer 202 and the second openings O2 of the first transparent conductive pattern layer 203, the transmittance of the light transmitting mode can be maintained or increased, and by setting the first metal pattern layer 202 and the first transparent conductive pattern layer 203 with a smaller grain size, the resistance is reduced to increase the switching speed between the light transmitting mode and the opaque mode, thereby improving the display quality of the display device 1.
Referring to
As shown in
In some embodiments, the first grain size and the third grain size are both in a range from 45 nm to 55 nm, and the second grain size and the fourth grain size are both in a range from 30 nm to 40 nm. In some embodiments, the transmittance of the first transparent electrode layer 201 and the transmittance of the second transparent electrode layer 205 are greater than the transmittance of the first transparent conductive pattern layer 203 and the transmittance of the second transparent conductive pattern layer 207, respectively. The sheet resistance of the first transparent conductive pattern layer 203 and the sheet resistance of the second transparent conductive pattern layer 207 are less than the sheet resistance of the first transparent electrode layer 201 and the sheet resistance of the second transparent electrode layer 205, respectively. For example, the transmittance of the first transparent electrode layer 201 and the transmittance of the second transparent electrode layer 205 are both greater than 95%, and the transmittance of the first transparent conductive pattern layer 203 and the transmittance of the second transparent conductive pattern layer 207 are both less than 95%, e.g., the transmittance of the first transparent electrode layer 201 and the transmittance of the second transparent electrode layer 205 are both in a range from 95.5% and 99.9%, and the transmittance of the first transparent conductive pattern layer 203 and the transmittance of the second transparent conductive pattern layer 207 are both in a range from 88.5% to 94.5%. The sheet resistance of the first transparent conductive pattern layer 203 and the sheet resistance of the second transparent conductive pattern layer 207 are both less than 25Ω/□, and the sheet resistance of the first transparent electrode layer 201 and the sheet resistance of the second transparent electrode layer 205 are both greater than 25Ω/□, e.g., the sheet resistance of the first transparent conductive pattern layer 203 and the sheet resistance of the second transparent conductive pattern layer 207 are both in a range from 10.5Ω/□ to 24.5Ω/□, and the sheet resistance of the first transparent electrode layer 201 and the sheet resistance of the second transparent electrode layer 205 are both in a range from 25.5Ω/□ to 40.5Ω/□. By designing the relationship and range of the aforementioned characteristic values, the resistance can be reduced to increase the switching speed between the light transmitting mode and the opaque mode, and the transmittance of the light transmitting mode can be maintained or increased, thereby improving the display quality of the display device.
In some embodiments, the display panel 10 may be a self-luminous display panel, such as a micro light emitting diode (micro LED, μLED) panel or an organic light emitting diode (OLED) panel. In addition, the display panel 10 may be a transparent display panel, taking the micro LED panel as an example, the micro LED is located in the pixel area near the wiring, so the pixel area not only has the area for the micro LED, but also has the light transmitting area that is not covered by the micro LED, which in turn allows the micro LED panel to be used as the transparent display panel.
In some embodiments, the materials of the first substrate 200 and the second substrate 204 may include quartz, glass, polymer, and/or other suitable materials. The materials of the first transparent electrode layer 201, the second transparent electrode layer 205, the first transparent conductive pattern layer 203, and the second transparent conductive pattern layer 207 may include indium tin oxide (ITO), indium zinc oxide (IZO), aluminum tin oxide (ATO), aluminum zinc oxide (AZO), indium germanium zinc oxide (IGZO), or other suitable materials. The materials of the first metal pattern layer 202 and the second metal pattern layer 206 may include a metal with good electrical conductivity, such as aluminum, molybdenum, titanium, copper, silver, and other metals. In addition, the display medium 210 may include a suspended particle layer, a polymer dispersed liquid crystal layer, or an electrochromic material layer. For example, the materials of the first transparent electrode layer 201, the second transparent electrode layer 205, the first transparent conductive pattern layer 203, and the second transparent conductive pattern layer 207 include indium tin oxide, the materials of the first metal pattern layer 202 and the second metal pattern layer 206 include aluminum, and the display medium 210 include an electrochromic material layer. In some embodiments, the first transparent electrode layer 201, the second transparent electrode layer 205, the first metal pattern layer 202, the second metal pattern layer 206, the first transparent conductive pattern layer 203, and the second transparent conductive pattern layer 207 may be formed by a deposition process, a printing process, a photolithography process, an etching process, or other suitable process.
In some embodiments, the annealing temperature of the first transparent electrode layer 201 and the annealing temperature of the second transparent electrode layer 205 are greater than the annealing temperature of the first transparent conductive pattern layer 203 and the annealing temperature of the second transparent conductive pattern layer 207, respectively. For example, the annealing temperature of the first transparent electrode layer 201 and the annealing temperature of the second transparent electrode layer 205 are both greater than 400° C., the annealing temperature of the first transparent conductive pattern layer 203 and the annealing temperature of the second transparent conductive pattern layer 207 are both less than 300° C., e.g., the annealing temperature of the first transparent electrode layer 201 and the annealing temperature of the second transparent electrode layer 205 are both in a range from 420° C. to 480° C., and the annealing temperature of the first transparent conductive pattern layer 203 and the annealing temperature of the second transparent conductive pattern layer 207 are both in a range from 200° C. to 260° C. By the aforementioned relationship and value design of the annealing temperature, the first transparent electrode layer 201 and the second transparent electrode layer 205 can have larger grain sizes and higher transmittances than the first transparent conductive pattern layer 203 and the second transparent conductive pattern layer 207, respectively, and the first transparent conductive pattern layer 203 and the second transparent conductive pattern layer 207 can have lower sheet resistances than the first transparent electrode layer 201 and the second transparent electrode layer 205, respectively. Furthermore, by annealing the first transparent conductive pattern layer 203 and the second transparent conductive pattern layer 207 formed on the first metal pattern layer 202 and the second metal pattern layer 206 at a relatively low temperature, the first metal pattern layer 202 and the second metal pattern layer 206 can be prevented from being severely oxidized to cause abnormal resistance and affect display quality.
Referring to
Similarly, the second transparent electrode layer 205 is continuously formed on the second substrate 204. The second metal pattern layer 206 is continuously formed on the second transparent electrode layer 205, and includes the third openings O3 exposing the second transparent electrode layer 205. The second transparent conductive pattern layer 207 is continuously formed on the second metal pattern layer 206, and includes the fourth openings O4 exposing the second transparent electrode layer 205. That is, the top view patterns of the second metal pattern layer 206 and the second transparent conductive pattern layer 207 are grid patterns, respectively. The shapes of the grid patterns of the second metal pattern layer 206 and the second transparent conductive pattern layer 207 may be parallelogram, circle, ellipse, triangle or other appropriate shapes, and the shapes of the grid patterns of the second metal pattern layer 206 and the second transparent conductive pattern layer 207 may be the same or different. In addition, the shapes of the grid patterns of the first metal pattern layer 202, the first transparent conductive pattern layer 203, the second metal pattern layer 206, and the second transparent conductive pattern layer 207 may be the same or different.
As shown in
Similarly, the orthographic projection of the second metal pattern layer 206 on the second substrate 204 is located within the orthographic projection of the second transparent conductive pattern layer 207 on the second substrate 204. In addition, the orthographic projection of the fourth opening O4 of the second transparent conductive pattern layer 207 on the second substrate 204 is located within the orthographic projection of the third opening O3 of the second metal pattern layer 206 on the second substrate 204.
Referring to
As shown in
Similarly, the second metal pattern layer 206 includes a second oxide layer in contact with the second transparent conductive pattern layer 207 and a second conductive layer located between the second transparent electrode layer 205 and the second oxide layer. The thickness of the second oxide layer is less than 5 nm.
Referring to
Similarly, the second transparent electrode layer 205 may include multiple transparent electrodes separated from each other, and the second metal pattern layer 206 and the second transparent conductive pattern layer 207 may include multiple grid patterns separated from each other, and this embodiment may further include a second wiring layer disposed on the second substrate 204 and a second insulating layer disposed on the second wiring layer. The second wiring layer may include a grid part and a connection part connecting the grid part, where the grid part includes multiple sixth openings exposing the second transparent electrode layer 205, that is, the top view pattern of the grid part is a grid pattern. In this embodiment, the shape of the grid pattern of the grid part is a square, but is not limited thereto. In other embodiments, the shape of the grid pattern of the grid part may be other types of parallelograms, circle, ellipse, triangle, or other appropriate shapes.
As shown in
Similarly, the orthographic projection of the grid part of the second wiring layer on the second substrate 204 is located within the orthographic projection of the second metal pattern layer 206 on the second substrate 204. In some embodiments, the shape of the grid pattern of the grid part of the second wiring layer is the same as the shape of the grid pattern of the second metal pattern layer 206. In some embodiments, the size of the grid pattern of the grid part of the second wiring layer is the same as the size of the grid pattern of the second metal pattern layer 206.
Referring to
Similarly, the second wiring layer is disposed on the second substrate 204, the second insulating layer is disposed on the second wiring layer, the second transparent electrode layer 205 is disposed on the second insulating layer, the second metal pattern layer 206 is electrically connected to the second wiring layer via a through hole extending through the second transparent electrode layer 205 and the second insulating layer, and the second transparent conductive pattern layer 207 is disposed on the second metal pattern layer 206 and covers the upper surface and the side surface of the second metal pattern layer 206. In the normal line of the second substrate 204, the second metal pattern layer 206 overlaps with the second wiring layer.
In some embodiments, the materials of the first wiring layer 208 and the second wiring layer may include a metal with good electrical conductivity, such as aluminum, molybdenum, titanium, copper, silver, and other metals. In addition, the material of the first insulating layer 209 and the second insulating layer may be an inorganic insulating material, an organic insulating material, or a combination thereof. The inorganic insulating material may be silicon oxide, silicon nitride, silicon oxynitride, etc., and the organic insulating material may be polymethylmethacrylate (PMMA), siloxane, polyimide (PI), epoxy, or other suitable materials. In some embodiments, the first wiring layer 208, the first insulating layer 209, the second wiring layer and the second insulating layer may be formed by a deposition process, an inkjet process, a printing process, a coating process, a photolithography process and/or other appropriate processes.
In summary, in at least one embodiment of the display device of the present disclosure, the display device includes the switch panel disposed under the display panel. The switch panel includes the transparent electrode layer, the metal pattern layer, and the transparent conductive pattern layer sequentially disposed on the substrate. The grain size of the transparent conductive pattern is less than the grain size of the transparent electrode layer. By disposing the metal pattern layer and the transparent conductive pattern layer, the resistance is reduced to increase the switching speed between the light transmitting mode and the opaque mode. Furthermore, through the metal pattern layer and the transparent conductive pattern layer with openings in to expose the transparent electrode layer, the transmittance of the light transmitting mode can be maintained or increased, thereby improving the display quality of the display device.
Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 112145013 | Nov 2023 | TW | national |
