Patent Grant
12142229
The present application claims priority to Korean Patent Application No. 10-2021-0193166, filed on Dec. 30, 2021, which is herein incorporated by reference in its entirety.
The disclosure relates to a display device.
An organic light-emitting diode (hereinafter, referred to as a light-emitting diode) of an organic light-emitting display device is self-emissive and does not need a separate light source, thereby decreasing the thickness and weight of the display device. Further, the organic light-emitting display device exhibits high-quality characteristics such as low power consumption, high brightness, fast response time, etc.
In general, the light emitting diode has a structure in which an anode, a bank surrounding an edge region of the anode, a light emitting layer formed on the anode within the bank, and a cathode covering the light emitting layer and the bank are stacked. Such a light emitting diode emits light with required brightness as a driving transistor controls the amount of current flowing in the light emitting diode.
One of the technical benefits of the disclosure is to relieve the difference in brightness on a display panel caused by fluctuation in a high-potential driving voltage, thereby improving display quality.
Further, one of the technical benefits of the disclosure is to prevent distortion of color coordinates when the high-potential driving voltage is compensated with respect to pixels of different colors.
According to at least one embodiment, a display device includes: a display panel on which a plurality of pixels of different colors are arrayed; a power supply configured to supply a high-potential driving voltage to the display panel; and a data driver configured to calculate an average picture level (APL) of input image data, and generate a data voltage based on a compensation value for compensating for a voltage drop of the high-potential driving voltage based on the calculated APL. The compensation value may be independently set for each of the colors.
The data driver may include: an APL calculator configured to calculate the APL; a memory configured to store the compensation value based on the APL; and a compensator configured to generate the data voltage based on the compensation value corresponding to the calculated APL.
The compensator may be independently provided corresponding to each of the colors.
The data driver may include: a shift register configured to output a sampling signal in response to a data driving control signal output from a timing controller; a latch configured to sample the image data into a digital data signal in response to the sampling signal; a reference voltage generator configured to generate a reference voltage; a gamma voltage generator configured to generate gamma voltages based on the reference voltage; and a digital-analog converter (DAC) configured to convert the digital data signal into an analog data signal based on the gamma voltages, and output the analog data signal as the data voltage.
The data driver may further include a compensation circuit configured to output the compensation value corresponding to the calculated APL, and the gamma voltage generator may be configured to receive a reference voltage to or from which the compensation value is added or subtracted.
The compensation circuit and the reference voltage generator may be independently provided corresponding to each of the colors.
The gamma voltages may be provided as different sets of gamma voltages to the pixels of different colors, respectively.
The data driver may be configured to set the compensation value for decreasing the data voltage when the calculated APL increases and set the compensation value for increasing the data voltage when the calculated APL decreases.
The compensation circuit may be configured to perform adding compensation for adding the compensation value to the reference voltage when the APL increases, and subtracting compensation for subtracting the compensation value from the reference voltage when the APL decreases.
The compensation value may be previously stored in a memory of the display device, or generated by detecting a fluctuation of the high-potential driving voltage by the display device, or received from outside of the display device.
According to some embodiments, a compensation method for a display device having a plurality of pixels of different colors comprises: calculating an average picture level (APL) of input image data; generating a data voltage based on a compensation value for compensating for a voltage drop of a high-potential driving voltage based on the calculated APL, wherein the compensation value is independently set for each of the colors.
Below, embodiments are described with reference to the accompanying drawings. In this specification, when one element (or region, layer, portion) is referred to as being ‘on’, ‘connected to,’ or ‘coupled to’ another element, it can be directly disposed/connected/coupled on/to the one element, or an intervening third element may also be present.
Like reference numerals refer to like elements throughout. Also, in the accompanying drawings, the thickness, ratio, and dimensions of elements are exaggerated for clarity of illustration. The term “and/or” includes any and all combinations of one or more of the associated listed elements.
Although the terms such as ‘first’ and ‘second’ are used herein to describe various elements, these elements should not be limited by these terms. The terms are only used to distinguish one element from other elements. For example, a first element referred to as a first element in one embodiment can be referred to as a second element in another embodiment without departing from the scope of the appended claims. The terms of a singular form may include plural forms unless otherwise meant contextually.
Also, “under,” “below,” “above,” “upper,” and the like are used for explaining relation association of elements illustrated in the accompanying drawings. The terms may be a relative concept and described based on directions expressed in the accompanying drawings.
The term ‘include’ or ‘comprise’ specifies a property, a fixed number, a step, an operation, an element, a component or a combination thereof, but does not exclude other properties, fixed numbers, steps, operations, elements, components or combinations thereof.
Referring to
The timing controller 10 may receive an image signal RGB and a control signal CS from the outside. The image signal RGB may include a plurality of grayscale data. The control signal CS may, for example, have a horizontal sync signal, a vertical sync signal, and a clock signal.
The timing controller 10 may process the image signal RGB and the control signal CS to be suitable for operating conditions of the display panel 50, thereby generating and outputting image data RGB′, a scan driving control signal CONT1, a data driving control signal CONT2, and a power supply control signal CONT3.
The gate driver 20 may generate gate signals based on the gate driving control signal CONT1 output from the timing controller 10. The gate driver 20 may provide the generated gate signals to pixels PX through a plurality of gate lines GL. When the gate signals are supplied to the gate lines GL in sequence, the pixels PX may be selected in units of horizontal lines.
The data driver 30 may generate data signals based on the image data RGB′ and data driving control signal CONT2 output from the timing controller 10. The data driver 30 may provide the generated data signals to the selected pixels PX through the plurality of data lines DL, when the pixels PX are selected by the scan signals in units of horizontal lines.
The power supply 40 may generate driving voltages ELVDD, ELVSS to be supplied to the display panel 50 based on the power supply control signal CONT3. The power supply 40 may supply the generated driving voltages to the pixels PX through the corresponding power lines PL1 and PL2.
On the display panel 50, a plurality of pixels PX (or sub-pixels) are arrayed. The pixels PX may, for example, be arrayed on the display panel 50 in the form of a matrix. The pixels PX are controlled to emit light with required brightness based on the gate signals and the data signals supplied through the gate lines GL and the data lines DL.
Each pixel PX may emit light in red, green, and blue. According to an embodiment, a set of pixels PX that emit light in red, green, and blue may be grouped into one unit pixel.
The timing controller 10, the gate driver 20, the data driver 30, and the power supply 40 may be respectively configured as individual integrated circuits (IC), or at least some of them may be integrated into an IC. For example, at least one of the data driver 30 and the power supply 40 may be integrated into the timing controller 10.
Further, the gate driver 20 is shown as an individual element separated from the display panel 50 in
Referring to
The switching transistor ST includes a first electrode connected to the data line DL, and a second electrode connected to a first node N1. The switching transistor ST includes a gate electrode connected to the gate line GL. The switching transistor ST is turned on when the gate-on level gate signal is applied to the gate line, thereby transmitting the data signal applied to the data line to the first node N1.
The storage capacitor Cst is connected between the anode of the light emitting diode LD and the first node N1. The storage capacitor Cst may be configured to store voltage corresponding to the difference between a voltage applied to the first node N1 and voltage applied to the anode of the light-emitting diode LD.
The driving transistor DT includes a first electrode receiving a high-potential driving voltage ELVDD, and a second electrode connected to the anode of the light-emitting diode LD. The driving transistor DT includes a gate electrode connected to the first node N1. The driving transistor DT is turned on when voltage having the gate-on level is applied through the first node N1, thereby controlling the amount of driving current flowing in the light emitting diode LD based on the voltage supplied to the gate electrode.
The light emitting diode LD emits light corresponding to the driving current. The light emitting diode LD may emit light in one of red, green, blue and white. The light emitting diode LD may include an organic light emitting diode (OLED), or a micro- to nano-sized inorganic light emitting diode, but the disclosure is not limited to these embodiments.
In some cases, the structure of the pixel PX is not limited to that shown in
Referring to
The high-potential driving voltage ELVDD applied to the display panel 50 may be dropped by a load of the display panel 50. In this case, the load of the display panel 50 may be varied depending on an average picture level (APL) of the image data RGB′. When the APL of an input picture is high, electric current consumed by the pixels PX included in the display panel 50 increases, thereby increasing a voltage drop of the high-potential driving voltage ELVDD. On the other hand, when the APL of an input picture is low, electric current consumed by the pixels PX decreases, thereby decreasing a voltage drop of the high-potential driving voltage ELVDD. Change in the voltage drop of the high-potential driving voltage ELVDD causes the brightness of the APL to be decreased or increased, thereby leading to poor picture quality.
According to an embodiment, the display device 1 may be configured to compensate for such a voltage drop (IR drop) of the high-potential driving voltage ELVDD. For example, the data driver 30 may calculate the APL of the input image data RGB′, and provide the data voltage Vdata compensated based on the calculated APL to the display panel 50. The APL refers to the average brightness of the image data RGB′, which may, for example, be defined as the average brightness of the brightest color in the image data RGB′ of one frame.
The data driver 30 may convert the input image data RGB′ into the data voltage Vdata, and transmit the data voltage Vdata, which is compensated based on the APL, to the display panel 50. To this end, the data driver 30 may include an APL calculator 31, a memory 32, and a compensator 33.
The APL calculator 31 may calculate the APL of the input image data RGB′ in units of frames.
The memory 32 may be configured to store a compensation value of the data voltage Vdata for the APL. The compensation value may be set based on a fluctuation simulation of the high-potential driving voltage ELVDD according to change in the APL. For example, when the calculated APL increases, the voltage drop of the high-potential driving voltage ELVDD may increase, and thus the data voltage Vdata may be compensated to decrease to prevent the brightness from relatively increasing. On the other hand, when the calculated APL decreases, the voltage drop of the high-potential driving voltage ELVDD may decrease, and thus the data voltage Vdata may be compensated to increase to prevent the brightness from relatively decreasing.
Such a compensation value refers to a compensation voltage given as a high-potential driving voltage ELVDD, which may, for example, include values added to or subtracted from a reference voltage to generate the data voltage Vdata. The compensation values may, for example, be stored in the form of a lookup table (LUT) in the memory 32.
The compensation value may previously be stored in the memory 32 when the display device 1 is manufactured. Alternatively, the compensation value may be generated by detecting the fluctuation of the high-potential driving voltage ELVDD by the display device 1 itself or may be received in the display device 1 from the outside while the display device 1 is operating.
The compensator 33 may load the compensation value corresponding to the APL from the memory 32, and generate the data voltage Vdata compensated based on the loaded compensation value. The compensator 33 may transmit the compensated data voltage Vdata to the display panel 50.
The foregoing embodiments show that the data voltage compensation may be performed in units of frames in real-time, but the disclosure is not limited to these embodiments. In other words, the data voltage compensation may be performed in units of a predetermined number of frames or may be performed when a preset compensation condition is satisfied. Further, the data voltage compensation may be based on the APL of a single frame or based on the APL of a plurality of frames.
According to an embodiment, the compensation value for the data voltage Vdata may be based on the APL of the image data RGB′, and may be equally applied to the display panel 50 on which the pixels PX are arrayed.
As described above with reference to
Therefore, the pixels R, G and B emitting light in different colors are different in the voltage drop of the high-potential driving voltage ELVDD. Consequently, as shown in
As described above with reference to
However, as described above, the pixels R, G and, B of different colors are different in the voltage drop. Therefore, when the same compensation value is applied to the pixels R, G and B of different colors, there may be a problem that brightness and color coordinates are significantly distorted according to the APL as shown in
Below, a detailed configuration of the data driver 30 for solving this problem will be described.
Referring to
The data driver 30′ may convert the input image data RGB′ into the data voltage Vdata, and transmit the data voltage Vdata, which is compensated based on the APL, to the display panel 50. To this end, the data driver 30′ may include an APL calculator 31′, a memory 32′, and a compensator 33′.
In this embodiment, the compensator 33′ is provided with regard to each of the pixels R, G and B emitting light in different colors. In other words, the compensator 33′ includes a first compensator 33′R to compensate for the data voltage Vdata of the red pixel R, a second compensator 33′G to compensate for the data voltage Vdata of the green pixel G, and a third compensator 33′B to compensate for the data voltage Vdata of the blue pixel B.
The first to third compensators 33′R to 33′B may have the same circuit structure. Below, a detailed structure of the data driver 30′, including the first to third compensators 33′R to 33′B will be described.
Referring to
The reference voltage generator 360 generates and outputs the reference voltage based on a voltage supplied from the outside. According to an embodiment, the reference voltage generator 360 may generate and output the reference voltage considering the compensation value set based on the APL of the input image data RGB′.
In this case, the compensation values may be differently given to the data driver 30′ according to the corresponding pixels R, G and B. For example, the compensation values may be individually set with regard to the pixels R, G, and B of different colors, and the reference voltages generated reflecting the compensation values may also be individually provided with respect to such pixels R, G and B.
The reference voltage generator 360 may be provided outside the data driver 30′ as shown in
The data driver 30′ may further include a shift register 310, a latch 320, a digital-analog converter (DAC) 340, and an output buffer 350.
The data driving control signal CONT2 provided by the timing controller 10 includes a source start pulse (SSP) signal, a source sampling clock (SSC) signal, a source output enables (SOE) signal, etc. The SSP signal controls a data sampling start point of the data driver 30′. The SSC signal is a clock signal for controlling a data sampling operation in the data driver 30′ with respect to a rising or falling edge. The SOE signal controls the output of the data driver 30′.
The shift register 310 outputs a sampling signal SAM in response to the SSP and SSC signals output from the timing controller 10. The latch 320 sequentially samples digital data signal DDATA corresponding to the image data RGB′ in response to the sampling signal SAM output from the shift register 310, and simultaneously outputs the digital data signal DDATA of one line sampled corresponding to the SOE signal.
The DAC 340 converts the digital data signal DDATA of one line into an analog data signal ADATA corresponding to the first to nth gamma voltages GMA1 to GMAn output from the gamma voltage generator 330. The output buffer 350 amplifies (or amplifies and compensates for) the analog data signal ADATA output from the DAC 340, and outputs it as the data voltage Vdata to each data line.
Referring to
The data driver 30′ may include the reference voltage generator 360 to generate the reference voltage VREF by reflecting the compensation value provided from the compensation circuit 361, and the gamma voltage generator 330 including a resistor string portion for dividing voltage based on the reference voltage VREF to generate the gamma voltages GMA1 to GMAn based on the divided voltages.
In the reference voltage generator 360, the first reference voltage terminal RV1 is connected to a low gamma voltage terminal BRV1 (or a low grayscale gamma voltage terminal) of the gamma voltage generator 330, and the nth reference voltage terminal RVn is connected to a high gamma voltage terminal BRVn (or a high grayscale gamma voltage terminal) of the gamma voltage generator 330.
The compensation circuit 361 is illustrated as a separate block. Alternatively, the compensation circuit 361 may be provided as a separate circuit or element so that voltage can be indirectly added to or subtracted from the reference voltages VREF output from the first reference voltage terminal RV1 and the nth reference voltage terminal RVn of the reference voltage generator 360.
According to some embodiments, when the APL of the image data RGB′ is increased compared to a reference value, the compensation circuit 361 is configured to perform compensation (adding compensation) of adding a compensation value to the reference voltage VREF. On the other hand, when the APL is decreased compared to the reference value, the compensation circuit 361 is configured to perform compensation (subtracting compensation) by subtracting a compensation value from the reference voltage VREF.
The compensation circuit 361 makes the low gamma voltage terminal BRV1 and the high gamma voltage terminal BR Vn of the gamma voltage generator 330 do not directly receive the reference voltage VREF output from the reference voltage generator 360 but receive the reference voltage subjected to the addition or subtracting compensation.
For example, the low gamma voltage terminal BRV1 receives a compensation voltage AVREF1 (hereinafter, referred to as a lower reference voltage) of a low reference voltage VREF1±the high-potential driving voltage ELVDD, and the high gamma voltage terminal BRVn receives a compensation voltage AVREFn (hereinafter, referred to as a higher reference voltage) of a high reference voltage VREFn±the high-potential driving voltage ELVDD.
The gamma voltage generator 330 may include a plurality of resistor strings RS1, RS2 and RS3.
The first resistor string RS1 generates some gamma reference voltages GM1 and GM9 by dividing the voltage between the lower reference voltage VREF1+AVREF1 and the upper reference voltage VREFn+AVREFn. Some selected gamma reference voltages GM1 and GM9 may be output through a buffer BUF.
Some gamma reference voltages GM1 and GM9 are distributed through the second resistor string RS2. The second resistor string RS2 may select the other gamma reference voltages GM2 to GM8 from the distributed voltages, and output the selected gamma reference voltages GM2 to GM8 through the buffer BUF.
The third resistor string RS3 may distribute the gamma reference voltages GM1 to GM9 and output the gamma voltages GMA1 to GMAn corresponding to the whole grayscales. The generated gamma voltages GMA1 to GMAn may be provided to the DAC 340 and used for generating the data voltage Vdata.
In some of the foregoing embodiments, the compensation circuit 361 and the reference voltage generator 360 may be provided for each of the pixels R, G and B of different colors. In other words, the compensation values and the reference voltages reflecting these compensation values may be individually provided corresponding to the pixels R, G and B of different colors. Consequently, different sets of gamma voltages are provided to the pixels R, G and B of different colors, and the data voltages Vdata compensated as a result are generated independently of one another.
As described above with reference to
Such compensation values are set adaptively to the pixels R, G, and B which are different in the voltage drop of the driving voltage ELVDD, and therefore the color coordinates based on the APL are maintained without being distorted with respect to the pixels R, G and B after the compensation as shown in
According to some embodiments, the display device compensates for the voltage drop of the high-potential driving voltage, and relieves the difference in brightness among the pixels, thereby improving display quality.
According to some embodiments, the display device solves the problem that the color coordinates are distorted when the voltage drop of the high-potential driving voltage is compensated.
It is apparent to a person having ordinary knowledge in the art, to which the disclosure pertains, that the disclosure can be embodied in other specific forms without changing the technical concept or essential features. Accordingly, it should be understood that above-described embodiments are for illustrative purpose only but not in any way for restriction thereto.
The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.
These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2021-0193166 | Dec 2021 | KR | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 9361823 | Takahama et al. | Jun 2016 | B2 |
| 20080170014 | Jung | Jul 2008 | A1 |
| 20190147802 | Li | May 2019 | A1 |
| 20210193047 | Kwon | Jun 2021 | A1 |
| 20210201801 | Lee | Jul 2021 | A1 |
| Number | Date | Country |
|---|---|---|
| 2003280590 | Oct 2003 | JP |
| WO 2013136998 | Sep 2013 | WO |
| Number | Date | Country | |
|---|---|---|---|
| 20230215384 A1 | Jul 2023 | US |
