Display systems with compensation for line propagation delay

Abstract

A method for characterizing and eliminating the effect of propagation delay on data and monitor lines of AMOLED panels is introduced. A similar technique may be utilized to cancel the effect of incomplete settling of select lines that control the write and read switches of pixels on a row.

Description

FIELD OF THE INVENTION

The present disclosure generally relates to circuits for use in displays, and methods of driving, calibrating, and programming displays, particularly displays such as active matrix organic light emitting diode displays.

BACKGROUND

Displays can be created from an array of light emitting devices each controlled by individual circuits (i.e., pixel circuits) having transistors for selectively controlling the circuits to be programmed with display information and to emit light according to the display information. Thin film transistors (“TFTs”) fabricated on a substrate can be incorporated into such displays. TFTs tend to demonstrate non-uniform behavior across display panels and over time as the displays age. Compensation techniques can be applied to such displays to achieve image uniformity across the displays and to account for degradation in the displays as the displays age.

Some schemes for providing compensation to displays to account for variations across the display panel and over time utilize monitoring systems to measure time dependent parameters associated with the aging (i.e., degradation) of the pixel circuits. The measured information can then be used to inform subsequent programming of the pixel circuits so as to ensure that any measured degradation is accounted for by adjustments made to the programming. Such monitored pixel circuits may require the use of additional transistors and/or lines to selectively couple the pixel circuits to the monitoring systems and provide for reading out information. The incorporation of additional transistors and/or lines may undesirably decrease pixel-pitch (i.e., “pixel density”).

SUMMARY

Aspects of the present disclosure provide pixel circuits suitable for use in a monitored display configured to provide compensation for pixel aging. Pixel circuit configurations disclosed herein allow for a monitor to access nodes of the pixel circuit via a monitoring switch transistor such that the monitor can measure currents and/or voltages indicative of an amount of degradation of the pixel circuit. Aspects of the present disclosure further provide pixel circuit configurations which allow for programming a pixel independent of a resistance of a switching transistor. Pixel circuit configurations disclosed herein include transistors for isolating a storage capacitor within the pixel circuit from a driving transistor such that the charge on the storage capacitor is not affected by current through the driving transistor during a programming operation.

The foregoing and additional aspects and embodiments of the present disclosure will be apparent to those of ordinary skill in the art in view of the detailed description of various embodiments and/or aspects, which is made with reference to the drawings, a brief description of which is provided next.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other advantages of the invention will become apparent upon reading the following detailed description and upon reference to the drawings.

FIG. 1 illustrates an exemplary configuration of a system for monitoring degradation in a pixel and providing compensation therefore according to the present disclosure.

FIG. 2 is a circuit diagram of an RC model of data and monitor lines in a display system.

FIG. 3A is an illustrative plot of voltage versus time for programming a pixel showing the settling effects for the pixel in the Nth row in FIG. 2.

FIG. 3B is an illustrative plot of voltage versus time for programming a pixel showing the settling effects for the pixel in the ith row in FIG. 2.

FIG. 3C is an illustrative plot of voltage versus time for programming a pixel showing the settling effects for the pixel in the 1st row in FIG. 2.

FIG. 4A is an illustrative plot of current versus time for reading a current from a pixel programmed with the operating programming duration influenced by settling effects.

FIG. 4B is an illustrative plot of current versus time for reading a current from a pixel programmed with an extended programming duration not influenced by settling effects

FIG. 5 illustrates accumulation of errors due to line propagation during programming and readout and also due to errors from pixel degradation.

FIG. 6 illustrates an operation sequence where startup calibration data is utilized to characterize the monitor line effects.

FIG. 7 illustrates an operation sequence where real-time measurements are utilized to provide calibration of pixel aging.

FIG. 8 illustrates isolation of the initial errors in the programming path early in the operating lifetime of a display.

FIG. 9 provides an exemplary graph of read out time durations required to substantially avoid settling effects for each row in a display.

FIG. 10 is a flowchart of an embodiment for extracting the propagation delay effects on the monitoring line.

FIG. 11 is a flowchart of an embodiment for extracting the propagation delay effects on the signal line.

While the present disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and will be described in detail herein. It should be understood, however, that the disclosure is not intended to be limited to the particular forms disclosed. Rather, it is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION

FIG. 1 is a diagram of an exemplary display system 50. The display system 50 includes an address driver 8, a data driver 4, a controller 2, a memory storage 6, and display panel 20. The display panel 20 includes an array of pixels 10 arranged in rows and columns. Each of the pixels 10 is individually programmable to emit light with individually programmable luminance values. The controller 2 receives digital data indicative of information to be displayed on the display panel 20. The controller 2 sends signals 32 to the data driver 4 and scheduling signals 34 to the address driver 8 to drive the pixels 10 in the display panel 20 to display the information indicated. The plurality of pixels 10 associated with the display panel 20 thus comprise a display array (“display screen”) adapted to dynamically display information according to the input digital data received by the controller 2. The display screen can display, for example, video information from a stream of video data received by the controller 2. The supply voltage 14 can provide a constant power voltage or can be an adjustable voltage supply that is controlled by signals from the controller 2. The display system 50 can also incorporate features from a current source or sink (not shown) to provide biasing currents to the pixels 10 in the display panel 20 to thereby decrease programming time for the pixels 10.

For illustrative purposes, the display system 50 in FIG. 1 is illustrated with only four pixels 10 in the display panel 20. It is understood that the display system 50 can be implemented with a display screen that includes an array of similar pixels, such as the pixels 10, and that the display screen is not limited to a particular number of rows and columns of pixels. For example, the display system 50 can be implemented with a display screen with a number of rows and columns of pixels commonly available in displays for mobile devices, monitor-based devices, and/or projection-devices.

The pixel 10 is operated by a driving circuit (“pixel circuit”) that generally includes a driving transistor 202 (shown in FIG. 2) and a light emitting device 204. Hereinafter the pixel 10 may refer to the pixel circuit. The light emitting device 204 can optionally be an organic light emitting diode, but implementations of the present disclosure apply to pixel circuits having other electroluminescence devices, including current-driven light emitting devices. The driving transistor 202 in the pixel 10 can optionally be an n-type or p-type amorphous silicon thin-film transistor, but implementations of the present disclosure are not limited to pixel circuits having a particular polarity of transistor or only to pixel circuits having thin-film transistors. The pixel circuit 10 can also include a storage capacitor 200 (shown in FIG. 2) for storing programming information and allowing the pixel circuit 10 to drive the light emitting device 204 after being addressed. Thus, the display panel 20 can be an active matrix display array.

As illustrated in FIG. 1, the pixel 10 illustrated as the top-left pixel in the display panel 20 is coupled to a select line 24j, a supply line 26j, a data line 22i, and a monitor line 28i. In an implementation, the supply voltage 14 can also provide a second supply line to the pixel 10. For example, each pixel can be coupled to a first supply line charged with Vdd and a second supply line coupled with Vss, and the pixel circuits 10 can be situated between the first and second supply lines to facilitate driving current between the two supply lines during an emission phase of the pixel circuit. The top-left pixel 10 in the display panel 20 can correspond to a pixel in the display panel in a “jth” row and “ith” column of the display panel 20. Similarly, the top-right pixel 10 in the display panel 20 represents a “jth” row and “mth” column; the bottom-left pixel 10 represents an “nth” row and “ith” column; and the bottom-right pixel 10 represents an “nth” row and “ith” column. Each of the pixels 10 is coupled to appropriate select lines (e.g., the select lines 24j and 24n), supply lines (e.g., the supply lines 26j and 26n), data lines (e.g., the data lines 22i and 22m), and monitor lines (e.g., the monitor lines 28i and 28m). It is noted that aspects of the present disclosure apply to pixels having additional connections, such as connections to additional select lines, and to pixels having fewer connections, such as pixels lacking a connection to a monitoring line.

With reference to the top-left pixel 10 shown in the display panel 20, the select line 24j is provided by the address driver 8, and can be utilized to enable, for example, a programming operation of the pixel 10 by activating a switch or transistor to allow the data line 22i to program the pixel 10. The data line 22i conveys programming information from the data driver 4 to the pixel 10. For example, the data line 22i can be utilized to apply a programming voltage or a programming current to the pixel 10 in order to program the pixel 10 to emit a desired amount of luminance. The programming voltage (or programming current) supplied by the data (or source) driver 4 via the data line 22i is a voltage (or current) appropriate to cause the pixel 10 to emit light with a desired amount of luminance according to the digital data received by the controller 2. The programming voltage (or programming current) can be applied to the pixel 10 during a programming operation of the pixel 10 so as to charge a storage device 200 within the pixel 10, such as a storage capacitor (FIG. 2), thereby enabling the pixel 10 to emit light with the desired amount of luminance during an emission operation following the programming operation. For example, the storage device 200 in the pixel 10 can be charged during a programming operation to apply a voltage to one or more of a gate or a source terminal of the driving transistor 202 during the emission operation, thereby causing the driving transistor 202 to convey the driving current through the light emitting device 204 according to the voltage stored on the storage device 200.

Generally, in the pixel 10, the driving current that is conveyed through the light emitting device 204 by the driving transistor 202 during the emission operation of the pixel 10 is a current that is supplied by the first supply line 26j and is drained to a second supply line (not shown). The first supply line 22j and the second supply line are coupled to the voltage supply 14. The first supply line 26j can provide a positive supply voltage (e.g., the voltage commonly referred to in circuit design as “Vdd”) and the second supply line can provide a negative supply voltage (e.g., the voltage commonly referred to in circuit design as “Vss”). In some embodiments, one or the other of the supply lines (e.g., the supply line 26j) are fixed at a ground voltage or at another reference voltage.

The display system 50 also includes a readout or monitoring system 12. With reference again to the top left pixel 10 in the display panel 20, the monitor line 28i connects the pixel 10 to the monitoring system 12. The monitoring system 12 can be integrated with the data driver 4, or can be a separate stand-alone system. In particular, the monitoring system 12 can optionally be implemented by monitoring the current and/or voltage of the data line 22i during a monitoring operation of the pixel 10, and the monitor line 28i can be entirely omitted. Additionally, the display system 50 can be implemented without the monitoring system 12 or the monitor line 28i. The monitor line 28i allows the monitoring system 12 to measure a current or voltage associated with the pixel 10 and thereby extract information indicative of a degradation of the pixel 10. For example, the monitoring system 12 can extract, via the monitor line 28i, a current flowing through the driving transistor 202 within the pixel 10 and thereby determine, based on the measured current and based on the voltages applied to the driving transistor 202 during the measurement, a threshold voltage of the driving transistor 202 or a shift thereof. Generally then, measuring the current through the driving transistor 202 allows for extraction of the current-voltage characteristics of the driving transistor 202. For example, by measuring the current through the drive transistor 202 (I_DS), the threshold voltage Vth and/or the parameter β can be determined according to the relation I_DS=β(V_GS−Vth)², where V_GS is the gate-source voltage applied to the driving transistor 202.

The monitoring system 12 can additionally or alternatively extract an operating voltage of the light emitting device 204 (e.g., a voltage drop across the light emitting device while the light emitting device is operating to emit light). The monitoring system 12 can then communicate the signals 32 to the controller 2 and/or the memory 6 to allow the display system 50 to store the extracted degradation information in the memory 6. During subsequent programming and/or emission operations of the pixel 10, the degradation information is retrieved from the memory 6 by the controller 2 via the memory signals 36, and the controller 2 then compensates for the extracted degradation information in subsequent programming and/or emission operations of the pixel 10 by increasing or decreasing the programming values by a compensation value. For example, once the degradation information is extracted, the programming information conveyed to the pixel 10 via the data line 22i can be appropriately adjusted during a subsequent programming operation of the pixel 10 such that the pixel 10 emits light with a desired amount of luminance that is independent of the degradation of the pixel 10. In an example, an increase in the threshold voltage of the driving transistor 202 within the pixel 10 can be compensated for by appropriately increasing the programming voltage applied to the pixel 10.

Furthermore, as discussed herein, the monitoring system 12 can additionally or alternatively extract information indicative of a voltage offset in the programming and/or monitoring readout (such as using a readout circuit 210 or monitoring system 12 shown in FIG. 2) due to propagation delay in the data line (e.g., the data lines 22i, 22m) resulting from the parasitic effects of line resistance and line capacitance during the programming and/or monitoring intervals.

According to some embodiments disclosed herein, optimum performance of Active Matrix Organic Light Emitting (AMOLED) displays is adversely affected by nonuniformity, aging, and hysteresis of both OLED and backplane devices (Amorphous, Poly-Silicon, or Metal-Oxide TFT). These adverse effects introduce both time-invariant and time-variant factors into the operation of the display that can be accounted for by characterizing the various factors and providing adjustments during the programming process. In large area applications where full-high definition (FHD) and ultra-high definition (UHD) specifications along with high refresh-rate (e.g., 120 Hz and 240 Hz) are demanded, the challenge of operating an AMOLED display is even greater. For example, reduced programming durations enhance the influence of dynamic effects on programming and display operations.

In addition, the finite conductance of very long metal (or otherwise conductive) lines through which the AMOLED pixels are accessed and programmed (e.g., the lines 22i, 28i, 22m, 28m in FIG. 1), along with the distributed parasitic capacitance coupled to the lines, introduces a fundamental limit on how fast a step function of driving signals can propagate across the panel and settle to their steady state. Generally, the voltage on such lines is changed according to a time-dependent function proportional to 1−exp(−t/RC), where R is the total effective resistance between the source of the voltage change and the point of interest and C is the total effective capacitance between the source of the voltage change and the point of interest. This fundamental limit prevents large area panels to be refreshed at higher rates if proper compensation techniques are not provided. On the other hand, while one can use longer refresh time for factory calibration to eliminate the effect of imperfect settling, the calibration time will increase significantly resulting in longer Takt time or cycle time (i.e., less efficient production).

A method for characterizing and eliminating (or at least suppressing) the effect of propagation delay on data lines 22 and monitor lines 28 of AMOLED panels is disclosed herein. A similar technique can be utilized to cancel the effect of incomplete settling of select lines (e.g., the lines 24j, 24n in FIG. 1) that control the write and read switches of pixels on a row.

FIG. 2 is a circuit diagram of an RC model of data and monitor lines in a display system. A single column of a display panel is shown for simplicity. The data line (labeled “Data Line”) can be equivalent to any of the data lines 22i, 22m in FIG. 1. The monitor line (labeled “Monitor Line”) can be equivalent to any of the monitor lines 28i, 28m in FIG. 1. Here the panel has an integer number, N, rows where N is 1080 in a FHD or 2160 in a UHD panel, or another number corresponding to the number of rows in the display panel 20 of FIG. 1. The Data and Monitor lines are modeled with N cascaded RC elements. Each node of the RC network is connected to a pixel circuit as shown in FIG. 2. In a typical design the lumped sum of R_P and C_P are close to 10 kΩ and 500 pF, respectively. The settling time required for 10-bit accuracy (e.g., such as to achieve 0.1% error) for such a panel can be close to 15 μS, whereas the row time (e.g., the time interval available for programming a single row between successive frames) in FHD and UHD panels running at 120 Hz are roughly 8 μS and 4 μS, respectively.

The required settling time for each row is proportional to its physical distance from the data or source driver 4 as shown in FIG. 2. In other words, the farther away a pixel 10 is physically located from the source driver 4, the longer it takes for the drive signal to propagate and settle on the corresponding row of the pixel 100. Accordingly, row N has the largest settling time constant, whereas row 1 (which is physically closest to the source driver 4) has the fastest. This effect is shown in the examples plotted in FIGS. 3A-3C, which are discussed next. During programming for a particular row, a write transistor 208 (e.g., the transistors 208 in FIG. 2 whose gates are connected to the “WR” line) in that row is turned on so as to connect the respective capacitor 200 of the pixel circuit 10 to the data line 22.

FIG. 3A is an illustrative plot 300 of voltage versus time for programming a pixel 10 showing the settling effects for the pixel in the Nth row in FIG. 2. FIG. 3B is an illustrative plot 302 of voltage versus time for programming a pixel 10 showing the settling effects for the pixel in the ith row in FIG. 2. FIG. 3C is an illustrative plot 304 of voltage versus time for programming a pixel 10 showing the settling effects for the pixel in the 1st row in FIG. 2. In each of FIGS. 3A-3C, a programming voltage V_P is applied on the data line 22, while the respective pixel circuits 10 are selected for programming (e.g., by activating the respective “WR” lines for the Nth, ith, and 1st row circuits) and are charged according to the time-dependent parameter 1−exp(−t/RC), where RC is the product of the total effective resistance and capacitance at each pixel circuit 10. Due to the difference in the total effective resistance and capacitance at different points on the data line 22, the 1^st row charges the most rapidly, whereas the Nth row charges the slowest. Thus, at the end of the programming duration (“t_prog”) the Nth pixel reaches a value V_P−ΔV_DATA(N), while the ith row reaches a value V_P−ΔV_DATA(i), and the first row reaches a value V_P−ΔV_DATA(1). As shown in FIGS. 3A-3C, ΔV_DATA(1) is generally a smaller value than ΔV_DATA(N). FIGS. 3A-3C also illustrate the settlement time t_settle, which is a time to achieve a voltage on the storage capacitor 200 that is at or near the programmed voltage.

However, the corresponding time constant (e.g., RC value) of each row is not a linear function of the row number (row number is a linear representation for row distance from the source driver 4). Given this phenomenon, variation of fabrication process, which randomly affects R_P and C_P, along with nonuniformity of the OLED (e.g., the light emitting devices 204) and the drive TFT 202, make it practically impossible to predict the accurate behavior of the data lines 22 and the monitor lines 28.

Thus, propagation delay on the data line 22 introduces an error to the desired voltage level that the storage device 200 in the pixel circuit 10 is programmed to. On the monitor line 28, however, the error is introduced to the current level of the TFT 202 or OLED 204 that is detected by the readout circuit 210 (e.g., such as in the monitoring system 12 of FIG. 1). Note that the readout circuit 210 can be on the same or opposite end of the source driver 4 side of the panel 50.

FIG. 4A is an illustrative plot 400 of current versus time for reading a current using the readout circuit 210 from a pixel 10 programmed with the operating programming duration (timing budget) influenced by settling effects (e.g., the duration t_prog). The value of I_MON is the current measured via the monitor line 28 (such as extracted via a current comparator that extracts the monitored current based on a comparison between the monitored current and a reference current, for example). Furthermore, in some embodiments, the monitor line 28 is employed to measure a voltage from the pixel circuit 10, such as the OLED 204 operation voltage, in which case the measured value can be V_MON, although the functional forms of FIGS. 4A and 4B extend to situations where voltages instead of currents are measured. FIG. 4A thus illustrates that the information extracted via the monitoring system 12 when the pixel circuit 10 is programmed during an interval with duration t_prog and measured during an interval with duration t_meas is offset from the ideal monitored value. The ideal monitored value is the value predicted in the absence of line parasitics, and where pixel circuits 10 have no non-uniformities, degradation effects, hysteresis, etc. The amount of the offsets are indicated in FIG. 4A by ΔI_DATA(i), ΔI_pixel(i), and ΔI_MON(i). The value of ΔI_DATA(i) corresponds to the value of ΔV_DATA(i) due to the parasitic effects of the data line 22 discussed in connection with FIGS. 3A-3C. The value of I_MON(i) is the corresponding offset in the monitored current due to the finite line capacitance C and resistance R that causes the current level on the monitor line 28 to adjust over time before settling at a steady value, such as occurs after the duration t_settle. However, due to timing budgets of enhanced resolution displays, t_meas is generally less than t_settle, and therefore parasitic effects can influence the monitoring operation as well the programming operation. In addition, the value of I_MON(i) is influenced by the degradation and/or non-uniformity of the pixel circuit in the ith row (e.g., due to threshold voltage or mobility variations, temperature sensitivity, hysteresis, manufacturing effects, etc.), which is indicated by the ΔI_pixel(i). Thus, the effect of the propagation delay on the monitoring line can be extracted by comparing the value of I_MON(i) after the time t_meas with the value of I_MON(i) after the time t_settle, and thereby determine the value of ΔI_MON(i).

FIG. 4B is an illustrative plot 402 of current versus time for reading a current from a pixel 10 programmed with an extended programming duration (longer than t_meas) sufficient to avoid settling effects, such as the time t_settle shown in FIG. 3B. In FIG. 4B, the pixel is programmed during an interval with duration t_settle such that the ΔI_DATA(i) factor is substantially eliminated from the factors influencing the monitored voltage I_MON(i). Comparing the value of I_MON(i) while the pixel is programmed with duration t_prog (as in FIG. 4A) with the value of I_MON(i) while the pixel is programmed with duration t_settle thus allows for determination of the value ΔI_DATA(i). Thus, aspects of the present disclosure provide for extracting non-uniformities and/or degradations of pixels 10 in a display 50 while accounting for parasitic effects in the data 22 and/or monitor line 28 that otherwise interfere with measurements of the pixel properties, such as by extending the programming timing budget to avoid propagation delay effects.

FIG. 5 illustrates accumulation of errors due to line propagation during programming and readout and also due to errors from pixel degradation. FIG. 5 illustrates a sequence 500 of errors introduced along the signal path between programming through the data line 22 and readout of a pixel 10 through a monitor line 28. The source driver provides the desired signal level to the data line 22 to program a pixel 10 (502). Due to the limited available row-time during a program signal path 512, the voltage signal from the data line 22 does not completely settle at the pixel end (504). Consequently, the signal level that is sampled on storage device 200 (C_S) of the pixel 10 of interest is deviated from its nominal value. The pixel 10 itself introduces an error to the signal path 514 due to aging and random process variations of pixel devices 202, 204 (506). When the pixel 10 is accessed for readout through the monitor line 28, the delay of monitor line 28 within a row time also introduces an error to the extracted data (508). Thus, the accumulation of errors shown in FIG. 5 corresponds to the readout level at time t_meas shown in FIG. 4A (510).

If the allocated time for readout is stretched or extended (e.g., to the duration t_settle), the amplitude of error can be detected by comparing the readout signal level (e.g., extracted from the readout circuit 210) to the signal level that is detected within the duration of a row time (e.g., the duration t_prog). The error introduced by the data line 22 propagation delay can be detected indirectly by stretching or extending the programming timing budget (e.g., to the duration t_settle) and observing the effect in the readout signal level (such as, for example, the scheme discussed in connection with FIG. 4B) using the readout circuit 210.

FIG. 6 illustrates an operation sequence 600 where startup calibration data is utilized to characterize the monitor line 28 effects (602). To calibrate for the monitor line 28 delay effect, such delay can be extracted as follows. Few (but not necessarily all) pixels 10 at different positions in the columns are measured with a long enough time to avoid the settling issue referred to above (e.g., t_settle). Then, the currents drawn by those pixels 10 are measured (calibrated) within the required timing. The comparison of the two values for each pixel 10 provides the delay element associated with the monitor line 28 for the pixel 10 in that row. Using the extracted delays, the delay element is calculated for each pixel 10 in the column. Other columns in the display 50 can also be measured similarly.

The extracted delay shows itself as a gain in the pixel current detected by the measurement unit. To correct for this effect, the reference current can be scaled or the extracted calibration value for the pixel can be scaled accordingly, to account for the gain factor.

In FIG. 6, the delay caused by the monitor line 28 can be extracted as follows. The programming data put by the source driver 4 onto the data line 22 is calibrated for data line error and pixel non-uniformity (602). During programming of the pixels 10, the data line 22 introduces an error, e.g., ΔI_DATA shown in FIG. 4A) (604), and the random pixel non-uniformity discussed above contributes an error as well, e.g., ΔI_pixel shown in FIG. 4A) (606). When programming completes and the monitor line 28 is activated to read the current from the pixel circuit 10, the monitor line 28 introduces an error (e.g., ΔI_MON shown in FIG. 4A) (608), and the accumulation of these three types of errors (ΔI_DATA, ΔI_pixel, and ΔI_MON) is present in the signals from the pixel circuit 10 monitored by the readout circuit 210 (610).

FIG. 7 illustrates an operation sequence where real-time measurements are utilized to provide calibration of pixel aging. The monitor line 28 error from FIG. 6 is used as a feedback to adjust an aging and hysteresis compensation before programming the pixels 10. In the system 700 shown in FIG. 7, the delays due to both the data line 22 and the monitor lines 28 are characterized and accounted for. The outputs from the monitoring system 12 are compensated and passed to the controller 2 (or the controller 2 performs any compensation after receiving the outputs), which dynamically determines, based on the output from the monitoring system 12, any adjustments to programming voltages for an incoming source of video or still display data to account for the determined time-dependent characteristics of the display 50. Aging and hysteresis of the display data are compensated (702), and the programming data for the pixels 10 is calibrated to account for both data 22 line error and pixel non-uniformity (704). During programming, the data line 22 introduces an error as described above (e.g., ΔI_DATA shown in FIG. 4A) (706), and pixel aging, hysteresis, and non-uniformity (e.g., ΔI_pixel shown in FIG. 4A) further degrades the current measurement reading of the pixel circuit 10 (708). The monitor line 28 introduces an error (e.g., ΔI_MON shown in FIG. 4A) (710), and the resultant signal with the accumulation of errors (contributed by ΔI_DATA, ΔI_pixel, and ΔI_MON) is read by the readout circuit 210 (712) at the time t_meas shown in FIG. 4A. The monitoring system 12 compensates for the delay in the monitor line 28 (714) as a feedback to compensating for the aging and hysteresis.

FIG. 8 illustrates an operation sequence 800 for isolating the initial errors in the programming path early in the operating lifetime of a display. In order to characterize the propagation delay of the data lines 22 and monitor lines 28, the programming error and the readout error are isolated as illustrated in FIG. 8. The error contributed by the propagation delay of the data line 22 (ΔI_DATA) and the error introduced by the initial non-uniformity of the panel (ΔI_pixel) can be lumped together and be considered as one source of error.

The lumped programming error is characterized by running an initial (factory) calibration at the beginning of the panel life-time, i.e. before the panel 50 is aged. At that stage in the life-time of the panel, the effects of time-dependent pixel degradation are minimal, but pixel non-uniformity (due to manufacturing processes, panel layout characteristics, etc.) can still be characterized as part of the initial lumped programming errors.

In some examples, the timing budget allocated for avoiding the settling effects can be set to different values depending on the row of the display. For example, the value of t_settle referred to in reference to FIGS. 3A-3C as the duration required to provide a programming voltage substantially not influenced by the propagation delay effects can be set to a smaller duration for the first row than the Nth row, because the settling time constant (e.g., the product of the effective resistance and effective capacitance) is generally greater at higher row numbers from the source driver. In another example, the value of t_settle referred to in reference to FIGS. 4A-4B as the duration required to read out or measure a current on the monitor line 28 that is substantially not influenced by the propagation delay effects can be set to a smaller duration for the 1st row than the Nth row, because the settling time constant (e.g., the product of the effective resistance and effective capacitance) is generally greater at higher row numbers from the row closest to the current monitoring system 12.

FIG. 9 provides an exemplary graph of readout time durations required to substantially avoid settling effects for each row in a display having 1024 rows. In the exemplary graph of FIG. 9, the circles indicate measured and/or simulated points for a subset of rows in the display (for example, pixels in rows 1, 101, 201, 301, 401, 501, 601, 701, 801, 901, and 1001 can be sampled to provide a representative subset of pixels across the entire display 50). Once the timing budget to avoid settling for the pixels in the representative subset is extracted, the timing budgets of the remaining rows can be calculated from the values for the subset (e.g., interpolated). As shown in FIG. 2, the effective resistance (R) and effective capacitance (C) of the monitor (data) line 22, 28 is approximately linearly related to row number from the current monitoring system 12 (source driver 4) as the resistance and capacitance of the lines can be approximately modeled as a series of series connected resistors and parallel connected capacitors. Thus, if a pixel is located in a row further from the current monitoring system 12, more time can be allocated for readout measurements (monitoring timing budget) to avoid settling effects than for a pixel located closer to the current monitoring system 12.

As shown in FIG. 9, the rows nearest the current monitoring system 12 (e.g., rows 1-100) are relatively unaffected by the settling effects and accordingly require comparatively low readout or monitoring timing budgets to substantially avoid settling effects. At intermediate rows (e.g., rows 200-400) the required monitoring timing budget is relatively sensitive to row number as the settling effects due to the effective resistance and capacitance across the rows of the display become significant and relative changes (e.g., from 200 to 400) translate to relatively large comparative differences in the settling constant. By contrast, the rows furthest from the current monitoring system 12 (e.g., rows 900-1000) require still more time (i.e., a greater monitoring timing budget) to avoid the settling effects, but are comparatively insensitive to row number as the effective resistance (R) and capacitance (C) is dominated by the accumulated resistance and capacitance and incremental changes (e.g., from 800 to 1000) do not translate to large comparative differences in the settling constant.

Thus, some embodiments employ differential or varied timing budgets that are specific to each row, rather than providing a constant or fixed timing budget of for example, 3 or 4 microseconds, which would be sufficient to avoid settling effects at all rows. By providing differential or adjustable timing budgets on a row-by-row basis or a subset of rows basis, the overall processing time for calibration, whether during initial factory calibration of the signal lines and/or initial pixel non-uniformities or during calibration of the monitor line effects, is significantly reduced, thereby providing greater processing and/or operating efficiency.

Thus some embodiments generally provide for reducing the effects of settling time by allocating readout or monitoring timing and/or programming timing budgets to the pixels 10 according to their position in a column (e.g., according to their row number and/or physical distance from the monitor and/or source driver 4, 12). The schemes described above can be employed to extract the line propagation delay settling characteristics by comparing measurements during typical programming budgets with measurements during timing budgets sufficient for each row to achieve settling (and the timing can be set according to pixel position). Furthermore, according to the line settling characteristics, the readout (or monitoring) time can be extracted for each pixel 10.

FIG. 10 is a flowchart 1000 of an exemplary embodiment for extracting the propagation delay effects on the monitoring line 28. A representative subset of pixels is programmed and the currents through those pixels are monitored via the monitor line 28. The measurements are taken during periods (fixed or varied monitoring timing budget) with a duration (or durations) sufficient to avoid settling effects on the monitoring line 28 (e.g., t_settle) (1002). The periods can have durations set according to row position of the measured pixel as described generally in connection with FIG. 9. The subset of pixels is then programmed with the same values and the currents through those pixels are monitored via the monitor line 28, but with durations (timing budgets) typically afforded for feedback measurements, rather than durations like t_settle sufficient to avoid settling effects (1004). The two measurements are compared to extract the effect of the propagation delay effect on the monitoring line 28 (column) (1006). In some examples, the ratio of the two current measurements can be determined to provide a gain factor for use in scaling future current measurements. Because the propagation effects generally vary across the panel 50 in a predictable manner according to the effective resistance and capacitance of the monitor line 28 at each pixel readout location, which generally accumulates linearly with increasing row separation from the monitor, the effective propagation delay is calculated (e.g., interpolated) from the representative subset.

FIG. 11 is a flowchart 1100 of an embodiment for extracting the propagation delay effects on the signal line (e.g., the signal line or path comprising the data line 22, the pixel circuit 10, and the monitoring line 28). A representative subset of pixels is programmed with programming intervals or timing budgets sufficient to avoid settling effects (1102), and the currents through those subset of pixels are monitored via the monitoring line 28 by the readout circuit 210 (1104). The programming intervals or timing budgets can each be set according to the respective row position of the programmed pixels, such that the programming intervals vary as a function of the physical distance of the pixel 10 from the readout circuit 210. The measurements are taken during periods (fixed or varied monitoring timing budget) with a duration (or durations) sufficient to avoid settling effects on the monitoring line 28 (1104). The periods or timing budgets can have durations set according to row position of the measured pixel as described generally in connection with FIG. 9. The offset, if any, from the predicted ideal current value corresponding to the provided programming value is not due to propagation delay effects in either the signal line or the monitoring line and therefore indicates pixel non-uniformity effects (e.g., drive transistor non-uniformities, threshold voltage shift, mobility variations, such as due to temperature, mechanical stress, etc.).

The subset of pixels is then programmed according to the same programming values, but during programming intervals equal to a typical programming timing budget (1106). The currents through the subset of pixels are then measured via the monitor line 28 by the readout circuit 210, again during duration(s) (fixed or varied monitoring timing budgets) sufficient to avoid settling effects (1108). The two measurements are compared to extract the propagation delay effect on the signal line (1110). In some examples, the extracted propagation delay effects for the subset of pixels are used to calculate the propagation delay effects for the subset of pixels at each row based on the respective measurements of each of the subset of pixels (1112). In some examples, the measurement scheme 1100 is repeated for each pixel in the display to detect non-uniformities across the display 50. In some examples, the extraction of the propagation delay effects on the signal line 22, 10, 28 can be performed during an initial factory calibration, and the information can be stored (in the memory 6, for example) for use in future operation of the display 50.

In some examples, the readout operations to extract pixel aging information, for example, can be employed during non-active frame times. For example, readout can be provided during black frames (e.g., reset frames, blanking frames, etc.) inserted between active frames to increase motion perception (by decrease blurring), during display standby times while the display is not driven to display an image, during initial startup and/or turn off sequences for the display, etc.

While the driving circuits illustrated in FIG. 2 are illustrated with n-type transistors, which can be thin-film transistors and can be formed from amorphous silicon, the driving circuit illustrated in FIG. 2 can be extended to a complementary circuit having one or more p-type transistors and having transistors other than thin film transistors.

Circuits disclosed herein generally refer to circuit components being connected or coupled to one another. In many instances, the connections referred to are made via direct connections, i.e., with no circuit elements between the connection points other than conductive lines. Although not always explicitly mentioned, such connections can be made by conductive channels defined on substrates of a display panel such as by conductive transparent oxides deposited between the various connection points. Indium tin oxide is one such conductive transparent oxide. In some instances, the components that are coupled and/or connected may be coupled via capacitive coupling between the points of connection, such that the points of connection are connected in series through a capacitive element. While not directly connected, such capacitively coupled connections still allow the points of connection to influence one another via changes in voltage which are reflected at the other point of connection via the capacitive coupling effects and without a DC bias.

Furthermore, in some instances, the various connections and couplings described herein can be achieved through non-direct connections, with another circuit element between the two points of connection. Generally, the one or more circuit element disposed between the points of connection can be a diode, a resistor, a transistor, a switch, etc. Where connections are non-direct, the voltage and/or current between the two points of connection are sufficiently related, via the connecting circuit elements, to be related such that the two points of connection can influence each another (via voltage changes, current changes, etc.) while still achieving substantially the same functions as described herein. In some examples, voltages and/or current levels may be adjusted to account for additional circuit elements providing non-direct connections, as can be appreciated by individuals skilled in the art of circuit design.

Two or more computing systems or devices may be substituted for any one of the controllers described herein (e.g., the controller 2 of FIG. 1). Accordingly, principles and advantages of distributed processing, such as redundancy, replication, and the like, also can be implemented, as desired, to increase the robustness and performance of controllers described herein.

The operation of the example determination methods and processes described herein may be performed by machine readable instructions. In these examples, the machine readable instructions comprise an algorithm for execution by: (a) a processor, (b) a controller, such as the controller 2, and/or (c) one or more other suitable processing device(s). The algorithm may be embodied in software stored on tangible media such as, for example, a flash memory, a CD-ROM, a floppy disk, a hard drive, a digital video (versatile) disk (DVD), or other memory devices, but persons of ordinary skill in the art will readily appreciate that the entire algorithm and/or parts thereof could alternatively be executed by a device other than a processor and/or embodied in firmware or dedicated hardware in a well known manner (e.g., it may be implemented by an application specific integrated circuit (ASIC), a programmable logic device (PLD), a field programmable logic device (FPLD), a field programmable gate array (FPGA), discrete logic, etc.). For example, any or all of the components of the baseline data determination methods could be implemented by software, hardware, and/or firmware. Also, some or all of the machine readable instructions represented may be implemented manually.

While particular embodiments and applications of the present disclosure have been illustrated and described, it is to be understood that the disclosure is not limited to the precise construction and compositions disclosed herein and that various modifications, changes, and variations can be apparent from the foregoing descriptions without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method of operating a display system, the method comprising: generating signals at a first location on a signal line of the display system;receiving the signals at a second location on the signal line; anddetermining a propagation delay effect on the signals as received at the second location with use of the received signals including determining a gain factor between the signals generated at the first location and the signals as received at the second location.

2. The method of claim 1, further comprising: controlling the operation of the display system with use of the determined propagation delay effect.

3. The method of claim 1, wherein the signal line comprises a data line coupled to a data driver at the first location and coupled to a pixel circuit at the second location.

4. The method of claim 3, further comprising controlling a programming of the pixel circuit to compensate for the propagation delay effect.

5. The method of claim 1, wherein the signal line comprises a monitor line coupled to a pixel circuit at the first location and coupled to a monitor at the second location.

6. The method of claim 5, further comprising controlling a monitoring of the pixel circuit to compensate for the propagation delay effect.

7. The method of claim 1, wherein determining the propagation delay effect comprises determining a signal offset between the signals generated at the first location and the signals as received at the second location.

8. The method of claim 1, wherein said generating and receiving the signals and said determining the propagation delay effect are performed during an initial factory calibration of the display system.

9. A method of operating a display system, the method comprising: generating signals at a first location on a signal line of the display system;receiving the signals at a second location on the signal line, each of the received signals at the second location received with use of time periods of different durations; anddetermining a propagation delay effect on the signals as received at the second location with use of the received signals.

10. The method of claim 9, wherein at least one of the time periods of different durations is a function of a physical distance between the first location and the second location.

11. The method of claim 9, wherein the time periods of different durations comprise at least a first time period of a duration sufficient to avoid settling effects and a second time period of a duration insufficient to avoid settling effects.

12. The method of claim 11, further comprising: controlling the operation of the display system with use of the determined propagation delay effect.

13. A display system comprising: a signal line; anda controller coupled to the signal line and adapted to control the display system to: generate signals at a first location on the signal line; andreceive the signals at a second location on the signal line, anddetermine a propagation delay effect on the signals as received at the second location with use of the received signals including determining a gain factor between the signals generated at the first location and the signals as measured at the second location.

14. The display system of claim 13, wherein the controller is further adapted to control the operation of the display system with use of the determined propagation delay effect.

15. The display system of claim 13, further comprising: a data driver; anda pixel circuit,

16. The display system of claim 15, wherein the controller is further adapted to control a programming of the pixel circuit to compensate for the propagation delay effect.

17. The display system of claim 13, further comprising: a monitor; anda pixel circuit,

18. The display system of claim 17, wherein the controller is further adapted to control a monitoring of the pixel circuit to compensate for the propagation delay effect.

19. The display system of claim 13, wherein the controller is adapted to determine the propagation delay effect by determining a signal offset between the signals generated at the first location and the signals as measured at the second location.

20. The display system of claim 13, wherein the controller is adapted to control the display system to generate and receive the signals and to determine the propagation delay effect during an initial factory calibration of the display system.

21. A display system comprising: a signal line; anda controller coupled to the signal line and adapted to control the display system to: generate signals at a first location on the signal line; andreceive the signals at a second location on the signal line, each of the received signals at the second location received with use of time periods of different durations, anddetermine a propagation delay effect on the signals as received at the second location with use of the received signals.

22. The display system of claim 21, wherein at least one of the time periods of different durations is a function of a physical distance between the first location and the second location.

23. The display system of claim 21, wherein the time periods of different durations comprise at least a first time period of a duration sufficient to avoid settling effects and a second time period of a duration insufficient to avoid settling effects.

24. The display system of claim 23, wherein the controller is further adapted to control the operation of the display system with use of the determined propagation delay effect.