The present invention relates to a distributed control apparatus that controls an entire system by means of a plurality of units, and a communication technology for industrial apparatuses including a semiconductor inspection apparatus that uses the distributed control apparatus.
In a semiconductor inspection apparatus, an electronic control system that includes analog input/output paths from a plurality of centrally managed control boards to a sensor or an actuator mounted on the apparatus is generally used. However, in the current system, because an increase in the amount of wiring, substrate redesign, and the like, occur in accordance with function expansion, it is difficult to cope with the diversification in apparatus needs that has been increasing in recent years. Thus, there is a pressing need to improve design productivity of an electronic system.
Therefore, by applying a network-type distributed control system to an in-apparatus electronic system, an improvement in function expandability can be expected while reducing analog wiring.
However, when a network-type distributed control system is introduced into a semiconductor inspection apparatus, a high-speed constant cycle and low-delay input/output for performing control of the apparatus are required, and thus it is necessary to secure a data communication band. For example, in JP 2011-2402 A (PTL 1), a software control unit and a hardware control unit are provided. The software control unit includes a scheduler unit that performs scheduling processing in which a scheduled transmission time is calculated for each piece of data enqueued in each of a plurality of queues for which priority level set values are set according to the types of data to be stored, on the basis of the priority level set values set for the queues, and in which the data is dequeued and outputted to the hardware control unit together with time information indicating the scheduled transmission time, thereby securing a communication band for data with a high priority level.
PTL 1: JP 2011-24027 A
Nevertheless, in the case of the technology disclosed in PTL 1, while the communication band can be secured, data is occasionally discarded or delayed depending on the data type.
An object of the present invention is to provide a distributed control system, and a semiconductor inspection apparatus that includes the distributed control system, that execute data communication necessary for apparatus control at high speed while maintaining a certain communication delay for all data requiring an input/output.
In order to solve the foregoing problem, the present invention is a distributed control system including a tree topology network or a daisy-chain network including a communication parent station, communication child stations, and a plurality of communication paths among the communication parent station and the communication child stations, wherein the communication parent station and the communication child stations include a scheduling unit that controls a transfer cycle that is temporal intervals of data transfer, the scheduling unit sets the transfer cycle that is the fastest out of a plurality of the data as a reference cycle, counts the number of times each time the reference cycle elapses, and imparts a value of the number of times to the reference cycle as a cycle number, when the cycle number reaches an optional number, the number of times is returned to an initial value, which makes one cycle of transfer control, and the transfer control is repeatedly executed, and for the timing of the reference cycle at which the data is transferred, the scheduling unit executes scheduling processing to define a cycle number to which the reference cycle corresponds, on the basis of first information corresponding to the data.
According to the present invention, it is possible to provide a distributed control system, and a semiconductor inspection apparatus that includes the distributed control system, that execute data communication necessary for apparatus control at high speed while maintaining a certain communication delay for all data requiring an input/output.
Hereinafter, embodiments according to the present invention will be described with reference to the drawings.
In the distributed control system 1, the upstream communication port 111 of a communication child station 11 is connected to the communication port 102 of the communication parent station 10 or to the downstream communication port 112 of a communication child station 11. In addition, for the sake of expediency in the description, communication in the direction from the communication parent station 10 to the communication child station 11 is defined as the upstream direction, and communication in the direction from the communication child station 11 to the communication parent station 10 is defined as the downstream direction. At this time, the distributed control system 1 performs communication band control in all data communication handled by the distributed control system 1 by executing the scheduling processing and transfer control of the scheduling units 101 of the communication parent station 10 and the communication child stations 11.
Next, a detailed configuration of each communication station will be described.
Further, details of the scheduling unit 101 will be described. The scheduling unit 101 includes a settings decoding unit 30, a write enable storage unit 31, a writing unit 32, at least one address queue unit 33, a queue selection unit 34, a buffer selection unit 35, at least one buffer unit 36, a memory unit 37, and a cycle management unit 38. Here, the settings decoding unit 30 reads information stored in the memory unit 37 and further interprets the content thereof. The write enable storage unit 31 outputs a write enable that is defined in advance on the basis of the content of the information obtained by the settings decoding unit 30. The writing unit 32 selects the address queue unit 33 to which information is to be written on the basis of the write enable outputted by the write enable storage unit 31. The address queue unit 33 stores the addresses of data which is transmitted and received under the transfer control. During the execution of transfer control, the queue selection unit 34 selects an appropriate address queue unit 33 and reads information stored in the address queue unit 33. The buffer selection unit 35 selects the buffer unit 36 on the basis of the information outputted from the queue selection unit 34. Each buffer unit 36 stores and outputs the address of data to be received or the address of data to be transmitted. The memory unit 37 stores information necessary for scheduling processing. The cycle management unit 38 counts the number of times a reference cycle necessary for transfer control has elapsed.
Note that details of the transfer control, the scheduling processing, and the reference cycle will be described subsequently. The communication parent station 10 is connected to the central processing unit 13 and writes information from the central processing unit 13 to the memory unit 37.
Here, the communication band control executed by the distributed control system 1 will be described. A timetable 5 for data transfer when the communication band control is applied is illustrated in
As described above, in order to execute communication band control, it is necessary to determine the transfer timing, as per the timetable 5, for all the transfer data 50. The transfer timing is defined by each piece of information of a communication direction of the data in the upstream direction or the downstream direction, a cycle number of a reference cycle for starting the transfer, and a temporal interval from when the transfer data 50 is transferred to when the next transfer data 50 is transferred. In addition, when the transfer timing is determined, the transfer data 50 transferred in each reference cycle is arranged so as to be distributed. For example, the transfer data 50 of No. 6 and No. 7 of 200 microseconds are both transferred once every four reference cycles, but are alternately transferred. By determining the transfer timing in this manner, the number of pieces of transfer data 50 of each reference cycle can be distributed, and the communication band can be controlled.
The scheduling processing and transfer control that constitute communication band control will be described below.
The scheduling processing is pre-preparation processing performed by the scheduling unit 101 in order to implement transfer control.
First, A will be described. In the communication parent station 10, first, in S60, the central processing unit 13 writes predetermined information to the memory unit 37. Here, the predetermined information is information for determining the transfer timing. Next, in S61, the predetermined information is also transmitted to the communication child station. S60 and S61 are repeated, and in a case where it is determined in S62 that the writing of all the predetermined information has been completed, the scheduling processing is started in S63. At this time, in S64, a first instruction, which is a notification of the start of the scheduling processing, is transmitted to the communication child station 11. Next, in S65, predetermined information is read from the memory unit 37, and the settings decoding unit 30 interprets the content. In S66, a write enable 70 held in the write enable storage unit 31 is outputted on the basis of the interpretation result in the settings decoding unit 30. In S67, the address queue unit 33 is selected by the write enable 70, and the address of the data corresponding to the predetermined information read in S65 is stored in the selected address queue unit 33. Here, the scheduling unit 101 includes an address queue unit 33 that corresponds to each cycle number, and a plurality of addresses stored in each address queue unit 33 is a set of data transferred in the reference cycle of the cycle number. Finally, when the entire memory unit 37 is read in S67, the scheduling processing is complete.
Next, B will be described. The communication child station 11 receives the predetermined information transmitted from the communication parent station 10 in S69, and writes the information received in S610 to the memory unit 37. Next, when the first instruction is received in S611, the scheduling unit starts the scheduling processing in S612. Because the processing from S613 onwards is the same as the processing of S65, a description thereof will be omitted.
Here, the write enable 70 will be described.
Next, transfer control is a function for performing communication band control while maintaining the timetable 5 for data transfer set by the scheduling processing while the distributed control system 1 is performing apparatus control.
First, C will be described. In the communication parent station 10, the processing of C is started when the central processing unit 13 or the parent station communication control unit 100 activates a time management trigger for apparatus control. At this time, the time management trigger is a signal issued every reference cycle. In C, after receiving the input of the time management trigger in S80, the cycle management unit 38 updates the cycle number in S81. Next, in S82, the communication parent station 10 transmits the second instruction including the cycle number to all the communication child stations. Here, the second instruction is an instruction for reporting the start of the transfer control. Further, in S83, the queue selection unit 34 selects the address queue unit 33 corresponding to the cycle number, and outputs the stored address. At this time, as the addresses stored in the address queue unit 33, the address to be transmitted and the address to be received are outputted simultaneously. Therefore, in S84, the buffer selection unit 35 outputs the address of the data to be transmitted to a transmission buffer unit 36, and outputs the address of the data to be received to the reception buffer unit 36. Finally, in S85, the parent station communication control unit 100 generates the packet 2 while referring to the address stored in the buffer unit 36, and transmits the packet 2 to the communication child stations 11.
Next, D will be described. In the communication child stations 11, after the child station communication control unit 110 receives the second instruction in S86, the cycle number is updated in S87. Because the processing from S88 to S810 is the same as the processing from S83 to S85 in C, a description thereof will be omitted here.
The communication operation of the distributed control system 1, when the transfer control described above is executed, is illustrated in
Here, an example of a log of received data that can be observed by the communication parent station 10 when the distributed control system 1 executes communication band control is illustrated in
According to an aspect of this embodiment, the distributed control system 1 is capable of ensuring a communication band and a constant communication delay for the inputting/outputting of all data necessary for control of the apparatus.
According to this embodiment, the distributed control system 1200 is capable of performing independent communication band control in a network system centered on each of the communication parent stations 10, and of cooperating via each of the communication parent stations 10 while controlling different control targets.
According to this embodiment, by applying the distributed control system 1 or the distributed control system 1200 to the semiconductor inspection apparatus 1300, the control system can be optimally arranged in an optional space, and the number of assembly steps can be reduced due to the advantageous effect of reducing the analog wiring.
1 distributed control system
10 communication parent station
100 parent station communication control unit
101 scheduling unit
102 communication port
11 communication child station
110 child station communication control unit
111 upstream communication port
112 downstream communication port
113 input/output port
12 communication path
13 central processing unit
2 packet
20 address unit
21 command unit
22 synchronization unit
23 data unit
30 settings decoding unit
31 write enable storage unit
32 writing unit
33 address queue unit
34 queue selection unit
35 buffer selection unit
36 buffer unit
37 memory unit
38 cycle management unit
5 timetable
50 transfer data
70 write enable
71 plurality of address queue units
72 transfer target queue
1000 data log
1100 system settings screen
1101 communication station configuration screen
1102 schedule settings screen
1103 communication parent station model
1104 communication child station model
1105 connector
1106 address unit
1107 settings input unit
1200 distributed control system
1201 expansion port
1300 semiconductor inspection apparatus
1301 input/output control apparatus
1302 control device
Filing Document | Filing Date | Country | Kind |
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PCT/JP2020/023030 | 6/11/2020 | WO |