The present disclosure relates to electrostatic discharge protection, and more specifically, to electrostatic discharge protection circuits with magnetically coupled differential inputs and outputs.
The input and output speed of integrated circuits (ICs) constantly increases with each respective new generation of chips. Input/output (I/O) pins of large ICs can exceed 4 Tb of data per second of aggregated data transfer. ICs tend to build up electrostatic charges. Consequently, ICs are routinely configured with electrostatic discharge (ESD) protection circuits to mitigate chip damage caused by electrostatic charge buildup. However, at higher data transfer rates, capacitance of ESD protection elements may exceed allowable limits. Unfortunately, ESD devices have not scaled to keep up with increases in IC speed. In some conventional approaches, T-coils have been used to cancel out a portion of the capacitance. However, this may not be sufficient for ultra-wide band ICs.
According to some embodiments, a distributed electrostatic discharge protection circuit includes a plurality of electrostatic discharge protection elements and a current balancing network connecting the plurality of electrostatic discharge protection elements. The current balancing network is configured in a return path of the distributed electrostatic discharge protection circuit such that during an electrostatic discharge (ESD) event, the circuit provides predefined current density within each of the electrostatic discharge protection elements.
According to other embodiments, a method for electrostatic discharge protection may include configuring a plurality of electrostatic discharge protection elements in a current balancing network having a plurality of electrostatic discharge protection elements, and grounding the electrostatic discharge protection elements via a return path of a distributed electrostatic discharge protection circuit such that during an electrostatic discharge (ESD) event the circuit provides predefined current density within each of the electrostatic discharge protection elements.
According to yet other embodiments, an apparatus may include a distributed electrostatic discharge protection circuit. The circuit may include a plurality of electrostatic discharge protection elements, and a current balancing network connecting the plurality of electrostatic discharge protection elements. The current balancing network is configured in a return path of the distributed electrostatic discharge protection circuit such that during an electrostatic discharge (ESD) event the circuit provides predefined current density within each of the electrostatic discharge protection elements.
The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
Other conventional approaches may include the use of distributed ESD protection circuits such as the circuit depicted with respect to
Other approaches have attempted to distribute current through stacked diodes and resistors. However the signal loss of the stacked resistors has been shown to be less than optimal. For example, ESD circuits may be highly dependent on frequency, as current balance may lose effectiveness when used with more than one frequency, as shown in the example in
In yet other conventional approaches, transmission lines 6 may be intervened by silicon controlled resistors (SCRs) 7 in an effort to balance current. In some configurations most ESD current may flow through SCR1, and significantly less through SCR2. Even less ESD current may flow through SCR3.
Referring now to
Accordingly, couplings 402-408 may be configured to balance the load on current distribution network 400. Network 400 may further include a plurality of SCRs 410, 412, 414, 410′, 412′, and 414′, which may be intervened by inductor coils Lg1 and Lg2 (416 and 418, respectively), which balance ESD currents in the ESD protection elements. Accordingly, the inductors may be configured in at least one chain of inductors. The bottom side of inductors 416 and 418 are part of the ground return path for all SCRs. By adding couplings 402-408, the effective size of the current distribution network 400 may be reduced by a factor of 2.
In other aspects, an ESD protection circuit such as current distribution network 400 may be optimal because the magnetic couplings (e.g., couplings 402-408), may not have a bypass path for pulse energy to bypass the ESD elements (e.g., load configurations). In contrast, when magnetic couplings are configured as single T-coils as in
In other aspects, the inductors may be configured to form a Chebyshev low-pass filter.
Central triggering for the SCR feature may be highly beneficial in some embodiments because the snapback in SCR current/voltage characteristic could prevent all other SCRs from triggering if one of the SCRs triggers early. This may be due in part to voltage decreases below triggering. In some aspects, triggering could be implemented similar to a SCR power clamp. Accordingly, trigger voltage may be sensed not only on the voltage supply, but also on the signal pin.
In some aspects, centralized triggering can be made by replacing a diode triggered SCR by a FET triggered SCR. Accordingly, the trigger circuit may detect a short pulse, similar to a clamp.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Number | Name | Date | Kind |
---|---|---|---|
5416663 | Atkins | May 1995 | A |
5969929 | Kleveland et al. | Oct 1999 | A |
7151298 | Eggert | Dec 2006 | B1 |
7564663 | Nicholson | Jul 2009 | B2 |
7589944 | Mergens et al. | Sep 2009 | B2 |
7609495 | Soldner et al. | Oct 2009 | B2 |
7989987 | McDonald | Aug 2011 | B2 |
9019669 | Ransijn | Apr 2015 | B1 |
20050162790 | Yoshinaga | Jul 2005 | A1 |
20090046401 | Dunnihoo | Feb 2009 | A1 |
20110181990 | Huang | Jul 2011 | A1 |
20120275074 | Dill | Nov 2012 | A1 |
20130163127 | Chu | Jun 2013 | A1 |
Number | Date | Country |
---|---|---|
2000510653 | Aug 2000 | JP |
2008015213 | Feb 2008 | WO |
Entry |
---|
Banerjee, K., et al., Analysis and Design of Distributed ESD Protection Circuits for Highspeed Mixed-Signal and RFICs; Electron Devices, IEEE Transactions, vol. 49, Issue 8; Aug. 2002: pp. 1444-1454, (3 pages). |
Ker, Ming-Dou, et al., “Decrasing-Size Distributed EDS Protection Scheme for Broad-Band RF Circuits,” IEEE Transactions on Microwave Theory and Techniques, vol. 53, No. 2, Feb. 2005; pp. 582-589, (8 pages). |
Ker, Ming-Dou, et al., “ESD Protection Design for Broadband RF Circuits with Decreaing-Size Distributed Protection Scheme”, 2004, IEEE Radio Frequency Integrated Circuits Symposium; pp. 383-386, (4 pages). |
Kleveland, Bendik et al., “Distributed ESD Protection for High-Speed Integrated Circuits,” IEEE Electron Device Letters, vol. 21, No. 8, Aug. 2000; pp. 390-392, (3 pages). |