DIVISION UNIT, IMAGE ANALYSIS UNIT AND DISPLAY APPARATUS USING THE SAME

Abstract

A division unit, an image analysis unit and a display apparatus using the same capable of simplifying the computation of overall average gray scale are provided. The shift-add type of division unit includes a plurality of shift units for shifting an input signal by a different number of bits, an adder for totaling the shifted result in the shift units and producing an addition result, and a most-significant-bit (MSB) shift unit for extracting the MSB (contains a plurality of bits) of the addition result to serve as a division result.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 is a flow diagram showing the steps for performing a conventional shift division.

FIG. 2 is a diagram of a division circuit deploying a conventional look-up table.

FIG. 3 is a block diagram of a division circuit according to the first embodiment of the present invention.

FIG. 4 is a block diagram of a division circuit according to the second embodiment of the present invention.

FIG. 5 is a block diagram of a division circuit according to the third embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

In one embodiment of the present invention, a combinatorial circuit comprising a shift adder and a multiplexer is used to obtain an overall average gray scale value. The overall average gray scale value thus obtained can be used in image analysis for improving the display quality of the image. Compared with the conventional shift division method, the present embodiment only requires a consideration of the net delay, which is considerably smaller than the time needed to perform a shift division, so that some computational time is saved. In a combinatorial logic circuit, shifting involves only a simple and fast wiring connection that demands very little circuit area. Thus, compared with a look-up table method, the present embodiment requires very little additional circuit area.

If the number 1152000 is represented as a base 2 index, it is obtained:

Log₂ 1152000≈20.1357  (6)

The formula (6) can be rearranged into:

1152000≈2²⁰*20.1357≈2²⁰*1.09863  (7)

After putting formula (7) into formula (5), it is obtained:

$\begin{array}{cc}\begin{array}{c}\mathrm{AVG\_L}=\mathrm{TOTAL\_L}/\left(220*1.09863\right)\\ =\mathrm{TOTAL\_L}*0.9102/2^{20}\end{array}& \left(8\right)\end{array}$

In formula (8), the purpose of putting a 2²⁰ in the denominator is to facilitate hardware implementation. The division by 2²⁰ represents shifting the dividend right by 20 bits. Thus, in formula (8), the required result is obtained after designing a simple circuit to process the number 0.9102.

Through a simple numerical analysis of the number 0.9102, it is obtained:

$\begin{array}{cc}\begin{array}{c}0.9102\approx 0.5+0.25+0.125+0.03125+0.00390625\\ \approx 2^{-1}+2^{-2}+2^{-3}+2^{-5}+2^{-8}\end{array}& \left(9\right)\end{array}$

After putting formula (9) into formula (8), it is obtained:

$\begin{array}{cc}\begin{array}{c}\mathrm{AVG\_L}=\left(\mathrm{TOTAL\_L}*\left(2^{-1}+2^{-2}+2^{-3}+2^{-5}+2^{-8}\right)\right)*2^{-20}\\ =(\mathrm{TOTAL\_L}*2^{-1}+\mathrm{TOTAL\_L}*2^{-2}+\\ \mathrm{TOTAL\_L}*2^{-3}+\mathrm{TOTAL\_L}*2^{-5}+\\ \mathrm{TOTAL\_L}*2^{-8}))*2^{-20}\end{array}& \left(10\right)\end{array}$

Formula 10 represents shifting the totaled gray scale signal (TOTAL_L) 1, 2, 3, 5 and 8 bits respectively and then summing them together. Thereafter, the value is shifted 20 bits to obtain the overall average gray scale value AVG_L. In formula 10, the reason for not shifting 20 bits first is that the present embodiment does not use a floating-point computation function. If the 20-bit shift is performed first, the decimal portion may appear too early, leading to an inaccurate calculation.

According to formula (10), FIG. 3 is a block diagram of a division circuit according to the first embodiment of the present invention. As shown in FIG. 3, the circuit in the first embodiment includes a plurality of shift units 31 to 35, an adder 36 and a most-significant-bit (MSB) shift unit 37.

In the present embodiment, the totaled gray scale signal TOTAL_L has 29 bits altogether and the overall average gray scale value AVG_L has 8 bits. The shift units 31 to 35 are used to shift 1 bit, 2 bits, 3 bits, 5 bits and 8 bits of the totaled gray scale signal TOTAL_L respectively. Since the shift units 31 to 35 only perform a shifting operation, the output signal still contains 29 bits.

The adder 36 adds the output signals from the shift units 31 to 35 together. Because the 29^th bit of the addition result by the adder 36 is supposed to be as 0, only last 28 bits of the addition result are output from the adder 36. Then, the MSB shift unit 37 shifts the output signal (28 bits) of the adder 36 by 20 bits and extracts the 8 bits to serve as the overall average gray scale value AVG_L.

Through the structure shown in FIG. 3, only a plurality of shift units and an adder are required to obtain the overall average gray scale value AVG_L. Therefore, in the first embodiment, the overall average gray scale value AVG_L can be obtained without too much computational time or circuit area.

In an actual circuit design, a shifting operation is only a wiring action. To perform a 1-bit shift, all one has to do is to shift the trailing bit of the input signal to the right a wiring bit and then adds a logic ‘0’ to complete a 1-bit right shift. The concept of shifting other bits is quite similar. Therefore, the present invention also provides a second embodiment whose circuit diagram is shown in FIG. 4.

In FIG. 4, the bus line signal {1′b0,TOTAL_L[28:1]} indicates that, of the 29 bit bus lines of the totaled gray scale signal TOTAL_L, the first bit is 0 and the following 28 bits are the first bus line to the 28^th bus line of the bus lines of the totaled gray scale signal TOTAL_L. That is, the bus line signal {1′b0,TOTAL_L[28:1]} represents shifting the TOTAL_L to the right one bit and then adding a 0 to the first bit as compensation. The bus line signals {2′b0,TOTAL_L[28:2]}, {3′b0,TOTAL_L[28:3]}, {5′b0,TOTAL_L[28:5]} and {8′b0,TOTAL_L[28:8]} have a similar meaning. After passing the five bus line signals {1′b0,TOTAL_L[28:1]}, {2′b0,TOTAL_L[28:2]}, {3′b0,TOTAL_L[28:3]}, {5′b0,TOTAL_L[28:5]} and {8′b0,TOTAL_L[28:8]} through an adder 41, the adder 41 outputs a 29-bit output result Adder[28:0].

However, in the present embodiment, eight bits Adder[27:20] of the output result Adder[28:0] are input to a multiplexer 42. Moreover, the most significant bit Adder[28] of the output result Adder[28:0] serves as a control signal to the multiplexer 42. The reason for this is to prevent any interference (for example, noise) during the computation process from causing the adder 41 to overflow. Thus, the 29^th bit Adder[28], with the possibility of triggering an overflow, is treated as a control bit for the multiplexer 42. If the Adder[28] has a bit value ‘0’, there is no overflow and the output bits Adder[27:20] from the adder 41 are the required overall average gray scale value AVG_L. On the other hand, if the Adder[28] has a bit value ‘1’, an overflow has occurred and the multiplexer 42 will select eight bits of 1 (8b′11111111) to serve as the overall average gray scale value AVG_L. That means the overall average gray scale value AVG_L is 255 (the highest value).

The application of the first and the second embodiments is not limited to a resolution of 1152000. They can also be applied to systems having other resolutions as long as the formulas (6) to (10), the amount of shifting in various shift units and the method of generating the bus signals are suitably adjusted.

FIG. 5 is a block diagram of a division circuit according to the third embodiment of the present invention. As shown in FIG. 5, the display apparatus 50 includes at least an image analysis unit 51, a contrast-adjust unit 54, a dynamic backlight adjusting unit 55 and a display panel 56. The image analysis unit 51 further includes an adder 52 and a shift adder 53.

The image analysis unit 51 obtains the overall average gray scale value AVG_L based on the gray scale signal IN. The adder 52 adds up all the gray scale signals of the image together to obtain a totaled gray scale signal TOTAL_L. The shift adder 53 receives the totaled gray scale signal TOTAL_L and outputs an overall average gray scale value AVG_L accordingly. The shift adder 53 can have a structure based on the first or the second embodiment of the present invention.

The overall average gray scale value AVG_L output from the image analysis unit 51 is input to the contrast-adjust unit 54 and the dynamic backlight adjusting unit 55. According to the overall average gray scale value AVG_L, the contrast-adjust unit 54 and the dynamic backlight adjusting unit 55 adjust images on the display panel 56 to improve the display quality.

Therefore, by using a high speed and small circuit area shift adder 53 in the third embodiment, the display apparatus 50 can compute the overall average gray scale value AVG_L within a very short time and use the value to perform an image analysis for improving the display quality.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Claims

1. A division unit, comprising: a first to an Nth shift units for shifting M bits of an input signal by a different number of bits respectively for generating output signals respectively, wherein N and M are positive whole numbers;an adder for receiving the output signals from the first to the Nth shift units and producing an addition result; anda most significant bit (MSB) shift unit for receiving the addition result of the adder and extracting an MSB of the addition result to serve as a division result of the division unit.

2. The division unit of claim 1, wherein, when the input signal has 29 bits (M=29) and the division unit divides the input signal by 1152000, then N=5, and the first to the fifth shift units perform a 1-bit, a 2-bits, a 3-bits, a 5-bits and an 8-bits shifting operation of the input signal respectively.

3. The division unit of claim 2, wherein the addition result of the adder has 28 bits.

4. The division unit of claim 3, wherein the MSB shift unit extracts the 8-bit MSB from the 28-bit addition result to serve as the division result.

5. A division unit for dividing an input signal with M bits (where M is a positive whole number), comprising: an adder for receiving a first to an Nth bus signals to produce an addition result, wherein the first to the Nth bus signals shift the input signal by a different number of bits and adding logic zeros to the shifted bits as compensation, where N is a positive whole number; anda multiplexer for receiving a most significant bit (MSB) of the addition result, wherein, when the MSB has a first value, the multiplexer treats P bits of the addition result as a division result, and when the MSB has a second value, the multiplexer outputs P logic 1 to serve as the division result, where P is a positive whole number.

6. The division unit of claim 5, wherein, when the input signal has 29 bits (M=29) and the division unit divides the input signal by 1152000, then N=5 and P=8, and the first to the Nth bus signals are the result obtained after performing a 1-bit, a 2-bits, a 3-bits, a 5-bits and an 8-bits shifting operation of the input signal respectively.

7. The division unit of claim 6, wherein the addition result of the adder has 29 bits.

8. The division unit of claim 7, wherein the MSB of the addition result is the 29th bit, the first value of the MSB is logic ‘0’ and the second value of the MSB is logic ‘1’.

9. The division unit of claim 8, wherein, when the MSB is logic ‘0’, the division result is the 28th bit to the 21st bit of the addition result.

10. An image analysis unit for a display apparatus, comprising: an adder for receiving all gray scale signals of an image and producing a totaled gray scale signal; anda shift adder for receiving the totaled gray scale signal of the adder, simultaneously and paralleled shifting the totaled gray scale signal by a different number of bits, adding the shifted totaled gray scale signals together and extracting predetermined bits of the addition result to serve as an overall average gray scale signal of the image, wherein the overall average gray scale signal is used for image analysis.

11. The image analysis unit of claim 10, wherein the shift adder comprises: a first to an Nth shift units for shifting the M-bit totaled gray scale signal a different number of bits respectively for generating output signals respectively, wherein N and M are positive whole numbers;an adder for receiving the output signals of the first to the Nth shift units to produce an addition result; anda most significant bit (MSB) shift unit for receiving the addition result of the adder and extracting an MSB of the addition result to serve as the overall average gray scale signal.

12. The image analysis unit of claim 10, wherein the shift adder comprises: an adder for receiving a first to an Nth bus signals and producing an addition result, wherein the first to the Nth bus signals shift the M-bits totaled gray scale signal by a different number of bits and add logic ‘0’ to the shifted bits as compensation, where N is a positive whole number; anda multiplexer for receiving a most significant bit (MSB) of the addition result of the adder, wherein, when the MSB is logic ‘O’, the multiplexer treats P bits of the addition result as the overall average gray scale signal, and when the MSB is logic ‘1’, the multiplexer outputs a plurality of logic ‘1’ to serve as the overall average gray scale signal, where P is a positive whole number.

13. A display apparatus, comprising: an image analysis unit for receiving all gray scale signals of an image to produce a totaled gray scale signal, simultaneously performing a shifting of the totaled gray scale signal by a different number of bits, adding up the shifted totaled gray scale signals and extracting predetermined bits of the addition result to serve as an overall average gray scale signal of the image;an image-quality adjusting unit for receiving the overall average gray scale signal produced by the image analysis unit; anda panel for displaying the image, wherein the image-quality adjust unit adjusts the image displayed on the panel according to the overall average gray scale signal.

14. The display apparatus of claim 13, wherein the image analysis unit comprises: an adder for receiving all gray scale signals of the image to produce a totaled gray scale signal; anda shift adder for simultaneously shifting the totaled gray scale signal by a different number of bits, adding up the shifted totaled gray scale signals and extracting predetermined bits of the addition result to serve as an overall average gray scale signal of the image.

15. The display apparatus of claim 14, wherein the shift adder comprises: a first to an Nth shift units for shifting the M-bits totaled gray scale signal by a different number of bits for generating output signals respectively, where N and M are positive whole numbers;an adder for receiving the output signals from the first to the Nth shift units and producing an addition result; anda most significant bit (MSB) shift unit for receiving the addition result of the adder and extracting an MSB of the addition result to serve as the overall average gray scale signal.

16. The display apparatus of claim 14, wherein the shift adder comprises: an adder for receiving a first to an Nth bus signals to produce an addition result, wherein the first to the Nth bus signals shift the M-bits totaled gray scale signal by a different number of bits and adding logic ‘0’ to the shifted bits as compensation, where N is a positive whole number; anda multiplexer for receiving a most significant bit (MSB) of the addition result of the adder, wherein, when the MSB is logic ‘0’, the multiplexer treats P bits of the addition result as the overall average gray scale signal, and when the MSB is logic ‘1’, the multiplexer outputs a plurality of logic ‘1’ to serve as the overall average gray scale signal, where P is a positive whole number.

17. The display apparatus of claim 13, wherein the image-quality adjusting unit comprises a contrast-adjust unit, or a dynamic backlight adjusting unit, or a combination of the two.