Patent Application
20250183849
This application claims priority based on Japanese Patent Application No. 2023-203090 filed on Nov. 30, 2023, and the entire contents of the Japanese patent application are incorporated herein by reference.
The present invention relates to a Doherty amplifier circuit and a semiconductor device.
It is known an N-way (N is three or more) Doherty amplifier circuit using a main amplifier and two or more peak amplifiers (for example, U.S. Pat. Nos. 8,022,760 and 10,601,375). It is known that a main amplifier and a peak amplifier are provided on an identical semiconductor chip (for example, WO 2023/187921).
A Doherty amplifier circuit according to an embodiment of the present disclosure includes a divider that divides a received input signal into a first signal, a second signal, and a third signal, a main amplifier that amplifies the first signal and outputs an amplified first signal as a fourth signal, a first peak amplifier that amplifies the second signal and outputs an amplified second signal as a fifth signal, a second peak amplifier that amplifies the third signal and outputs an amplified third signal as a sixth signal, a combiner that combines the fourth signal, the fifth signal, and the sixth signal into a combined signal and output the combined signal to an output terminal as an output signal, and a semiconductor chip including the main amplifier, the first peak amplifier, and the second peak amplifier. An input power of the input signal at which the second peak amplifier is turned on is larger than an input power of the input signal at which the first peak amplifier is turned on, and the main amplifier and the first peak amplifier are adjacent to each other.
A Doherty amplifier circuit according to an embodiment of the present disclosure includes a divider that divides a received input signal into a first signal, a second signal, and a third signal, a main amplifier that amplifies the first signal and outputs an amplified first signal as a fourth signal, a first peak amplifier that amplifies the second signal and outputs an amplified second signal as a fifth signal, a second peak amplifier that amplifies the third signal and outputs an amplified third signal as a sixth signal, a combiner that combines the fourth signal, the fifth signal, and the sixth signal into a combined signal and outputs the combined signal to an output terminal as an output signal, a first semiconductor chip including the main amplifier and the first peak amplifier, and a second semiconductor chip different from the first semiconductor chip and including the second peak amplifier. An input power of the input signal at which the second peak amplifier is turned on is larger than an input power of the input signal at which the first peak amplifier is turned on.
A semiconductor device for a Doherty amplifier circuit according to an embodiment of the present disclosure includes a main amplifier that amplifies a first signal divided from an input signal and outputs an amplified first signal as a fourth signal, a first peak amplifier that amplifies a second signal divided from the input signal and outputs an amplified second signal as a fifth signal, a second peak amplifier that amplifies a third signal divided from the input signal and outputs an amplified third signal as a sixth signal, and a semiconductor chip including the main amplifier, the first peak amplifier, and the second peak amplifier. An input power of the input signal at which the second peak amplifier is turned on is larger than an input power of the input signal at which the first peak amplifier is turned on, and the main amplifier and the first peak amplifier are adjacent to each other.
A semiconductor device for a Doherty amplifier circuit according to an embodiment of the present disclosure includes a main amplifier that amplifies a first signal divided from an input signal and outputs an amplified first signal as a fourth signal, a first peak amplifier that amplifies a second signal divided from the input signal and outputs an amplified second signal as a fifth signal, a second peak amplifier that amplifies a third signal divided from the input signal and outputs an amplified third signal as a sixth signal, a first semiconductor chip including the main amplifier and the first peak amplifier, and a second semiconductor chip different from the first semiconductor chip and including the second peak amplifier. An input power of the input signal at which the second peak amplifier is turned on is larger than an input power of the input signal at which the first peak amplifier is turned on.
When the difference in characteristics such as parasitic capacitance between a main amplifier and a plurality of peak amplifiers is large, the phases between amplifiers shift from a desired difference, and the characteristics such as gain deteriorate. In an N-way (Nis three or more) Doherty amplifier circuit, it is not known how to arrange the main amplifier and the plurality of peak amplifiers to improve the characteristics.
An object of the present disclosure is to suppress deterioration of the characteristics.
First, the contents of embodiments of the present disclosure will be listed and explained.
Specific examples of a Doherty amplifier circuit and a semiconductor device according to embodiments of the present disclosure will be described below with reference to the drawings. It should be noted that the present disclosure is not limited to these examples, but is defined by the claims and is intended to include all modifications within the meaning and scope equivalent to the claims.
A high-power high-frequency amplifier circuit used in a base station of mobile communication will be described as an example of a Doherty amplifier circuit. In this case, the frequency of the high frequency signal is, for example, 0.5 GHz to 10 GHz.
As illustrated in
A high frequency signal is input to an input terminal Tin as an input signal Sin. Divider 16 divides input signal Sin input to input terminal Tin into signals S1 (first signal), S2 (second signal), and S3 (third signal). Divider 16 is, for example, a Wilkinson-type divider.
A path to which signal S1 is input includes a matching circuit 30, a bias circuit 36, main amplifier 10, a bias circuit 39, and a matching circuit 33. A path to which signal S2 is input includes a matching circuit 31, a bias circuit 37, peak amplifier 12, and a matching circuit 34. A path to which signal S3 is input includes a matching circuit 32, a bias circuit 38, peak amplifier 14, and a matching circuit 35.
Matching circuits 30 to 32 match the impedances seen from divider 16 toward matching circuits 30 to 32 to the impedances seen from matching circuits 30 to 32 toward main amplifier 10 and peak amplifiers 12 and 14, respectively. Bias circuits 36 to 38 supply gate bias voltages VG1 to VG3 to gates G of main amplifier 10 and peak amplifiers 12 and 14, respectively, and suppress the leakage of signals S1 to S3 to the bias terminals.
Main amplifier 10 and peak amplifiers 12 and 14 amplify signals S1, S2 and S3 and output the amplified signals S4 (fourth signal), S5 (fifth signal) and S6 (sixth signal), respectively. Bias circuit 39 supplies a drain bias voltage VD to drains D of main amplifier 10 and peak amplifiers 12 and 14, and suppresses the leakage of signal S4 to the bias terminal. Matching circuits 33 to 35 match the impedances seen from main amplifier 10 and peak amplifiers 12 and 14 toward matching circuits 33 to 35, respectively, to the impedances seen from matching circuits 33 to 35 toward combiner 18. Combiner 18 combines signals S4 to S6 and outputs the combined signal to an output terminal Tout as an output signal Sout.
Main amplifier 10 and peak amplifiers 12 and 14 include transistors Q1 to Q3, respectively. Transistors Q1 to Q3 are, for example, field effect transistors (FETs), such as gallium nitride high electron mobility transistors (GaN HEMTs) or laterally diffused metal oxide semiconductors (LDMOSs). Sources S of transistors Q1 to Q3 are grounded, signals S1 to S3 are input to each of gates G, and signals S4 to S6 are output from each of drains D. Transistors Q1 to Q3 are mounted on a single semiconductor chip 20. Matching circuits 30 to 33 and semiconductor chip 20 are mounted on a package 50.
As illustrated in
Leads 27a to 27c are disposed on a side of base 51 in a negative direction of the X direction with insulating layers (not illustrated) interposed between base 51 and leads 27a to 27c. Leads 28a to 28c are disposed on a side of base 51 in a positive direction of the X direction with insulating layers (not illustrated) interposed between base 51 and leads 28a to 28c. Leads 27a to 27c and 28a to 28c are metal layers or metal plates made of, for example, copper. Signals S1 to S3 are input to leads 27a to 27c, respectively, and signals S4 to S6 are output from leads 28a to 28c, respectively.
Semiconductor chip 20 includes a substrate 21, transistors Q1 to Q3, pads 22a to 22c and 23a to 23c disposed on an upper surface of substrate 21, and an electrode (not illustrated) disposed on a lower surface of substrate 21. Pads 22a (first input pad), 23a (first output pad) and the electrode on the lower surface are electrically connected to a gate G (input terminal), a drain D (output terminal) and a source S of transistor Q1, respectively. Pads 22b (second input pad), 23b (second output pad) and the electrode on the lower surface are electrically connected to a gate G (input terminal), a drain D (output terminal) and a source S of transistor Q2, respectively. Pads 22c (third input pad), 23c (third output pad) and the electrode on the lower surface are electrically connected to a gate G (input terminal), a drain D (output terminal) and a source S of transistor Q3, respectively.
Substrate 21 is a semiconductor substrate. When transistors Q1 to Q3 are GaN HEMTs, substrate 21 is, for example, a silicon carbide (SiC) substrate, a sapphire substrate, or a gallium nitride (GaN) substrate. When transistors Q1 to Q3 are LDMOS, substrate 21 is, for example, a silicon (Si) substrate. Pads 22a to 22c, 23a to 23c and the electrodes on the lower surfaces are metal layers, such as gold layers. Although transistor Q1 is illustrated as being smaller than transistors Q2 and Q3 (for example, the gate width is smaller and the saturation power is smaller when the gate bias voltage and the drain bias voltage are the same), transistor Q1 may be the same as transistors Q2 and Q3 (for example, the same gate width and the same saturation power when the gate bias voltage and the drain bias voltage are the same).
Each of capacitive components 24a to 24c include a dielectric substrate 25, an electrode 26 disposed on an upper surface of dielectric substrate 25, and an electrode (not illustrated) disposed on a lower surface of dielectric substrate 25. Electrode 26 and the electrode on the lower surface, which sandwich dielectric substrate 25, form a capacitor. Dielectric substrate 25 is, for example, an alumina substrate or a barium titanate substrate. Electrode 26 is, for example, a metal layer, such as a gold layer.
Bonding wires 46 electrically connect leads 27a to 27c and electrodes 26 of capacitive components 24a to 24c, respectively. Bonding wires 47 electrically connect electrodes 26 of capacitive components 24a to 24c and pads 22a to 22c, respectively. Bonding wires 48 electrically connect pads 23a to 23c and leads 28a to 28c, respectively. Bonding wires 46 to 48 are metal wires, such as gold wires or aluminum wires.
Bonding wires 46 and 47 function as inductors, and capacitive components 24a to 24c function as capacitors. Bonding wires 46 and 47 and capacitive components 24a to 24c correspond to at least a part of matching circuits 30 to 32 of T-type LCL circuits.
Transistor Q1 includes a source electrode 41a, a gate electrode 42a, and a drain electrode 43a arranged in the Y direction. Transistor Q2 includes a source electrode 41b, a gate electrode 42b, and a drain electrode 43b arranged in the Y direction. Transistor Q3 includes a source electrode 41c, a gate electrode 42c, and a drain electrode 43c arranged in the Y direction. An insulating layer 49 is disposed on substrate 21 so as to cover transistors Q1 to Q3. Insulating layer 49 is an organic insulating layer, such as a polyimide layer or a benzocycbutene (BCB) layer. At least a part of insulating layer 49 may be an inorganic insulating layer.
When transistors Q1 to Q3 are GaN HEMTs, substrate 40a is, for example, a silicon carbide substrate, and semiconductor layer 40b includes a gallium nitride transit layer and an aluminum gallium nitride barrier layer. Source electrodes 41a to 41c and drain electrodes 43a to 43c are metal films, and are, for example, titanium films and aluminum films stacked in this order from semiconductor layer 40b. Gate electrodes 42a to 42c are metal films, and are, for example, nickel films and gold films stacked in this order from semiconductor layer 40b
In transistors Q1 to Q3, the thicknesses of the respective layers of semiconductor layer 40b are substantially the same. For example, in transistors Q1 to Q3, the thicknesses of the gallium nitride transit layers are the same as each other, and the thicknesses of the aluminum gallium nitride barrier layers are the same as each other. In addition, in transistors Q1 to Q3, the sizes of source electrodes 41a to 41c are the same as each other, the sizes of gate electrodes 42a to 42c are the same as each other, and the sizes of drain electrodes 43a to 43c are the same as each other.
Thus, the characteristics per unit gate widths of transistors Q1 to Q3 are substantially the same as each other e. For example, in transistors Q1 to Q3, the gate source capacitances per unit gate widths are substantially the same as each other, the drain source capacitances per unit gate widths are substantially the same as each other, and the gate drain capacitances per unit gate widths are substantially the same as each other.
The probability is a probability of a modulated wave signal of a high frequency signal for mobile communication amplified by Doherty amplifier circuit 100. That is, the probability is a probability that Doherty amplifier circuit 100 outputs a certain output power Pout. Each Pout is output power Pout of each of main amplifier 10 and peak amplifiers 12 and 14. Each gain is a power gain of each of main amplifier 10 and peak amplifiers 12 and 14. The overall gain is a power gain of output power Pout of output signal Sout with respect to an input power Pin of input signal Sin. Pin and Pout are expressed in dB. The gain of main amplifier 10 at a power P1 or less of each gain is larger than the gain of peak amplifier 12 at power P1 or more and a power P2 or less. That is, the slope of Pout with respect to input power Pin at a power equal to or less than power P1 in main amplifier 10 is larger than the slope of Pout with respect to input power Pin at power P1 or more and power P2 or less in peak amplifier 12. However,
As illustrated in
When input power Pin of input signal Sin increases, at input power Pin more than power P0 and power P1 or less, main amplifier 10 operates, but peak amplifiers 12 and 14 do not operate. When input power Pin is equal to or less than power P1, output power Pout of main amplifier 10 increases linearly as input power Pin increases. Thus, when input power Pin is equal to or less than power P0, each gain and the overall gain are substantially constant.
When input power Pin is equal to or more than power P1 and equal to or less than power P2, main amplifier 10 and peak amplifier 12 operate, but peak amplifier 14 does not operate. In this range, main amplifier 10 is saturated. Thus, the gain of main amplifier 10 is reduced. The overall gain is also reduced along with reducing the gain of main amplifier 10. Since peak amplifier 12 is performed in class-C operation, the gain of peak amplifier 12 between power P1 and power P2 is lower than the gain of main amplifier 10 at a power equal to or less than power P1. Also, the saturation power of peak amplifier 12 is smaller than the saturation power of main amplifier 10.
When input power Pin is equal to or more than power P2 and equal to or less than a power P3, all of main amplifier 10 and peak amplifiers 12 and 14 operate. In this range, peak amplifier 12 is saturated in addition to main amplifier 10. Thus, the gain of peak amplifier 12 is reduced. The overall gain also is reduced along with reducing the gain of main amplifier 12. Since the operating point of peak amplifier 14 is negatively larger than the operating point of peak amplifier 12, the gain of peak amplifier 14 between powers P2 and P3 is lower than the gain of peak amplifier 12 between powers P1 and P2. Also, the saturation power of peak amplifier 14 is smaller than the saturation power of peak amplifier 12.
When input power Pin is equal to or more than power P3, peak amplifier 14 is saturated in addition to main amplifier 10 and peak amplifier 12. Thus, the gain of peak amplifier 14 is reduced. The overall gain is also reduced along with reducing the gain of main amplifier 14.
The product of the probability and the overall gain corresponds to the gain of the modulated wave. In order to improve the gain of the modulated wave, the overall gain at Pout having a high probability is improved.
According to the first embodiment, as illustrated in
As illustrated in
As illustrated in
As illustrated in
As illustrated in
Main amplifier 10 and peak amplifiers 12 and 14 are arranged in the Y direction. Pads 22a and 23a are located with main amplifier 10 interposed therebetween in the X direction. Pads 22b and 23b are located with peak amplifier 12 interposed therebetween in the X direction. Pads 22c and 23c are located with peak amplifier 14 interposed therebetween in the X direction. Thus, pads 22a to 22c and 23a to 23c are not disposed between main amplifier 10 and peak amplifier 12 or between peak amplifiers 12 and 14. Thus, main amplifier 10 and peak amplifier 12 can be adjacent to each other, and peak amplifiers 12 and 14 can be adjacent to each other.
No passive element such as an inductor or a capacitor is disposed on semiconductor chip 20. Thus, no passive element is disposed between main amplifier 10 and peak amplifier 12 and between peak amplifiers 12 and 14. Thus, main amplifier 10 and peak amplifier 12 can be adjacent to each other, and peak amplifiers 12 and 14 can be adjacent to each other.
In order to improve the gain of the modulated wave, it is effective to reduce the phase difference between main amplifier 10 and peak amplifier 12. Thus, semiconductor chip 20a (first semiconductor chip) includes main amplifier 10 and peak amplifier 12. Thus, the phase difference between main amplifier 10 and peak amplifier 12 is reduced, and the gain of the modulated wave can be improved. On the other hand, when three amplifiers are disposed on the identical semiconductor chip 20 as in the first embodiment, semiconductor chip 20 is determined to be non-defective when all the three amplifiers are non-defective. Thus, the yield of semiconductor chip 20 is reduced. Thus, peak amplifier 14 that does not affect the gain of the modulated wave as much as peak amplifier 12 is mounted on semiconductor chip 20c (second semiconductor chip) different from semiconductor chip 20a. Thus, the yield of semiconductor chips 20a and 20c can be improved.
Main amplifier 10 and peak amplifier 12 are adjacent to each other on semiconductor chip 20a. Thus, the difference in parasitic capacitance between transistors Q1 and Q2 is reduced. Thus, the deterioration of the characteristics can be suppressed. Referring to
Although the first embodiment and its modification have been described by taking a 3-way Doherty amplifier circuit as an example, in the case of an N-way Doherty amplifier circuit, N-1 peak amplifiers may be provided.
The embodiments disclosed here should be considered illustrative in all respects and not restrictive. The present disclosure is not limited to the specific embodiments described above, but various variations and changes are possible within the scope of the gist of the present disclosure as described in the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-203090 | Nov 2023 | JP | national |
