Claims
- 1. A method for forming a DRAM/EEPROM chip, comprising:
forming a plurality of dynamic random access memory (DRAM) access transistors on a semiconductor substrate; forming a plurality of stacked capacitors in a subsequent level above the plurality of DRAM access transistors and separated from the plurality of DRAM access transistors by an insulator layer; and coupling a first group of the plurality of stacked capacitors to a gate for each DRAM access transistor in a first group of the plurality of DRAM access transistors; coupling a second group of the plurality of stacked capacitors to a diffused region in a second group of the plurality of DRAM access transistors.
- 2. The method of claim 1, wherein forming a plurality of DRAM access transistors includes forming a plurality of n-channel metal oxide semiconductor (NMOS) transistors.
- 3. The method of claim 1, wherein forming a plurality of stacked capacitors includes forming a plurality of stacked capacitors having a bottom plate, a capacitor dielectric, and a top plate, wherein the bottom plate is formed in a cup shape having interior walls, the capacitor dielectric is formed conformal to the bottom plate and the top plate is formed conformal to the capacitor dielectric, and wherein forming the plurality of stacked capacitors includes forming a portion of the top plate within the interior walls of the bottom plate.
- 4. The method of claim 3, wherein coupling a first group of the plurality of stacked capacitors to a gate in each DRAM access transistors in a first group of the plurality of DRAM access transistors includes coupling the bottom plate of each stacked capacitor in the first group of the plurality of stacked capacitors to the gate for the first group of the plurality of DRAM access transistors.
- 5. The method of claim 1, wherein the forming a plurality of stacked capacitors includes forming the plurality of stacked capacitors according to a dynamic random access memory (DRAM) process flow.
- 6. A programmable logic array, comprising:
a first logic plane that receives a number of input signals, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs; a second logic plane having a number of non-volatile memory cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function; and wherein the non-volatile memory cells each include:
a metal oxide semiconductor field effect transistor (MOSFET); a stacked capacitor formed according to a dynamic random access memory (DRAM) process; and an electrical contact that couples the stacked capacitor to a gate of the MOSFET.
- 7. The programmable logic array of claim 6, wherein the first logic plane and the second logic plane each comprise NOR planes.
- 8. The programmable logic array of claim 6, wherein the substrate is a bulk semiconductor.
- 9. The programmable logic array of claim 6, wherein the electrical contact includes a polysilicon plug.
- 10. The programmable logic array of claim 6, wherein the working surface of the substrate includes an insulating layer formed on top of an underlying semiconductor.
- 11. The programmable logic array of claim 6, wherein the programmable logic array is operatively coupled to a computer system.
- 12. The programmable logic array of claim 6, wherein the stacked capacitor includes a fin type capacitor.
- 13. The programmable logic array of claim 6, wherein the stacked capacitor includes a storage node, a capacitor dielectric, and a plate conductor and wherein the electrical contact couples the storage node of the stacked capacitor to the gate of the MOSFET.
- 14. An address decoder for a memory device, the address decoder comprising:
a number of address lines; a number of output lines; wherein the address lines, and the output lines form an array; a number of non-volatile memory cells that are disposed at intersections of output lines and address lines, wherein each non-volatile memory cell includes a metal oxide semiconductor field effect transistor (MOSFET), a stacked capacitor formed according to a dynamic random access memory (DRAM) process, and an electrical contact that couples the stacked capacitor to a gate of the MOSFET; and wherein the non-volatile memory cells are selectively programmed such that the non-volatile memory cells implement a logic function that selects an output line responsive to an address provided to the address lines.
- 15. The address decoder of claim 14, wherein the number of address lines includes a number of complementary address lines that are disposed in the array.
- 16. The address decoder of claim 14, wherein the decoder is operatively coupled to a dynamic random access memory (DRAM) device.
- 17. The address decoder of claim 14, wherein the array includes N address lines and 2N output lines.
- 18. The address decoder of claim 14, wherein the number of address lines includes a number of complementary address lines that are each coupled to one of the address lines through an inverter and are disposed in the array.
- 19. An electronic system, comprising:
a memory; and a processor coupled to the memory and formed on a die common with the memory; and wherein the processor includes at least one programmable logic array including:
a first logic plane that receives a number of input signals, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs, and wherein the non-volatile memory cells each include:
a metal oxide semiconductor field effect transistor (MOSFET); a stacked capacitor formed according to a dynamic random access memory (DRAM) process; and an electrical contact that couples the stacked capacitor to a gate of the MOSFET.
- 20. The electronic system of claim 19, wherein the programmable logic array includes a second logic plane having a number of non-volatile memory cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function.
- 21. The electronic system of claim 20, wherein the first logic plane and the second logic plane each comprise NOR planes.
- 22. The electronic system of claim 19, wherein:
the processor includes at least one register formed from dynamic random access memory cells; and wherein the processor includes at least one function and sequence circuit.
- 23. The electronic system of claim 19, wherein the processor includes a program circuit that stores a program.
- 24. The electronic system of claim 23, wherein the program circuit stores the program in an EEPROM.
- 25. An integrated circuit formed in and on a semiconductor layer, the integrated circuit comprising:
a plurality of metal oxide semiconductor field effect transistors (MOSFETs) formed in and on the semiconductor layer; a plurality of stacked capacitors disposed above the plurality of MOSFETs and separated from the plurality of MOSFETs by an insulator layer; and wherein a first group of the plurality of stacked capacitors is selectively coupled to gates of the MOSFETs to form non-volatile memory cells for a first sub-circuit; wherein a second group of the plurality of stacked capacitors is selectively coupled to diffused regions of the MOSFETs to form a second sub-circuit; and wherein the first sub-circuit is operatively coupled to the second sub-circuit.
- 26. The integrated circuit of claim 25, wherein the plurality of stacked capacitors includes a plurality of stacked capacitors formed according to a dynamic random access memory (DRAM) process flow.
- 27. An integrated circuit, comprising:
a processor; a memory, operatively coupled to the processor; and wherein the processor and the memory are formed on the same semiconductor substrate and the processor includes at least one programmable logic array with a non-volatile memory cell that includes a metal oxide semiconductor field effect transistor with a stacked capacitor coupled to its gate.
- 28. A method for forming an integrated circuit, the method comprising:
forming a plurality of metal oxide semiconductor transistors (MOSFETs) in and on a layer of semiconductor material; forming a first set of stacked capacitors that are coupled to diffusion regions of selected ones of the plurality of MOSFETs to form a memory array; and forming, on the same layer of semiconductor material, a second set of stacked capacitors that are coupled to gates of selected ones of the plurality of MOSFETs to form a plurality of non-volatile memory cells; and interconnecting the memory array and the non-volatile memory cells to provide the integrated circuit.
- 29. The method of claim 28, wherein forming a second set of stacked capacitors comprises forming a second set of stacked capacitors that are coupled to gates of selected ones of the plurality of MOSFETs to form a EEPROM.
- 30. The method of claim 28, wherein forming a second set of stacked capacitors comprises forming a second set of stacked capacitors that are coupled to gates of selected ones of the plurality of MOSFETs to form at least one programmable logic array.
- 31. The method of claim 28, wherein forming a second set of stacked capacitors comprises forming a second set of stacked capacitors that are coupled to gates of selected ones of the plurality of MOSFETs to form a memory decode array.
- 32. The method of claim 28, wherein forming a second set of stacked capacitors comprises forming a second set of stacked capacitors that are coupled to gates of selected ones of the plurality of MOSFETs to form at least one programmable logic array of a processor circuit.
- 33. A method for forming a memory chip, comprising:
forming a plurality of access transistors at a first level of a substrate; forming a plurality of stacked capacitors at a second level of the substrate; forming an insulator separating the plurality of access transistors from the plurality of stacked capacitors; coupling a first group of the plurality of stacked capacitors to a gate of each access transistor in a first group of the plurality of access transistors; and coupling a second group of the plurality of stacked capacitors to a first region in a second group of the plurality of access transistors.
- 34. The method of claim 33, wherein forming the plurality of access transistors includes forming metal oxide semiconductor transistors.
- 35. The method of claim 34, wherein forming metal oxide semiconductor transistors includes forming an n-channel transistor.
- 36. The method of claim 33, wherein forming the stacked capacitors occurs after forming the access transistors.
- 37. The method of claim 33, wherein the second level is formed above the first level.
- 38. The method of claim 33, wherein forming a plurality of stacked capacitors includes forming a plurality of stacked capacitors having a bottom plate, a capacitor dielectric, and a top plate, wherein the bottom plate is formed in a cup shape having interior walls, the capacitor dielectric is formed conformal to the bottom plate and the top plate is formed conformal to the capacitor dielectric, and wherein forming the plurality of stacked capacitors includes forming a portion of the top plate within the interior walls of the bottom plate.
- 39. The method of claim 38, wherein coupling a first group of the plurality of stacked capacitors to a gate in each access transistors in a first group of the plurality of access transistors includes coupling the bottom plate of each stacked capacitor in the first group of the plurality of stacked capacitors to the gate for the first group of the plurality of access transistors.
- 40. The method of claim 33, wherein forming the plurality of access transistors includes forming a plurality of DRAM access transistors.
- 41. A method for forming a memory chip, comprising:
forming a plurality of access transistors at a first level of a substrate; forming a first plurality of first stacked capacitors at a second level of the substrate; forming a second plurality of second stacked capacitors on the substrate; coupling the first plurality of the first stacked capacitors to diffusion regions of selected first ones of the access transistors to form a memory array; coupling the second plurality of the second stacked capacitors to gates of selected second ones of the access transistors to form a plurality of non-volatile memory cells; and interconnecting the memory array and the non-volatile memory cells.
- 42. The method of claim 41, wherein forming the second plurality of second stacked capacitors includes forming the second stacked capacitors includes forming the second stacked capacitors at the second level of the substrate.
- 43. The method of claim 42, wherein the second level is above the first level.
- 44. The method of claim 41, wherein forming the plurality of access transistors includes forming metal oxide semiconductor transistors.
- 45. The method of claim 41, wherein coupling the second plurality of the second stacked capacitors includes forming an EEPROM.
- 46. The method of claim 41, wherein coupling the second plurality of the second stacked capacitors includes forming a programmable logic array.
- 47. The method of claim 41, wherein coupling the second plurality of the second stacked capacitors includes forming a memory decode array.
- 48. The method of claim 41, wherein coupling the second plurality of the second stacked capacitors includes forming at least one programmable logic array of a processor.
- 49. The method of claim 41, wherein forming the plurality of access transistors includes forming DRAM access transistors.
- 50. A method of forming an integrated circuit, comprising:
forming an array of intersecting address lines and output lines; disposing non-volatile memory cells at intersections of the address lines and the output lines; wherein disposing non-volatile memory cells includes:
forming an access transistor; forming a stacked capacitor that has a coupling ratio greater than 1.0 and that is coupled to the access transistor; and selectively programming the non-volatile memory cells to implement a logic function.
- 51. The method of claim 50, wherein selectively programming includes programming the logic function to select an output line based on an address provided on the address lines.
- 52. The method of claim 50, wherein forming the array includes forming pairs of an address line and a complementary address line.
- 53. The method of claim 50, wherein forming the array includes forming N address lines and forming 2N output lines.
- 54. The method of claim 50, wherein forming the array includes forming a number of complementary address lines that are each coupled to one of the address lines through an invertor.
- 55. The method of claim 50, wherein forming the stacked capacitor includes forming a cup-shaped capacitor.
- 56. The method of claim 50, wherein forming the stacked capacitor includes forming capacitors according to a DRAM process.
- 57. The method of claim 50, wherein forming the stacked capacitor includes connecting the capacitors to a gate of the access transistor.
- 58. The method of claim 57, wherein connecting the capacitors includes connecting the capacitors to the gate with a polysilicon plug.
- 59. The method of claim 50, wherein forming the capacitor includes forming a fin type capacitor.
RELATED APPLICATIONS
[0001] This application is related to commonly assigned applications, U.S. application Ser. No. 09/259,493, filed Feb. 26, 1999, now U.S. Pat. No. 6,380,581, U.S. application Ser. No. 09/261,597, filed Feb. 26, 1999, now U.S. Pat. No. 6,297,989, and U.S. application Ser. No. 09/261,479, filed Feb. 26, 1999, now U.S. Pat. No. 6,256,225 which are hereby incorporated by reference.
[0002] This application is a Divisional of U.S. application Ser. No. 09/261,598, filed Feb. 26, 1999 which is incorporated herein.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09261598 |
Feb 1999 |
US |
Child |
10191330 |
Jul 2002 |
US |