TREA

Dual mode arithmetic saturation processing

Follow

Information

  • Patent Grant
  • 7467178
  • Patent Number
    7,467,178
  • Date Filed
    Friday, June 1, 2001
    25 years ago
  • Date Issued
    Tuesday, December 16, 2008
    17 years ago
Information
Abstract
A system and method for overflow and saturation processing during accumulator operations that reduces the error in a saturation operation. Upon overflow, additional guard bits used in conjunction with an accumulator allow a user to continue processing without any error in the values used in computations following the overflow. A saturation condition can be detected following the overflow the appropriate maximum value stored in the accumulator upon detecting saturation.
Description
FIELD OF THE INVENTION

The present invention relates to systems and methods in a device such as a processor, including microprocessors and controllers. More particularly, the present invention relates to systems and methods for overflow and saturation processing during accumulator operations.


BACKGROUND OF THE INVENTION

Processors, including microprocessors, digital signal processors and microcontrollers, typically include an accumulator that stores the results of operations performed by the processor. Common operations performed include addition and subtraction. Addition and subtraction operations may cause the result of the operation to exceed the maximum value of the accumulator.


In an accumulator, the most significant bit of the accumulator can be used to represent the sign of the number stored in the remaining bits of the accumulator. For example, in a 32 bit accumulator the most significant bit, b31 can represent the sign of the number stored in bits b30-b0. Using such an arrangement, the accumulator can store a maximum negative number of 0x80000000, where “0x” denotes hexadecimal. The accumulator can store a maximum positive number of 0x7FFFFFFF. Typical saturation processing in the exemplary 32 bit accumulator sets the 32 bit accumulator to the maximum positive number, 0x7FFFFFFF, or the maximum negative number 0x80000000 as the case may require. To illustrate, suppose the following two numbers are added, 0x007FFFF000 and 0x0000001020. The result is 0x0080000020, with an overflow of the result into the sign bit, b31. Because the result of adding two positive numbers overflowed, the maximum positive number 0x007FFFFFFF is stored in the accumulator.


The above common saturation operation, however, causes the result to be truncated. That is, the actual result of the operation is lost and an approximate result represented by a selected one of the predetermined constants is stored in the accumulator. Thus, the accumulator value after being set by the saturation processing is erroneous. It is desirable to minimize the error introduced by the saturation processing.


SUMMARY OF THE INVENTION

It is an object of the present invention to provide an efficient saturation processing system and method.


It is another object of the present invention to provide a saturation processing system and method that reduces the error introduced by the saturation processing.


It is a further object of the present invention to provide a saturation processing system and method that allows programmers the flexibility of additional accuracy in overflow and saturation processing.


It is still another object of the present invention to provide a saturation processing system and method that provides enhanced computational accuracy in saturation processing of an overflow condition.


It is still a further object of the present invention to provide a saturation processing system and method that can be selectively enabled and disabled.


To achieve the above an other objects, the present invention provides a system for overflow and saturation processing, comprising: an adder, operatively connected to receive first and second operands, and connected to add the operands; an accumulator, operatively connected to store at least a portion of the added operands or at least a portion of a selected one of predetermined constants based on control signals; guard bits, operatively connected to store the remaining portion of the added operands or the remaining portion of the selected one of predetermined constants based on the control signals; overflow logic operatively connected to the accumulator and to the guard bits so as to indicate overflow of the accumulator; and saturation logic, operatively connected to the adder, to the guard bits, and connected to provide the control signals based on at least a portion of the added operands at least a portion of the guard bits.


To achieve the above and other object, the present invention also provides a method for overflow and saturation processing in a processor including guard bits and an accumulator, comprising: adding operands to form a result; comparing a portion of the result with a portion of the guard bits; storing either a portion of the result in the accumulator and the remaining portion of the result in the guard bits, or a portion of a selected predetermined constant in the accumulator and the remaining portion of the predetermined constant in the guard bits in accordance with an enable signal and the result of the comparison.





BRIEF DESCRIPTION OF THE FIGURES


FIG. 1 is a schematic block diagram of a portion of a processor structure that can embody the present invention.



FIG. 2 is a schematic block diagram of an exemplary embodiment of the present invention.





DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS


FIG. 1 is a schematic block diagram of a portion of a processor structure that can embody the present invention. Referring to FIG. 1, saturation logic 20 is coupled to an accumulator 10 and to an adder 30. As will be recognized by those skilled in the art, the adder 30 performs operations on Operand1 and Operand2. In the above example, of adding 0x007FFFF000 and 0x0000001020. The result is 0x0080000020. By comparing the most sign bit, b31, of the result with the sign of the accumulator, the overflow condition is detected. The saturation logic 20 causes the maximum positive number 0x007FFFFFFF to be stored in the accumulator 10.



FIG. 2 is a schematic block diagram of an exemplary embodiment of the present invention. This is only an example of an embodiment of the present invention. Those skilled in the art will recognize that the logic of FIG. 2 can be implemented in a variety of ways, such as, for example, micro code, logic gates, or a programmable logic array. Moreover, while FIG. 2 shows a 32-bit accumulator, the invention is not limited to any particular number of bits in an accumulator.



FIG. 2 shows an exemplary 32-bit accumulator 60. Bit b31 of accumulator 60 represents the sign of the value stored in bits b0-b31. In accordance with the present invention, guard bits 65 are used in conjunction with the accumulator 60. In FIG. 2, bits b39-b32 represent the guard bits 65. The present invention is not limited to eight guard bits as shown in FIG. 2. Preferably two or more guard bits are used, with the upper limit of guard bits being determined by the particular application.


NAND gate 70 and OR gate 75 detect an overflow condition of the accumulator. The output of a multiplexer 80 indicates whether the operation performed by adder 90. The output of multiplexer 80 can be applied to a status register, not shown. The state of the overflow bit in the status register can change for each operation performed by adder 90.



FIG. 2 shows saturation logic 20 coupled to the guard bits 65, the accumulator 60 and adder 90. The saturation logic 20 provides control signals to selector inputs “A” and “B” of a multiplexer 95. As shown in the illustrative example of FIG. 2, the saturation logic 20 compares most significant bits of the guard bits 65 with most significant bits of the result of the operation performed by the adder 90. In FIG. 2, AND gates 100 and 105 together with inverters 110 and 115 combine guard bits b39 and b38. In addition, AND gates 120 and 125 together with inverters 130 and 135 combine bits b39 and b38 of the result of the operation performed by adder 90. AND gates 140 and 145 compare the outputs of And gates 100, 105, 120, and 125 to form control signals that are applied to the A, B inputs of multiplexer 95. AND gates 140 and 145 also receive an Enable signal. In an example embodiment of the present invention, the Enable signal could originate in a mode register that has bits that are set and reset by respective instructions executed by the processor. In the illustrative example shown in FIG. 2, when the Enable signal is active, logic 1, the saturation logic allows one of two predetermined constants to be stored in the guard bits 65 and accumulator 60 as indicated by Table 2 shown below. Alternatively, if the Enable signal is inactive, logic 0, the multiplexer/selector 90 allows the result of the operation performed by the adder 90 to be stored in the guard bits 65 and accumulator 60. The Enable signal and the AND gates 140 and 145 function as a means for providing the control signals in accordance with the Enable signal and in accordance with the comparison of the guard bits 65 and the result of the operation performed by the adder 90.


In addition, together gates 100-145 function as a logic means that is responsive to the comparison of the guard bits 65 and the result of the operation performed by the adder 90 so as to selectively provide the control signals so that the accumulator stores at least a portion of the added operands and the guard bits store the remaining portion of the added operands, or the accumulator stores at least a portion of a predetermined constant (e.g., 0x7FFFFFFFFF) and the guard bits store the remaining portion of the predetermined constant (e.g., 0x7FFFFFFFFF). Table 1 illustrates the logic conditions that give rise to a saturation condition in the illustrative embodiment shown in FIG. 2. In Table 1, the “x” denotes a “don't care” condition of the respective bit.













TABLE 1





Guard
Guard
Result
Result



Bit b39
Bit b38
Bit b39
Bit b38
Action







0
1
1
0
Saturation, Store






0x7FFFFFFFFF in Guard






bits and Accumulator


1
0
0
1
Saturation, Store






0x800000000 in Guard bits






and Accumulator


0
x
0
x
No action, store result of






operation performed by






Adder


1
x
1
x
No action, store result of






operation performed by






Adder









output of an OR gate 150 indicates if saturation condition has occurred. Typically, the output of the OR gate 150 is applied to a saturation bit in a status register (not shown). It is common that the saturation bit of the status register be set on the occurrence of saturation and remain set until reset by an instruction executed by the processor. Table 2 below represents logical operation of the multiplexer 95.


The output of the multiplexer 95 is stored in the guard bits 65 and the accumulator 60.











TABLE 2





A
B
OUT







0
0
Result [b39-b0]


0
1
0x800000000


1
0
0x7FFFFFFFFF


(1 
1
Not possible)









While specific embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that changes may be made to those embodiments without departing from the spirit and scope of the invention that is defined by the following claims.

Claims
  • 1. A system for overflow and saturation processing, comprising: an adder, operatively connected to receive first and second operands, and connected to add the operands to produce a result of the added operands;an accumulator, operatively connected to store at least a portion of the result of the added operands or at least a portion of a selected one of predetermined constants based on control signals;guard bits, operatively connected to store the remaining portion of the result of the added operands or the remaining portion of the selected one of predetermined constants based on the control signals;overflow logic operatively connected to the accumulator and to the guard bits so as to indicate overflow of the accumulator;saturation logic, operatively connected to the adder, to the guard bits, and connected to provide the control signals based on at least a portion of the result of the added operands and at least a portion of the guard bits; andwherein the saturation logic comprises a plurality of AND logic gates and a plurality of inverting logic gates, the pluralities of AND gates and the plurality of inverting logic gates configured to compare most significant bits of the guard bits and most significant bits of the result of the added operands, and further configured to generate the control signals in accordance with the comparison.
  • 2. The system according to claim 1, wherein the saturation logic includes: a selector operatively connected to selectively provide a one of the result of the added operands or a one of the predetermined constants based on the comparison.
  • 3. The system according to claim 1, wherein the logic means includes: means for providing the control signals in accordance with an enable signal and in accordance with the comparison.
  • 4. The system according to claim 3, wherein the logic means further includes: means, responsive to the comparison, for selectively providing the control signals so that the accumulator stores at least a portion of the result of the added operands and the guard bits store the remaining portion of the result of the added operands, or the accumulator stores at least a portion of a predetermined constant and the guard bits store the remaining portion of the predetermined constant.
US Referenced Citations (217)
Number Name Date Kind
3771146 Cotton et al. Nov 1973 A
3781810 Downing Dec 1973 A
3886524 Appelt May 1975 A
3930253 Maida Dec 1975 A
4025771 Lynch et al. May 1977 A
4074353 Woods et al. Feb 1978 A
4090250 Carlson et al. May 1978 A
4323981 Nakamura Apr 1982 A
4379338 Nishitani et al. Apr 1983 A
4398244 Chu et al. Aug 1983 A
4408274 Wheatley et al. Oct 1983 A
4451885 Gerson et al. May 1984 A
4472788 Yamazaki Sep 1984 A
4481576 Bicknell Nov 1984 A
4488252 Vassar Dec 1984 A
4511990 Hagiwara et al. Apr 1985 A
4556938 Parker et al. Dec 1985 A
4615005 Maejima et al. Sep 1986 A
4626988 George Dec 1986 A
4709324 Kloker Nov 1987 A
4730248 Watanabe et al. Mar 1988 A
4742479 Kloker et al. May 1988 A
4768149 Konopik et al. Aug 1988 A
4779191 Greenblatt Oct 1988 A
4782457 Cline Nov 1988 A
4800524 Roesgen Jan 1989 A
4807172 Nukiyama Feb 1989 A
4829420 Stahle May 1989 A
4829460 Ito May 1989 A
4839846 Hirose et al. Jun 1989 A
4841468 Miller et al. Jun 1989 A
4872128 Shimizu Oct 1989 A
4882701 Ishii Nov 1989 A
4926371 Vassilliadis et al. May 1990 A
4941120 Brown et al. Jul 1990 A
4943940 New Jul 1990 A
4945507 Ishida et al. Jul 1990 A
4959776 Deerfield et al. Sep 1990 A
4977533 Miyabayashi et al. Dec 1990 A
4984213 Abdoo et al. Jan 1991 A
5007020 Inskeep Apr 1991 A
5012441 Retter Apr 1991 A
5032986 Pathak et al. Jul 1991 A
5034887 Yasui et al. Jul 1991 A
5038310 Akagiri et al. Aug 1991 A
5040178 Lindsay et al. Aug 1991 A
5056004 Ohde et al. Oct 1991 A
5099445 Studor et al. Mar 1992 A
5101484 Kohn Mar 1992 A
5117498 Miller et al. May 1992 A
5121431 Wiener Jun 1992 A
5122981 Taniguchi Jun 1992 A
5155823 Tsue Oct 1992 A
5177373 Nakamura Jan 1993 A
5197023 Nakayama Mar 1993 A
5197140 Balmer Mar 1993 A
5206940 Murakami et al. Apr 1993 A
5212622 Cocanougher et al. May 1993 A
5212662 Cocanougher et al. May 1993 A
5218239 Boomer Jun 1993 A
5239654 Ing-Simmons et al. Aug 1993 A
5276634 Suzuki et al. Jan 1994 A
5282153 Bartkowiak et al. Jan 1994 A
5327543 Miura et al. Jul 1994 A
5327566 Forsyth Jul 1994 A
5375080 Davies Dec 1994 A
5379240 Byrne Jan 1995 A
5386563 Thomas Jan 1995 A
5392435 Masui et al. Feb 1995 A
5418976 Iida May 1995 A
5422805 McIntyre et al. Jun 1995 A
5432943 Mitsuishi Jul 1995 A
5448703 Amini et al. Sep 1995 A
5448706 Fleming et al. Sep 1995 A
5450027 Gabara Sep 1995 A
5463749 Wertheizer et al. Oct 1995 A
5469377 Amano Nov 1995 A
5471600 Nakamoto Nov 1995 A
5497340 Uramoto et al. Mar 1996 A
5499380 Iwata et al. Mar 1996 A
5504916 Murakami et al. Apr 1996 A
5506484 Munro et al. Apr 1996 A
5517436 Andreas et al. May 1996 A
5525874 Mallarapu et al. Jun 1996 A
5548544 Matheny et al. Aug 1996 A
5561384 Reents et al. Oct 1996 A
5561619 Watanabe et al. Oct 1996 A
5564028 Swoboda et al. Oct 1996 A
5568380 Broadnax et al. Oct 1996 A
5568412 Han et al. Oct 1996 A
5596760 Ueda Jan 1997 A
5600813 Nakagawa et al. Feb 1997 A
5611061 Yasuda Mar 1997 A
5619711 Anderson Apr 1997 A
5623646 Clarke Apr 1997 A
5638524 Kiuchi et al. Jun 1997 A
5642516 Hedayat et al. Jun 1997 A
5649146 Riou Jul 1997 A
5651121 Davies Jul 1997 A
5657484 Scarrá Aug 1997 A
5659700 Chen et al. Aug 1997 A
5682339 Tam Oct 1997 A
5689693 White Nov 1997 A
5694350 Wolrich et al. Dec 1997 A
5696711 Makineni Dec 1997 A
5701493 Jaggar Dec 1997 A
5706460 Craig et al. Jan 1998 A
5706466 Dockser Jan 1998 A
5715470 Asano et al. Feb 1998 A
5737570 Koch Apr 1998 A
5740095 Parant Apr 1998 A
5740419 Potter Apr 1998 A
5740451 Muraki et al. Apr 1998 A
5748516 Goddard et al. May 1998 A
5748970 Miyaji et al. May 1998 A
5764555 McPherson et al. Jun 1998 A
5765216 Weng et al. Jun 1998 A
5765218 Ozawa et al. Jun 1998 A
5774711 Henry et al. Jun 1998 A
5778237 Yamamoto et al. Jul 1998 A
5778416 Harrison et al. Jul 1998 A
5790443 Shen et al. Aug 1998 A
5808926 Gorshtein et al. Sep 1998 A
5812439 Hansen Sep 1998 A
5812868 Moyer et al. Sep 1998 A
5815693 McDermott et al. Sep 1998 A
5825730 Nishida et al. Oct 1998 A
5826072 Knapp et al. Oct 1998 A
5826096 Baxter Oct 1998 A
5828875 Halvarsson et al. Oct 1998 A
5862065 Muthusamy Jan 1999 A
5867726 Ohsuga et al. Feb 1999 A
5875342 Temple Feb 1999 A
5880984 Burchfiel et al. Mar 1999 A
5892697 Brakefield Apr 1999 A
5892699 Duncan et al. Apr 1999 A
5894428 Harada Apr 1999 A
5900683 Rinehart et al. May 1999 A
5909385 Nishiyama et al. Jun 1999 A
5917741 Ng Jun 1999 A
5918252 Chen et al. Jun 1999 A
5930159 Wong Jul 1999 A
5930503 Drees Jul 1999 A
5936870 Im Aug 1999 A
5937199 Temple Aug 1999 A
5938759 Kamijo Aug 1999 A
5941940 Prasad et al. Aug 1999 A
5943249 Handlogten Aug 1999 A
5944816 Dutton et al. Aug 1999 A
5951627 Kiamilev et al. Sep 1999 A
5951679 Anderson et al. Sep 1999 A
5973527 Schweighofer et al. Oct 1999 A
5974549 Golan Oct 1999 A
5978825 Divine et al. Nov 1999 A
5983333 Kolagotia et al. Nov 1999 A
5991787 Abel et al. Nov 1999 A
5991868 Kamiyama et al. Nov 1999 A
5996067 White Nov 1999 A
6002234 Ohm et al. Dec 1999 A
6009454 Dummermuth Dec 1999 A
6014723 Tremblay et al. Jan 2000 A
6018757 Wong Jan 2000 A
6026489 Wachi et al. Feb 2000 A
6044392 Anderson et al. Mar 2000 A
6044434 Oliver Mar 2000 A
6049858 Kolagotia et al. Apr 2000 A
6055619 North et al. Apr 2000 A
6058409 Kozaki et al. May 2000 A
6058410 Sharangpani May 2000 A
6058464 Taylor May 2000 A
6061711 Song et al. May 2000 A
6061780 Shippey et al. May 2000 A
6061783 Harriman May 2000 A
6076154 Van Eijndhoven et al. Jun 2000 A
6084880 Bailey et al. Jul 2000 A
6101521 Kosiec Aug 2000 A
6101599 Wright et al. Aug 2000 A
6115732 Oberman et al. Sep 2000 A
6128728 Dowling Oct 2000 A
6134574 Oberman et al. Oct 2000 A
6144980 Oberman Nov 2000 A
6145049 Wong Nov 2000 A
6181151 Wasson Jan 2001 B1
6202163 Gabzdyl et al. Mar 2001 B1
6205467 Lambrecht et al. Mar 2001 B1
6209086 Chi et al. Mar 2001 B1
6243786 Huang et al. Jun 2001 B1
6243804 Cheng Jun 2001 B1
6260162 Typaldos et al. Jul 2001 B1
6282637 Chan et al. Aug 2001 B1
6292866 Zaiki et al. Sep 2001 B1
6295574 MacDonald Sep 2001 B1
6300800 Schmitt et al. Oct 2001 B1
6315200 Silverbrook et al. Nov 2001 B1
6356970 Killian et al. Mar 2002 B1
6377619 Denk et al. Apr 2002 B1
6397318 Peh May 2002 B1
6412081 Koscal et al. Jun 2002 B1
6434020 Lambert et al. Aug 2002 B1
6487654 Dowling Nov 2002 B2
6523108 James et al. Feb 2003 B1
6552625 Bowling Apr 2003 B2
6564238 Kim et al. May 2003 B1
6633970 Clift et al. Oct 2003 B1
6643150 Kawakami Nov 2003 B2
6658578 Laurenti et al. Dec 2003 B1
6681280 Miyake et al. Jan 2004 B1
6694398 Zhao et al. Feb 2004 B1
6724169 Majumdar et al. Apr 2004 B2
6728856 Grosbach et al. Apr 2004 B2
6751742 Duhault et al. Jun 2004 B1
6763478 Bui Jul 2004 B1
6819971 Alidina et al. Nov 2004 B1
20020194466 Catherwood et al. Dec 2002 A1
20030055860 Giacalone et al. Mar 2003 A1
20030093656 Masse et al. May 2003 A1
20040150439 Greenfeld Aug 2004 A1
Foreign Referenced Citations (6)
Number Date Country
0 554 917 Aug 1993 EP
0 855 643 Jul 1998 EP
0 992 888 Dec 2000 EP
0 992 889 Dec 2000 EP
01037124 Feb 1989 JP
9611443 Apr 1996 WO
Related Publications (1)
Number Date Country
20020188640 A1 Dec 2002 US