Patent Application
20070210453
The invention is directed, in general, to semiconductive devices, and more specifically, to dummy-fill-structures in these devices and the manufacture of integrated circuits having such devices.
Failure analysis is becoming an important component of integrated circuit fabrication. Failure analysis is often aided by the use of focused ion beam (FIB) tools to localize, characterize and repair prototype faulty devices. For example, FIB tools are used to mill through layers of a device to create cross-sections and electrical probe points to the area thought to have the fault. Even with the aid of such tools, however, the continuing push to produce smaller and faster semiconductive devices presents new challenges to conventional methods of failure analysis.
For instance, integrated circuits often employ a dense multilayered network of metal interconnections. The use of copper interconnections necessitates the use of chemical mechanical polishing (CMP) as part of the damascene processes used to fabricate copper wiring in the metal-containing layers (“metal layers”). To facilitate the production of a highly planar surface by CMP, it is desirable to introduce dummy-fill-structures between the copper wiring. Although the employment of dummy-fill-structures helps reduce dishing or erosion of polished layers, it also complicates any subsequent failure analysis of the device.
For example, thousands of dummy-fill-structures, many having the same sizes and shapes, can be present in a metal layer. Because such metal layers are not transparent to either optically or electron or ion beam-based microscopy, it is difficult to determine where to mill in order to create the cross-sections, the electrical probe points or modifications of the. circuit needed for the failure analysis of underlying areas. Additionally the dielectric is also not transparent to electron or ion beam microscopy. Milling through the wrong location can irreparably destroy the device, making it impossible to do failure analysis.
Accordingly, what is needed is an integrated circuit, and its method of manufacture, that employs dummy-fill-structures in a manner that addresses the drawbacks of prior art integrated circuits.
One embodiment is an integrated circuit. The integrated circuit comprises interconnects located in a layer on a semiconductor substrate. The circuit also comprises dummy-fill-structures located between the interconnects in the layer. The dummy-fill-structures form a plurality of fiducials, each of the fiducials being located in a different region of the layer. Each fiducial comprises a pre-defined recognition pattern that is different from every other fiducial in adjacent regions of the layer.
Another embodiment is a method of manufacturing an integrated circuit that comprises depositing an insulating layer over a semiconductor substrate and forming the above-described interconnects and dummy-fill-structures in the layer.
FIGS. 4 to 9 illustrate cross-section views of selected steps in an example implementation of a method of fabricating an integrated circuit of the invention.
The present invention benefits from the recognition that the design rules for placing dummy-fill-structures in a metal layer should include rules to facilitate failure analysis. It is recognized that there are higher priority design rules for placing dummy-fill-structures in a metal layer. Dummy-fill-structures are placed to minimize the topographical variations of the metal layer when subject to CMP. Dummy-fill-structures placement also should minimize any detrimental electrical or magnetic effects in the device (e.g., cross-talk, parasitic capacitances, parasitic resistances and RC delay).
While these design rules, which allow the fabrication of a functional semiconductive device, are paramount, the inventors realized that this does not exclude the introduction of additional design rules for dummy-fill-structures to facilitate the failure analysis of the device. In particular, it is desirable to arrange the dummy-fill-structure morphology or dummy-fill-structure placement to form fiducials.
The term fiducial as used herein is defined as an arrangement of one or more dummy-fill-structures to form a unique recognition pattern. The recognition pattern refers to the morphology, arrangement or electrical properties of dummy-fill-structures that makes the one arrangement of dummy-fill-structure distinguishable from another arrangement. Unique recognition patterns can be created by changing any one or all of the dummy-fill-structure's morphology, arrangement or electrical properties.
It is emphasized that the fiducials of the present invention are unrelated to fiducials used in photolithography. Rather, the fiducials here are used to aid failure analysis processing by allowing different regions of a device surface to be uniquely identified either locally or globally. The advantages in using fiducials comprising dummy-fill-structures to aid failure analysis is unexpected because previous interest in dummy-fill-structure placement in a layer has been devoted to achieving planarity in metal layers while avoiding negative electrical and magnetic consequences.
It was discovered that a plurality of fiducials could be formed in a metal layer without violating the priority design rules for dummy-fill-structure placement. The formation of such fiducials makes it easier to uniquely identify where underlying device features are located. Providing unique recognition patterns across the metal layer, or even between different metal layers, facilitates the determination of the appropriate location to conduct failure analysis, e.g., the location to start and stop FIB milling.
One embodiment is an integrated circuit.
As illustrated in
The arrangement of dummy-fill-structures in different regions to form fiducials is illustrated in
The size and shape of the regions containing the fiducials is adjusted to meet the anticipated needs of failure analysis. These regions typically will correspond to the size of the hole to be milled by a FIB tool to provide a field of view for the failure analysis of underlying device features. The size of the hole to be milled, and hence the size of the region, depend on a number of factors including: the size of the underlying devices 102, 103, the type of device fault being investigated, the capabilities of the milling tool and the number of metal layers being milled.
In some cases, each region 225-233 can be a square ranging from an about 0.1 by 0.1 micron to 200 micron by 200 micron area. E.g., for the failure analysis of transistor devices have a gate length of about 180 nanometers, a region of about 7 by 7 microns might be appropriate. However, a region of about 2 by 2 microns might be more suitable for the failure analysis of transistor devices having a gate length of about 70 nanometers.
These regions 225-233 or other regions of the layer 110 need not be square, or rectangular as depicted in
As noted above, sometimes it is sufficient for the pre-defined recognition pattern of one fiducial to be different from the fiducials in adjacent regions. That is, the unique identification of fiducials is only needed for a local area of the layer. Other times, however, it is desirable for the pre-defined recognition pattern for each of the fiducials to be different from every other fiducial in the layer. For example, fiducial 209 in region 229 (
As well as identifying specific locations within a layer, it is sometimes desirable to have fiducials that uniquely identify the layer itself. For instance, in some cases it is desirable, as part of a failure analysis investigation, to remove several metal layers of the circuit by parallel polishing. Parallel polishing, however, might planarize these layers unevenly. Consequently, several different layers can be exposed simultaneously, sometimes making it difficult to determine whether the area of interest, for the layer of interest has been exposed. Additionally, uneven parallel polishing can make it impossible to isolate one exposed layer from the another in the field of view created by milling if e.g., multiple metal layers are exposed at the same time.
As further illustrated in
Similar to layer 110, each additional fiducial, located in an additional region, comprises a pre-defined recognition pattern that is different from every other additional fiducial in adjacent regions within the additional layers 130, 132, 134. In some cases, each additional fiducial comprises a pre-defined recognition pattern that is different from every other additional fiducial in the layer. To provide inter-layer discrimination, each additional fiducial preferably is different from the fiducials in vertically adjacent regions of the additional layers. In some cases each fiducial of the layer is different from every other additional fiducial in every other additional layer.
Aspects of these embodiments are illustrated in
There are numerous ways to form the pre-defined recognition pattern of the fiducials. In some cases, the pre-defined recognition pattern comprises an ordered arrangement of one or more of the dummy-fill-structures. As illustrated in
In some embodiments, the ordered arrangement includes dummy-fill-structures that are offset from other dummy-fill-structures of the fiducial. The offset can be a-lateral offset, a vertical offset, or a combination of lateral and vertical offsets. For instance, in
The pre-defined recognition pattern can be unique locally, that is, at the sub-integrated circuit chip level, or globally, that is, at a chip-wide level. Sometimes one can use the design layout for e.g., interconnections in the layer of interest as a supplemental guide to the appropriate region of the chip. In such instances, it can be sufficient for the pre-defined recognition pattern to be locally unique. Locally unique can include, uniqueness just for adjacent fiducials, or for larger areas, within the layer 110, and in some cases, locally uniqueness between adjacent layers 132, 134 (
In other embodiments, it is the morphology of the dummy-fill-structure that is changed to form the pre-defined recognition patterns. For instance, the pre-defined recognition pattern of a fiducial can comprise one or more dummy-fill-structure whose morphology is configured to make the fiducial different than every other fiducial in adjacent regions of the layer. In some cases, every fiducial in a layer comprises one or more dummy-fill-structure having a morphology that makes the fiducial different than every other fiducial within the layer, and in some instances, different than adjacent fiducials in adjacent layers, or different than every fiducial in every layer.
Changing the morphology could include any one or more of changes to the size, shape or orientation of one or more dummy-fill-structure of a fiducial. As an example, the base shape of a square dummy-fill-structure can be modified by removing a portion of one corner or a side of one or more of the dummy-fill-structures in a fiducial. As shown in
As another example, the morphology of square dummy-fill-structures 120 of one fiducial in a region can be changed by adjusting their size as compared to, e.g., the dummy-fill-structures in another fiducial or other dummy-fill-structures within the same fiducial. As shown in
As still another example, the morphology of the square dummy-fill-structures 120, depicted in
As yet another example, altering the recognition pattern can comprise altering the electrical properties of selective ones of the dummy-fill-structures 120. By selectively electively grounding or floating dummy-fill-structures 120 within or between regions a recognition pattern can be formed. The dummy-fill-structure's electrical properties can be altered by e.g., selectively grounding one or more dummy-fill-structure 120 in a region. Consequently, when such regions are imaged via FIB or scanning electron microscopy (SEM), grounded dummy-fill-structures will provide a higher intensity signal as compared to ungrounded (or floating) dummy-fill-structures.
In some embodiments, the pre-defined recognition pattern can be formed through the absence of one or more of the dummy-fill-structures from the ordered arrangement of dummy-fill-structures. This is illustrated in
In still other embodiments, it is advantageous for the pre-defined recognition pattern of each fiducial to be substantially repeated in adjacent additional layers of the circuit 100. It is recognized that, because the layout of interconnects 144 in layer 154 is not identical to the layout of interconnects in layer 110, there are cases where the number or location of one or more of the regions 325-333, 350, 356, 365-368 will have to be altered (e.g., deleted or shifted) compared to regions 225-233, 250, 256, 265-268. However, to the extent that regions in layer 134 can have about the same location as adjacent regions in layer 110, it is desirable to repeat the pre-defined recognition pattern in the fiducials. As shown in
An advantage of repeating the pre-defined recognition patterns in the fiducials from one layer to the next is that dummy-fill-structures of one layer can be located directly above or below and contact the dummy-fill-structures of the adjacent layer. Locating dummy-fill-structures directly above and below each other between layers helps prevent dummy-fill-structures from coming out the layer during CMP. As illustrated in
Another embodiment of the invention is a method for manufacturing an integrated circuit. Any of the embodiments of the above-described integrated circuit can be manufactured by the method.
In some cases, the interconnects 140 and dummy-fill-structures 150 both comprise tungsten, titanium or combinations thereof. In other cases, the interconnects 140 and dummy-fill-structures 150 both comprise copper. Preferably, copper-containing interconnects 140 and dummy-fill-structures 150 also comprise a barrier material of e.g., tantalum nitride or silicon carbide, to prevent the diffusion of copper atoms out of these structures.
As further illustrated in
Those skilled in the art to which the invention relates will appreciate that other and further additions, deletions, substitutions and modifications may be made to the described example embodiments, without departing from the invention.
